lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 187                                             unsigned RegNo,
 188                                             uint64_t Address,
 189                                             const void *Decoder);
 190
 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 192                                        unsigned Offset,
 193                                        uint64_t Address,
 194                                        const void *Decoder);
 195
 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 197                                      unsigned Insn,
 198                                      uint64_t Address,
 199                                      const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 207                                          unsigned Offset,
 208                                          uint64_t Address,
 209                                          const void *Decoder);
 210
 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 214                                           unsigned Offset,
 215                                           uint64_t Address,
 216                                           const void *Decoder);
 217
 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 221                                            unsigned Offset,
 222                                            uint64_t Address,
 223                                            const void *Decoder);
 224
 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 228                                          unsigned Offset,
 229                                          uint64_t Address,
 230                                          const void *Decoder);
 231
 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 233 // shifted left by 1 bit.
 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 235                                        unsigned Insn,
 236                                        uint64_t Address,
 237                                        const void *Decoder);
 238
 239 static DecodeStatus DecodeMem(MCInst &Inst,
 240                               unsigned Insn,
 241                               uint64_t Address,
 242                               const void *Decoder);
 243
 244 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 245                               unsigned Insn,
 246                               uint64_t Address,
 247                               const void *Decoder);
 248
 249 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
 250                                     unsigned Insn,
 251                                     uint64_t Address,
 252                                     const void *Decoder);
 253
 254 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 255                                     unsigned Insn,
 256                                     uint64_t Address,
 257                                     const void *Decoder);
 258
 259 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
 260                                        unsigned Insn,
 261                                        uint64_t Address,
 262                                        const void *Decoder);
 263
 264 static DecodeStatus DecodeSyncI(MCInst &Inst,
 265                                 unsigned Insn,
 266                                 uint64_t Address,
 267                                 const void *Decoder);
 268
 269 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 270                                     uint64_t Address, const void *Decoder);
 271
 272 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 273                                     unsigned Insn,
 274                                     uint64_t Address,
 275                                     const void *Decoder);
 276
 277 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 278                                           unsigned Insn,
 279                                           uint64_t Address,
 280                                           const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 283                                           unsigned Insn,
 284                                           uint64_t Address,
 285                                           const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 288                                                unsigned Insn,
 289                                                uint64_t Address,
 290                                                const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 293                                     unsigned Insn,
 294                                     uint64_t Address,
 295                                     const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 298                                      unsigned Insn,
 299                                      uint64_t Address,
 300                                      const void *Decoder);
 301
 302 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 303                                      unsigned Insn,
 304                                      uint64_t Address,
 305                                      const void *Decoder);
 306
 307 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 308                                uint64_t Address,
 309                                const void *Decoder);
 310
 311 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 312                                uint64_t Address,
 313                                const void *Decoder);
 314
 315 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 316                                uint64_t Address,
 317                                const void *Decoder);
 318
 319 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 320                                uint64_t Address,
 321                                const void *Decoder);
 322
 323 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 324                                        unsigned Insn,
 325                                        uint64_t Address,
 326                                        const void *Decoder);
 327
 328 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 329                                        unsigned Value,
 330                                        uint64_t Address,
 331                                        const void *Decoder);
 332
 333 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 334                                     unsigned Value,
 335                                     uint64_t Address,
 336                                     const void *Decoder);
 337
 338 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 339                                   unsigned Value,
 340                                   uint64_t Address,
 341                                   const void *Decoder);
 342
 343 static DecodeStatus DecodeSimm4(MCInst &Inst,
 344                                 unsigned Value,
 345                                 uint64_t Address,
 346                                 const void *Decoder);
 347
 348 static DecodeStatus DecodeSimm16(MCInst &Inst,
 349                                  unsigned Insn,
 350                                  uint64_t Address,
 351                                  const void *Decoder);
 352
 353 // Decode the immediate field of an LSA instruction which
 354 // is off by one.
 355 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 356                                  unsigned Insn,
 357                                  uint64_t Address,
 358                                  const void *Decoder);
 359
 360 static DecodeStatus DecodeInsSize(MCInst &Inst,
 361                                   unsigned Insn,
 362                                   uint64_t Address,
 363                                   const void *Decoder);
 364
 365 static DecodeStatus DecodeExtSize(MCInst &Inst,
 366                                   unsigned Insn,
 367                                   uint64_t Address,
 368                                   const void *Decoder);
 369
 370 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 371                                      uint64_t Address, const void *Decoder);
 372
 373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 374                                      uint64_t Address, const void *Decoder);
 375
 376 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 377                                   uint64_t Address, const void *Decoder);
 378
 379 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 380                                     uint64_t Address, const void *Decoder);
 381
 382 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 383                                    uint64_t Address, const void *Decoder);
 384
 385 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 386                                      uint64_t Address, const void *Decoder);
 387
 388 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 389 /// handle.
 390 template <typename InsnType>
 391 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 392                                    const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                       const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                        const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 template <typename InsnType>
 410 static DecodeStatus
 411 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 412                        const void *Decoder);
 413
 414 template <typename InsnType>
 415 static DecodeStatus
 416 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 417                       const void *Decoder);
 418
 419 template <typename InsnType>
 420 static DecodeStatus
 421 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 422                        const void *Decoder);
 423
 424 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 425                                          uint64_t Address,
 426                                          const void *Decoder);
 427
 428 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 429                                            uint64_t Address,
 430                                            const void *Decoder);
 431
 432 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 433                                        uint64_t Address,
 434                                        const void *Decoder);
 435
 436 namespace llvm {
 437 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 438               TheMips64elTarget;
 439 }
 440
 441 static MCDisassembler *createMipsDisassembler(
 442                        const Target &T,
 443                        const MCSubtargetInfo &STI,
 444                        MCContext &Ctx) {
 445   return new MipsDisassembler(STI, Ctx, true);
 446 }
 447
 448 static MCDisassembler *createMipselDisassembler(
 449                        const Target &T,
 450                        const MCSubtargetInfo &STI,
 451                        MCContext &Ctx) {
 452   return new MipsDisassembler(STI, Ctx, false);
 453 }
 454
 455 extern "C" void LLVMInitializeMipsDisassembler() {
 456   // Register the disassembler.
 457   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 458                                          createMipsDisassembler);
 459   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 460                                          createMipselDisassembler);
 461   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 462                                          createMipsDisassembler);
 463   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 464                                          createMipselDisassembler);
 465 }
 466
 467 #include "MipsGenDisassemblerTables.inc"
 468
 469 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 470   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 471   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 472   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 473 }
 474
 475 template <typename InsnType>
 476 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 477                                    const void *Decoder) {
 478   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 479   // The size of the n field depends on the element size
 480   // The register class also depends on this.
 481   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 482   unsigned NSize = 0;
 483   DecodeFN RegDecoder = nullptr;
 484   if ((tmp & 0x18) == 0x00) { // INSVE_B
 485     NSize = 4;
 486     RegDecoder = DecodeMSA128BRegisterClass;
 487   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 488     NSize = 3;
 489     RegDecoder = DecodeMSA128HRegisterClass;
 490   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 491     NSize = 2;
 492     RegDecoder = DecodeMSA128WRegisterClass;
 493   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 494     NSize = 1;
 495     RegDecoder = DecodeMSA128DRegisterClass;
 496   } else
 497     llvm_unreachable("Invalid encoding");
 498
 499   assert(NSize != 0 && RegDecoder != nullptr);
 500
 501   // $wd
 502   tmp = fieldFromInstruction(insn, 6, 5);
 503   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 504     return MCDisassembler::Fail;
 505   // $wd_in
 506   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 507     return MCDisassembler::Fail;
 508   // $n
 509   tmp = fieldFromInstruction(insn, 16, NSize);
 510   MI.addOperand(MCOperand::createImm(tmp));
 511   // $ws
 512   tmp = fieldFromInstruction(insn, 11, 5);
 513   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 514     return MCDisassembler::Fail;
 515   // $n2
 516   MI.addOperand(MCOperand::createImm(0));
 517
 518   return MCDisassembler::Success;
 519 }
 520
 521 template <typename InsnType>
 522 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 523                                           uint64_t Address,
 524                                           const void *Decoder) {
 525   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 526   // (otherwise we would have matched the ADDI instruction from the earlier
 527   // ISA's instead).
 528   //
 529   // We have:
 530   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 531   //      BOVC if rs >= rt
 532   //      BEQZALC if rs == 0 && rt != 0
 533   //      BEQC if rs < rt && rs != 0
 534
 535   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 536   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 537   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 538   bool HasRs = false;
 539
 540   if (Rs >= Rt) {
 541     MI.setOpcode(Mips::BOVC);
 542     HasRs = true;
 543   } else if (Rs != 0 && Rs < Rt) {
 544     MI.setOpcode(Mips::BEQC);
 545     HasRs = true;
 546   } else
 547     MI.setOpcode(Mips::BEQZALC);
 548
 549   if (HasRs)
 550     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 551                                        Rs)));
 552
 553   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 554                                      Rt)));
 555   MI.addOperand(MCOperand::createImm(Imm));
 556
 557   return MCDisassembler::Success;
 558 }
 559
 560 template <typename InsnType>
 561 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 562                                            uint64_t Address,
 563                                            const void *Decoder) {
 564   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 565   // (otherwise we would have matched the ADDI instruction from the earlier
 566   // ISA's instead).
 567   //
 568   // We have:
 569   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 570   //      BNVC if rs >= rt
 571   //      BNEZALC if rs == 0 && rt != 0
 572   //      BNEC if rs < rt && rs != 0
 573
 574   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 575   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 576   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 577   bool HasRs = false;
 578
 579   if (Rs >= Rt) {
 580     MI.setOpcode(Mips::BNVC);
 581     HasRs = true;
 582   } else if (Rs != 0 && Rs < Rt) {
 583     MI.setOpcode(Mips::BNEC);
 584     HasRs = true;
 585   } else
 586     MI.setOpcode(Mips::BNEZALC);
 587
 588   if (HasRs)
 589     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 590                                        Rs)));
 591
 592   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 593                                      Rt)));
 594   MI.addOperand(MCOperand::createImm(Imm));
 595
 596   return MCDisassembler::Success;
 597 }
 598
 599 template <typename InsnType>
 600 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 601                                            uint64_t Address,
 602                                            const void *Decoder) {
 603   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 604   // (otherwise we would have matched the BLEZL instruction from the earlier
 605   // ISA's instead).
 606   //
 607   // We have:
 608   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 609   //      Invalid if rs == 0
 610   //      BLEZC   if rs == 0  && rt != 0
 611   //      BGEZC   if rs == rt && rt != 0
 612   //      BGEC    if rs != rt && rs != 0  && rt != 0
 613
 614   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 615   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 616   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 617   bool HasRs = false;
 618
 619   if (Rt == 0)
 620     return MCDisassembler::Fail;
 621   else if (Rs == 0)
 622     MI.setOpcode(Mips::BLEZC);
 623   else if (Rs == Rt)
 624     MI.setOpcode(Mips::BGEZC);
 625   else {
 626     HasRs = true;
 627     MI.setOpcode(Mips::BGEC);
 628   }
 629
 630   if (HasRs)
 631     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 632                                        Rs)));
 633
 634   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 635                                      Rt)));
 636
 637   MI.addOperand(MCOperand::createImm(Imm));
 638
 639   return MCDisassembler::Success;
 640 }
 641
 642 template <typename InsnType>
 643 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 644                                            uint64_t Address,
 645                                            const void *Decoder) {
 646   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 647   // (otherwise we would have matched the BGTZL instruction from the earlier
 648   // ISA's instead).
 649   //
 650   // We have:
 651   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 652   //      Invalid if rs == 0
 653   //      BGTZC   if rs == 0  && rt != 0
 654   //      BLTZC   if rs == rt && rt != 0
 655   //      BLTC    if rs != rt && rs != 0  && rt != 0
 656
 657   bool HasRs = false;
 658
 659   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 660   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 661   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 662
 663   if (Rt == 0)
 664     return MCDisassembler::Fail;
 665   else if (Rs == 0)
 666     MI.setOpcode(Mips::BGTZC);
 667   else if (Rs == Rt)
 668     MI.setOpcode(Mips::BLTZC);
 669   else {
 670     MI.setOpcode(Mips::BLTC);
 671     HasRs = true;
 672   }
 673
 674   if (HasRs)
 675     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 676                                               Rs)));
 677
 678   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 679                                      Rt)));
 680
 681   MI.addOperand(MCOperand::createImm(Imm));
 682
 683   return MCDisassembler::Success;
 684 }
 685
 686 template <typename InsnType>
 687 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 688                                           uint64_t Address,
 689                                           const void *Decoder) {
 690   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 691   // (otherwise we would have matched the BGTZ instruction from the earlier
 692   // ISA's instead).
 693   //
 694   // We have:
 695   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 696   //      BGTZ    if rt == 0
 697   //      BGTZALC if rs == 0 && rt != 0
 698   //      BLTZALC if rs != 0 && rs == rt
 699   //      BLTUC   if rs != 0 && rs != rt
 700
 701   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 702   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 703   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 704   bool HasRs = false;
 705   bool HasRt = false;
 706
 707   if (Rt == 0) {
 708     MI.setOpcode(Mips::BGTZ);
 709     HasRs = true;
 710   } else if (Rs == 0) {
 711     MI.setOpcode(Mips::BGTZALC);
 712     HasRt = true;
 713   } else if (Rs == Rt) {
 714     MI.setOpcode(Mips::BLTZALC);
 715     HasRs = true;
 716   } else {
 717     MI.setOpcode(Mips::BLTUC);
 718     HasRs = true;
 719     HasRt = true;
 720   }
 721
 722   if (HasRs)
 723     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 724                                        Rs)));
 725
 726   if (HasRt)
 727     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 728                                        Rt)));
 729
 730   MI.addOperand(MCOperand::createImm(Imm));
 731
 732   return MCDisassembler::Success;
 733 }
 734
 735 template <typename InsnType>
 736 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 737                                            uint64_t Address,
 738                                            const void *Decoder) {
 739   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 740   // (otherwise we would have matched the BLEZL instruction from the earlier
 741   // ISA's instead).
 742   //
 743   // We have:
 744   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 745   //      Invalid   if rs == 0
 746   //      BLEZALC   if rs == 0  && rt != 0
 747   //      BGEZALC   if rs == rt && rt != 0
 748   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 749
 750   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 751   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 752   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 753   bool HasRs = false;
 754
 755   if (Rt == 0)
 756     return MCDisassembler::Fail;
 757   else if (Rs == 0)
 758     MI.setOpcode(Mips::BLEZALC);
 759   else if (Rs == Rt)
 760     MI.setOpcode(Mips::BGEZALC);
 761   else {
 762     HasRs = true;
 763     MI.setOpcode(Mips::BGEUC);
 764   }
 765
 766   if (HasRs)
 767     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 768                                        Rs)));
 769   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 770                                      Rt)));
 771
 772   MI.addOperand(MCOperand::createImm(Imm));
 773
 774   return MCDisassembler::Success;
 775 }
 776
 777 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 778 /// according to the given endianess.
 779 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 780                                       uint64_t &Size, uint32_t &Insn,
 781                                       bool IsBigEndian) {
 782   // We want to read exactly 2 Bytes of data.
 783   if (Bytes.size() < 2) {
 784     Size = 0;
 785     return MCDisassembler::Fail;
 786   }
 787
 788   if (IsBigEndian) {
 789     Insn = (Bytes[0] << 8) | Bytes[1];
 790   } else {
 791     Insn = (Bytes[1] << 8) | Bytes[0];
 792   }
 793
 794   return MCDisassembler::Success;
 795 }
 796
 797 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 798 /// according to the given endianess
 799 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 800                                       uint64_t &Size, uint32_t &Insn,
 801                                       bool IsBigEndian, bool IsMicroMips) {
 802   // We want to read exactly 4 Bytes of data.
 803   if (Bytes.size() < 4) {
 804     Size = 0;
 805     return MCDisassembler::Fail;
 806   }
 807
 808   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 809   // always precede the low 16 bits in the instruction stream (that is, they
 810   // are placed at lower addresses in the instruction stream).
 811   //
 812   // microMIPS byte ordering:
 813   //   Big-endian:    0 | 1 | 2 | 3
 814   //   Little-endian: 1 | 0 | 3 | 2
 815
 816   if (IsBigEndian) {
 817     // Encoded as a big-endian 32-bit word in the stream.
 818     Insn =
 819         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 820   } else {
 821     if (IsMicroMips) {
 822       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 823              (Bytes[1] << 24);
 824     } else {
 825       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 826              (Bytes[3] << 24);
 827     }
 828   }
 829
 830   return MCDisassembler::Success;
 831 }
 832
 833 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 834                                               ArrayRef<uint8_t> Bytes,
 835                                               uint64_t Address,
 836                                               raw_ostream &VStream,
 837                                               raw_ostream &CStream) const {
 838   uint32_t Insn;
 839   DecodeStatus Result;
 840
 841   if (IsMicroMips) {
 842     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 843
 844     if (hasMips32r6()) {
 845       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
 846       // Calling the auto-generated decoder function for microMIPS32R6
 847       // (and microMIPS64R6) 16-bit instructions.
 848       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
 849                                  Address, this, STI);
 850       if (Result != MCDisassembler::Fail) {
 851         Size = 2;
 852         return Result;
 853       }
 854     }
 855
 856     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 857     // Calling the auto-generated decoder function for microMIPS 16-bit
 858     // instructions.
 859     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 860                                this, STI);
 861     if (Result != MCDisassembler::Fail) {
 862       Size = 2;
 863       return Result;
 864     }
 865
 866     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 867     if (Result == MCDisassembler::Fail)
 868       return MCDisassembler::Fail;
 869
 870     if (hasMips32r6()) {
 871       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 872       // Calling the auto-generated decoder function.
 873       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
 874                                  this, STI);
 875       if (Result != MCDisassembler::Fail) {
 876         Size = 4;
 877         return Result;
 878       }
 879     }
 880
 881     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 882     // Calling the auto-generated decoder function.
 883     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 884                                this, STI);
 885     if (Result != MCDisassembler::Fail) {
 886       Size = 4;
 887       return Result;
 888     }
 889     return MCDisassembler::Fail;
 890   }
 891
 892   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 893   if (Result == MCDisassembler::Fail)
 894     return MCDisassembler::Fail;
 895
 896   if (hasCOP3()) {
 897     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 898     Result =
 899         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 900     if (Result != MCDisassembler::Fail) {
 901       Size = 4;
 902       return Result;
 903     }
 904   }
 905
 906   if (hasMips32r6() && isGP64()) {
 907     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 908     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 909                                Address, this, STI);
 910     if (Result != MCDisassembler::Fail) {
 911       Size = 4;
 912       return Result;
 913     }
 914   }
 915
 916   if (hasMips32r6()) {
 917     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 918     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 919                                Address, this, STI);
 920     if (Result != MCDisassembler::Fail) {
 921       Size = 4;
 922       return Result;
 923     }
 924   }
 925
 926   if (hasCnMips()) {
 927     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 928     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 929                                Address, this, STI);
 930     if (Result != MCDisassembler::Fail) {
 931       Size = 4;
 932       return Result;
 933     }
 934   }
 935
 936   if (isGP64()) {
 937     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 938     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 939                                Address, this, STI);
 940     if (Result != MCDisassembler::Fail) {
 941       Size = 4;
 942       return Result;
 943     }
 944   }
 945
 946   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 947   // Calling the auto-generated decoder function.
 948   Result =
 949       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 950   if (Result != MCDisassembler::Fail) {
 951     Size = 4;
 952     return Result;
 953   }
 954
 955   return MCDisassembler::Fail;
 956 }
 957
 958 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 959                                                  unsigned RegNo,
 960                                                  uint64_t Address,
 961                                                  const void *Decoder) {
 962
 963   return MCDisassembler::Fail;
 964
 965 }
 966
 967 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 968                                              unsigned RegNo,
 969                                              uint64_t Address,
 970                                              const void *Decoder) {
 971
 972   if (RegNo > 31)
 973     return MCDisassembler::Fail;
 974
 975   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 976   Inst.addOperand(MCOperand::createReg(Reg));
 977   return MCDisassembler::Success;
 978 }
 979
 980 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 981                                                unsigned RegNo,
 982                                                uint64_t Address,
 983                                                const void *Decoder) {
 984   if (RegNo > 7)
 985     return MCDisassembler::Fail;
 986   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 987   Inst.addOperand(MCOperand::createReg(Reg));
 988   return MCDisassembler::Success;
 989 }
 990
 991 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 992                                                    unsigned RegNo,
 993                                                    uint64_t Address,
 994                                                    const void *Decoder) {
 995   if (RegNo > 7)
 996     return MCDisassembler::Fail;
 997   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 998   Inst.addOperand(MCOperand::createReg(Reg));
 999   return MCDisassembler::Success;
1000 }
1001
1002 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1003                                                     unsigned RegNo,
1004                                                     uint64_t Address,
1005                                                     const void *Decoder) {
1006   if (RegNo > 7)
1007     return MCDisassembler::Fail;
1008   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1009   Inst.addOperand(MCOperand::createReg(Reg));
1010   return MCDisassembler::Success;
1011 }
1012
1013 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1014                                              unsigned RegNo,
1015                                              uint64_t Address,
1016                                              const void *Decoder) {
1017   if (RegNo > 31)
1018     return MCDisassembler::Fail;
1019   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1020   Inst.addOperand(MCOperand::createReg(Reg));
1021   return MCDisassembler::Success;
1022 }
1023
1024 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1025                                            unsigned RegNo,
1026                                            uint64_t Address,
1027                                            const void *Decoder) {
1028   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1029     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1030
1031   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1032 }
1033
1034 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1035                                             unsigned RegNo,
1036                                             uint64_t Address,
1037                                             const void *Decoder) {
1038   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1039 }
1040
1041 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1042                                              unsigned RegNo,
1043                                              uint64_t Address,
1044                                              const void *Decoder) {
1045   if (RegNo > 31)
1046     return MCDisassembler::Fail;
1047
1048   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1049   Inst.addOperand(MCOperand::createReg(Reg));
1050   return MCDisassembler::Success;
1051 }
1052
1053 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1054                                              unsigned RegNo,
1055                                              uint64_t Address,
1056                                              const void *Decoder) {
1057   if (RegNo > 31)
1058     return MCDisassembler::Fail;
1059
1060   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1061   Inst.addOperand(MCOperand::createReg(Reg));
1062   return MCDisassembler::Success;
1063 }
1064
1065 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1066                                            unsigned RegNo,
1067                                            uint64_t Address,
1068                                            const void *Decoder) {
1069   if (RegNo > 31)
1070     return MCDisassembler::Fail;
1071   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1072   Inst.addOperand(MCOperand::createReg(Reg));
1073   return MCDisassembler::Success;
1074 }
1075
1076 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1077                                            unsigned RegNo,
1078                                            uint64_t Address,
1079                                            const void *Decoder) {
1080   if (RegNo > 7)
1081     return MCDisassembler::Fail;
1082   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1083   Inst.addOperand(MCOperand::createReg(Reg));
1084   return MCDisassembler::Success;
1085 }
1086
1087 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1088                                              uint64_t Address,
1089                                              const void *Decoder) {
1090   if (RegNo > 31)
1091     return MCDisassembler::Fail;
1092
1093   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1094   Inst.addOperand(MCOperand::createReg(Reg));
1095   return MCDisassembler::Success;
1096 }
1097
1098 static DecodeStatus DecodeMem(MCInst &Inst,
1099                               unsigned Insn,
1100                               uint64_t Address,
1101                               const void *Decoder) {
1102   int Offset = SignExtend32<16>(Insn & 0xffff);
1103   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1104   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1105
1106   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1107   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1108
1109   if(Inst.getOpcode() == Mips::SC ||
1110      Inst.getOpcode() == Mips::SCD){
1111     Inst.addOperand(MCOperand::createReg(Reg));
1112   }
1113
1114   Inst.addOperand(MCOperand::createReg(Reg));
1115   Inst.addOperand(MCOperand::createReg(Base));
1116   Inst.addOperand(MCOperand::createImm(Offset));
1117
1118   return MCDisassembler::Success;
1119 }
1120
1121 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1122                               unsigned Insn,
1123                               uint64_t Address,
1124                               const void *Decoder) {
1125   int Offset = SignExtend32<16>(Insn & 0xffff);
1126   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1127   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1128
1129   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1130
1131   Inst.addOperand(MCOperand::createReg(Base));
1132   Inst.addOperand(MCOperand::createImm(Offset));
1133   Inst.addOperand(MCOperand::createImm(Hint));
1134
1135   return MCDisassembler::Success;
1136 }
1137
1138 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1139                                     unsigned Insn,
1140                                     uint64_t Address,
1141                                     const void *Decoder) {
1142   int Offset = SignExtend32<12>(Insn & 0xfff);
1143   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1144   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1145
1146   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1147
1148   Inst.addOperand(MCOperand::createReg(Base));
1149   Inst.addOperand(MCOperand::createImm(Offset));
1150   Inst.addOperand(MCOperand::createImm(Hint));
1151
1152   return MCDisassembler::Success;
1153 }
1154
1155 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1156                                     unsigned Insn,
1157                                     uint64_t Address,
1158                                     const void *Decoder) {
1159   int Offset = fieldFromInstruction(Insn, 7, 9);
1160   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1161   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1162
1163   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1164
1165   Inst.addOperand(MCOperand::createReg(Base));
1166   Inst.addOperand(MCOperand::createImm(Offset));
1167   Inst.addOperand(MCOperand::createImm(Hint));
1168
1169   return MCDisassembler::Success;
1170 }
1171
1172 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1173                                        unsigned Insn,
1174                                        uint64_t Address,
1175                                        const void *Decoder) {
1176   int Offset = SignExtend32<9>(Insn & 0x1ff);
1177   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1178   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1179
1180   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1181   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1182
1183   Inst.addOperand(MCOperand::createReg(Reg));
1184   Inst.addOperand(MCOperand::createReg(Base));
1185   Inst.addOperand(MCOperand::createImm(Offset));
1186
1187   return MCDisassembler::Success;
1188 }
1189
1190 static DecodeStatus DecodeSyncI(MCInst &Inst,
1191                               unsigned Insn,
1192                               uint64_t Address,
1193                               const void *Decoder) {
1194   int Offset = SignExtend32<16>(Insn & 0xffff);
1195   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1196
1197   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1198
1199   Inst.addOperand(MCOperand::createReg(Base));
1200   Inst.addOperand(MCOperand::createImm(Offset));
1201
1202   return MCDisassembler::Success;
1203 }
1204
1205 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1206                                     uint64_t Address, const void *Decoder) {
1207   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1208   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1209   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1210
1211   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1212   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1213
1214   Inst.addOperand(MCOperand::createReg(Reg));
1215   Inst.addOperand(MCOperand::createReg(Base));
1216
1217   // The immediate field of an LD/ST instruction is scaled which means it must
1218   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1219   // data format.
1220   // .b - 1 byte
1221   // .h - 2 bytes
1222   // .w - 4 bytes
1223   // .d - 8 bytes
1224   switch(Inst.getOpcode())
1225   {
1226   default:
1227     assert (0 && "Unexpected instruction");
1228     return MCDisassembler::Fail;
1229     break;
1230   case Mips::LD_B:
1231   case Mips::ST_B:
1232     Inst.addOperand(MCOperand::createImm(Offset));
1233     break;
1234   case Mips::LD_H:
1235   case Mips::ST_H:
1236     Inst.addOperand(MCOperand::createImm(Offset * 2));
1237     break;
1238   case Mips::LD_W:
1239   case Mips::ST_W:
1240     Inst.addOperand(MCOperand::createImm(Offset * 4));
1241     break;
1242   case Mips::LD_D:
1243   case Mips::ST_D:
1244     Inst.addOperand(MCOperand::createImm(Offset * 8));
1245     break;
1246   }
1247
1248   return MCDisassembler::Success;
1249 }
1250
1251 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1252                                     unsigned Insn,
1253                                     uint64_t Address,
1254                                     const void *Decoder) {
1255   unsigned Offset = Insn & 0xf;
1256   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1257   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1258
1259   switch (Inst.getOpcode()) {
1260     case Mips::LBU16_MM:
1261     case Mips::LHU16_MM:
1262     case Mips::LW16_MM:
1263       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1264             == MCDisassembler::Fail)
1265         return MCDisassembler::Fail;
1266       break;
1267     case Mips::SB16_MM:
1268     case Mips::SH16_MM:
1269     case Mips::SW16_MM:
1270       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1271             == MCDisassembler::Fail)
1272         return MCDisassembler::Fail;
1273       break;
1274   }
1275
1276   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1277         == MCDisassembler::Fail)
1278     return MCDisassembler::Fail;
1279
1280   switch (Inst.getOpcode()) {
1281     case Mips::LBU16_MM:
1282       if (Offset == 0xf)
1283         Inst.addOperand(MCOperand::createImm(-1));
1284       else
1285         Inst.addOperand(MCOperand::createImm(Offset));
1286       break;
1287     case Mips::SB16_MM:
1288       Inst.addOperand(MCOperand::createImm(Offset));
1289       break;
1290     case Mips::LHU16_MM:
1291     case Mips::SH16_MM:
1292       Inst.addOperand(MCOperand::createImm(Offset << 1));
1293       break;
1294     case Mips::LW16_MM:
1295     case Mips::SW16_MM:
1296       Inst.addOperand(MCOperand::createImm(Offset << 2));
1297       break;
1298   }
1299
1300   return MCDisassembler::Success;
1301 }
1302
1303 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1304                                           unsigned Insn,
1305                                           uint64_t Address,
1306                                           const void *Decoder) {
1307   unsigned Offset = Insn & 0x1F;
1308   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1309
1310   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1311
1312   Inst.addOperand(MCOperand::createReg(Reg));
1313   Inst.addOperand(MCOperand::createReg(Mips::SP));
1314   Inst.addOperand(MCOperand::createImm(Offset << 2));
1315
1316   return MCDisassembler::Success;
1317 }
1318
1319 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1320                                           unsigned Insn,
1321                                           uint64_t Address,
1322                                           const void *Decoder) {
1323   unsigned Offset = Insn & 0x7F;
1324   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1325
1326   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1327
1328   Inst.addOperand(MCOperand::createReg(Reg));
1329   Inst.addOperand(MCOperand::createReg(Mips::GP));
1330   Inst.addOperand(MCOperand::createImm(Offset << 2));
1331
1332   return MCDisassembler::Success;
1333 }
1334
1335 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1336                                                unsigned Insn,
1337                                                uint64_t Address,
1338                                                const void *Decoder) {
1339   int Offset = SignExtend32<4>(Insn & 0xf);
1340
1341   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1342       == MCDisassembler::Fail)
1343     return MCDisassembler::Fail;
1344
1345   Inst.addOperand(MCOperand::createReg(Mips::SP));
1346   Inst.addOperand(MCOperand::createImm(Offset << 2));
1347
1348   return MCDisassembler::Success;
1349 }
1350
1351 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1352                                     unsigned Insn,
1353                                     uint64_t Address,
1354                                     const void *Decoder) {
1355   int Offset = SignExtend32<9>(Insn & 0x1ff);
1356   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1357   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1358
1359   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1360   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1361
1362   Inst.addOperand(MCOperand::createReg(Reg));
1363   Inst.addOperand(MCOperand::createReg(Base));
1364   Inst.addOperand(MCOperand::createImm(Offset));
1365
1366   return MCDisassembler::Success;
1367 }
1368
1369 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1370                                      unsigned Insn,
1371                                      uint64_t Address,
1372                                      const void *Decoder) {
1373   int Offset = SignExtend32<12>(Insn & 0x0fff);
1374   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1375   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1376
1377   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1378   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1379
1380   switch (Inst.getOpcode()) {
1381   case Mips::SWM32_MM:
1382   case Mips::LWM32_MM:
1383     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1384         == MCDisassembler::Fail)
1385       return MCDisassembler::Fail;
1386     Inst.addOperand(MCOperand::createReg(Base));
1387     Inst.addOperand(MCOperand::createImm(Offset));
1388     break;
1389   case Mips::SC_MM:
1390     Inst.addOperand(MCOperand::createReg(Reg));
1391     // fallthrough
1392   default:
1393     Inst.addOperand(MCOperand::createReg(Reg));
1394     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1395       Inst.addOperand(MCOperand::createReg(Reg+1));
1396
1397     Inst.addOperand(MCOperand::createReg(Base));
1398     Inst.addOperand(MCOperand::createImm(Offset));
1399   }
1400
1401   return MCDisassembler::Success;
1402 }
1403
1404 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1405                                      unsigned Insn,
1406                                      uint64_t Address,
1407                                      const void *Decoder) {
1408   int Offset = SignExtend32<16>(Insn & 0xffff);
1409   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1410   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1411
1412   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1413   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1414
1415   Inst.addOperand(MCOperand::createReg(Reg));
1416   Inst.addOperand(MCOperand::createReg(Base));
1417   Inst.addOperand(MCOperand::createImm(Offset));
1418
1419   return MCDisassembler::Success;
1420 }
1421
1422 static DecodeStatus DecodeFMem(MCInst &Inst,
1423                                unsigned Insn,
1424                                uint64_t Address,
1425                                const void *Decoder) {
1426   int Offset = SignExtend32<16>(Insn & 0xffff);
1427   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1428   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1429
1430   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1431   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1432
1433   Inst.addOperand(MCOperand::createReg(Reg));
1434   Inst.addOperand(MCOperand::createReg(Base));
1435   Inst.addOperand(MCOperand::createImm(Offset));
1436
1437   return MCDisassembler::Success;
1438 }
1439
1440 static DecodeStatus DecodeFMem2(MCInst &Inst,
1441                                unsigned Insn,
1442                                uint64_t Address,
1443                                const void *Decoder) {
1444   int Offset = SignExtend32<16>(Insn & 0xffff);
1445   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1446   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1447
1448   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1449   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1450
1451   Inst.addOperand(MCOperand::createReg(Reg));
1452   Inst.addOperand(MCOperand::createReg(Base));
1453   Inst.addOperand(MCOperand::createImm(Offset));
1454
1455   return MCDisassembler::Success;
1456 }
1457
1458 static DecodeStatus DecodeFMem3(MCInst &Inst,
1459                                unsigned Insn,
1460                                uint64_t Address,
1461                                const void *Decoder) {
1462   int Offset = SignExtend32<16>(Insn & 0xffff);
1463   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1464   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1465
1466   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1467   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1468
1469   Inst.addOperand(MCOperand::createReg(Reg));
1470   Inst.addOperand(MCOperand::createReg(Base));
1471   Inst.addOperand(MCOperand::createImm(Offset));
1472
1473   return MCDisassembler::Success;
1474 }
1475
1476 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1477                                     unsigned Insn,
1478                                     uint64_t Address,
1479                                     const void *Decoder) {
1480   int Offset = SignExtend32<11>(Insn & 0x07ff);
1481   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1482   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1483
1484   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1485   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1486
1487   Inst.addOperand(MCOperand::createReg(Reg));
1488   Inst.addOperand(MCOperand::createReg(Base));
1489   Inst.addOperand(MCOperand::createImm(Offset));
1490
1491   return MCDisassembler::Success;
1492 }
1493 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1494                                        unsigned Insn,
1495                                        uint64_t Address,
1496                                        const void *Decoder) {
1497   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1498   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1499   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1500
1501   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1502   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1503
1504   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1505     Inst.addOperand(MCOperand::createReg(Rt));
1506   }
1507
1508   Inst.addOperand(MCOperand::createReg(Rt));
1509   Inst.addOperand(MCOperand::createReg(Base));
1510   Inst.addOperand(MCOperand::createImm(Offset));
1511
1512   return MCDisassembler::Success;
1513 }
1514
1515 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1516                                               unsigned RegNo,
1517                                               uint64_t Address,
1518                                               const void *Decoder) {
1519   // Currently only hardware register 29 is supported.
1520   if (RegNo != 29)
1521     return  MCDisassembler::Fail;
1522   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1523   return MCDisassembler::Success;
1524 }
1525
1526 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1527                                               unsigned RegNo,
1528                                               uint64_t Address,
1529                                               const void *Decoder) {
1530   if (RegNo > 30 || RegNo %2)
1531     return MCDisassembler::Fail;
1532
1533   ;
1534   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1535   Inst.addOperand(MCOperand::createReg(Reg));
1536   return MCDisassembler::Success;
1537 }
1538
1539 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1540                                                 unsigned RegNo,
1541                                                 uint64_t Address,
1542                                                 const void *Decoder) {
1543   if (RegNo >= 4)
1544     return MCDisassembler::Fail;
1545
1546   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1547   Inst.addOperand(MCOperand::createReg(Reg));
1548   return MCDisassembler::Success;
1549 }
1550
1551 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1552                                                unsigned RegNo,
1553                                                uint64_t Address,
1554                                                const void *Decoder) {
1555   if (RegNo >= 4)
1556     return MCDisassembler::Fail;
1557
1558   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1559   Inst.addOperand(MCOperand::createReg(Reg));
1560   return MCDisassembler::Success;
1561 }
1562
1563 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1564                                                unsigned RegNo,
1565                                                uint64_t Address,
1566                                                const void *Decoder) {
1567   if (RegNo >= 4)
1568     return MCDisassembler::Fail;
1569
1570   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1571   Inst.addOperand(MCOperand::createReg(Reg));
1572   return MCDisassembler::Success;
1573 }
1574
1575 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1576                                                unsigned RegNo,
1577                                                uint64_t Address,
1578                                                const void *Decoder) {
1579   if (RegNo > 31)
1580     return MCDisassembler::Fail;
1581
1582   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1583   Inst.addOperand(MCOperand::createReg(Reg));
1584   return MCDisassembler::Success;
1585 }
1586
1587 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1588                                                unsigned RegNo,
1589                                                uint64_t Address,
1590                                                const void *Decoder) {
1591   if (RegNo > 31)
1592     return MCDisassembler::Fail;
1593
1594   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1595   Inst.addOperand(MCOperand::createReg(Reg));
1596   return MCDisassembler::Success;
1597 }
1598
1599 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1600                                                unsigned RegNo,
1601                                                uint64_t Address,
1602                                                const void *Decoder) {
1603   if (RegNo > 31)
1604     return MCDisassembler::Fail;
1605
1606   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1607   Inst.addOperand(MCOperand::createReg(Reg));
1608   return MCDisassembler::Success;
1609 }
1610
1611 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1612                                                unsigned RegNo,
1613                                                uint64_t Address,
1614                                                const void *Decoder) {
1615   if (RegNo > 31)
1616     return MCDisassembler::Fail;
1617
1618   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1619   Inst.addOperand(MCOperand::createReg(Reg));
1620   return MCDisassembler::Success;
1621 }
1622
1623 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1624                                                unsigned RegNo,
1625                                                uint64_t Address,
1626                                                const void *Decoder) {
1627   if (RegNo > 7)
1628     return MCDisassembler::Fail;
1629
1630   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1631   Inst.addOperand(MCOperand::createReg(Reg));
1632   return MCDisassembler::Success;
1633 }
1634
1635 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1636                                             unsigned RegNo,
1637                                             uint64_t Address,
1638                                             const void *Decoder) {
1639   if (RegNo > 31)
1640     return MCDisassembler::Fail;
1641
1642   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1643   Inst.addOperand(MCOperand::createReg(Reg));
1644   return MCDisassembler::Success;
1645 }
1646
1647 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1648                                             unsigned RegNo,
1649                                             uint64_t Address,
1650                                             const void *Decoder) {
1651   if (RegNo > 31)
1652     return MCDisassembler::Fail;
1653
1654   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1655   Inst.addOperand(MCOperand::createReg(Reg));
1656   return MCDisassembler::Success;
1657 }
1658
1659 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1660                                        unsigned Offset,
1661                                        uint64_t Address,
1662                                        const void *Decoder) {
1663   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1664   Inst.addOperand(MCOperand::createImm(BranchOffset));
1665   return MCDisassembler::Success;
1666 }
1667
1668 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1669                                      unsigned Insn,
1670                                      uint64_t Address,
1671                                      const void *Decoder) {
1672
1673   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1674   Inst.addOperand(MCOperand::createImm(JumpOffset));
1675   return MCDisassembler::Success;
1676 }
1677
1678 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1679                                          unsigned Offset,
1680                                          uint64_t Address,
1681                                          const void *Decoder) {
1682   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1683
1684   Inst.addOperand(MCOperand::createImm(BranchOffset));
1685   return MCDisassembler::Success;
1686 }
1687
1688 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1689                                          unsigned Offset,
1690                                          uint64_t Address,
1691                                          const void *Decoder) {
1692   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1693
1694   Inst.addOperand(MCOperand::createImm(BranchOffset));
1695   return MCDisassembler::Success;
1696 }
1697
1698 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1699                                           unsigned Offset,
1700                                           uint64_t Address,
1701                                           const void *Decoder) {
1702   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1703   Inst.addOperand(MCOperand::createImm(BranchOffset));
1704   return MCDisassembler::Success;
1705 }
1706
1707 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1708                                            unsigned Offset,
1709                                            uint64_t Address,
1710                                            const void *Decoder) {
1711   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1712   Inst.addOperand(MCOperand::createImm(BranchOffset));
1713   return MCDisassembler::Success;
1714 }
1715
1716 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1717                                          unsigned Offset,
1718                                          uint64_t Address,
1719                                          const void *Decoder) {
1720   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1721   Inst.addOperand(MCOperand::createImm(BranchOffset));
1722   return MCDisassembler::Success;
1723 }
1724
1725 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1726                                        unsigned Insn,
1727                                        uint64_t Address,
1728                                        const void *Decoder) {
1729   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1730   Inst.addOperand(MCOperand::createImm(JumpOffset));
1731   return MCDisassembler::Success;
1732 }
1733
1734 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1735                                        unsigned Value,
1736                                        uint64_t Address,
1737                                        const void *Decoder) {
1738   if (Value == 0)
1739     Inst.addOperand(MCOperand::createImm(1));
1740   else if (Value == 0x7)
1741     Inst.addOperand(MCOperand::createImm(-1));
1742   else
1743     Inst.addOperand(MCOperand::createImm(Value << 2));
1744   return MCDisassembler::Success;
1745 }
1746
1747 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1748                                     unsigned Value,
1749                                     uint64_t Address,
1750                                     const void *Decoder) {
1751   Inst.addOperand(MCOperand::createImm(Value << 2));
1752   return MCDisassembler::Success;
1753 }
1754
1755 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1756                                   unsigned Value,
1757                                   uint64_t Address,
1758                                   const void *Decoder) {
1759   if (Value == 0x7F)
1760     Inst.addOperand(MCOperand::createImm(-1));
1761   else
1762     Inst.addOperand(MCOperand::createImm(Value));
1763   return MCDisassembler::Success;
1764 }
1765
1766 static DecodeStatus DecodeSimm4(MCInst &Inst,
1767                                 unsigned Value,
1768                                 uint64_t Address,
1769                                 const void *Decoder) {
1770   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1771   return MCDisassembler::Success;
1772 }
1773
1774 static DecodeStatus DecodeSimm16(MCInst &Inst,
1775                                  unsigned Insn,
1776                                  uint64_t Address,
1777                                  const void *Decoder) {
1778   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1779   return MCDisassembler::Success;
1780 }
1781
1782 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1783                                  unsigned Insn,
1784                                  uint64_t Address,
1785                                  const void *Decoder) {
1786   // We add one to the immediate field as it was encoded as 'imm - 1'.
1787   Inst.addOperand(MCOperand::createImm(Insn + 1));
1788   return MCDisassembler::Success;
1789 }
1790
1791 static DecodeStatus DecodeInsSize(MCInst &Inst,
1792                                   unsigned Insn,
1793                                   uint64_t Address,
1794                                   const void *Decoder) {
1795   // First we need to grab the pos(lsb) from MCInst.
1796   int Pos = Inst.getOperand(2).getImm();
1797   int Size = (int) Insn - Pos + 1;
1798   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1799   return MCDisassembler::Success;
1800 }
1801
1802 static DecodeStatus DecodeExtSize(MCInst &Inst,
1803                                   unsigned Insn,
1804                                   uint64_t Address,
1805                                   const void *Decoder) {
1806   int Size = (int) Insn  + 1;
1807   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1808   return MCDisassembler::Success;
1809 }
1810
1811 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1812                                      uint64_t Address, const void *Decoder) {
1813   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1814   return MCDisassembler::Success;
1815 }
1816
1817 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1818                                      uint64_t Address, const void *Decoder) {
1819   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1820   return MCDisassembler::Success;
1821 }
1822
1823 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1824                                   uint64_t Address, const void *Decoder) {
1825   int32_t DecodedValue;
1826   switch (Insn) {
1827   case 0: DecodedValue = 256; break;
1828   case 1: DecodedValue = 257; break;
1829   case 510: DecodedValue = -258; break;
1830   case 511: DecodedValue = -257; break;
1831   default: DecodedValue = SignExtend32<9>(Insn); break;
1832   }
1833   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1834   return MCDisassembler::Success;
1835 }
1836
1837 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1838                                     uint64_t Address, const void *Decoder) {
1839   // Insn must be >= 0, since it is unsigned that condition is always true.
1840   assert(Insn < 16);
1841   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1842                              255, 32768, 65535};
1843   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1844   return MCDisassembler::Success;
1845 }
1846
1847 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1848                                     uint64_t Address, const void *Decoder) {
1849   Inst.addOperand(MCOperand::createImm(Insn << 2));
1850   return MCDisassembler::Success;
1851 }
1852
1853 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1854                                          unsigned Insn,
1855                                          uint64_t Address,
1856                                          const void *Decoder) {
1857   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1858                      Mips::S6, Mips::FP};
1859   unsigned RegNum;
1860
1861   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1862   // Empty register lists are not allowed.
1863   if (RegLst == 0)
1864     return MCDisassembler::Fail;
1865
1866   RegNum = RegLst & 0xf;
1867   for (unsigned i = 0; i < RegNum; i++)
1868     Inst.addOperand(MCOperand::createReg(Regs[i]));
1869
1870   if (RegLst & 0x10)
1871     Inst.addOperand(MCOperand::createReg(Mips::RA));
1872
1873   return MCDisassembler::Success;
1874 }
1875
1876 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1877                                            uint64_t Address,
1878                                            const void *Decoder) {
1879   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1880   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1881   unsigned RegNum = RegLst & 0x3;
1882
1883   for (unsigned i = 0; i <= RegNum; i++)
1884     Inst.addOperand(MCOperand::createReg(Regs[i]));
1885
1886   Inst.addOperand(MCOperand::createReg(Mips::RA));
1887
1888   return MCDisassembler::Success;
1889 }
1890
1891 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1892                                        uint64_t Address, const void *Decoder) {
1893
1894   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1895
1896   switch (RegPair) {
1897   default:
1898     return MCDisassembler::Fail;
1899   case 0:
1900     Inst.addOperand(MCOperand::createReg(Mips::A1));
1901     Inst.addOperand(MCOperand::createReg(Mips::A2));
1902     break;
1903   case 1:
1904     Inst.addOperand(MCOperand::createReg(Mips::A1));
1905     Inst.addOperand(MCOperand::createReg(Mips::A3));
1906     break;
1907   case 2:
1908     Inst.addOperand(MCOperand::createReg(Mips::A2));
1909     Inst.addOperand(MCOperand::createReg(Mips::A3));
1910     break;
1911   case 3:
1912     Inst.addOperand(MCOperand::createReg(Mips::A0));
1913     Inst.addOperand(MCOperand::createReg(Mips::S5));
1914     break;
1915   case 4:
1916     Inst.addOperand(MCOperand::createReg(Mips::A0));
1917     Inst.addOperand(MCOperand::createReg(Mips::S6));
1918     break;
1919   case 5:
1920     Inst.addOperand(MCOperand::createReg(Mips::A0));
1921     Inst.addOperand(MCOperand::createReg(Mips::A1));
1922     break;
1923   case 6:
1924     Inst.addOperand(MCOperand::createReg(Mips::A0));
1925     Inst.addOperand(MCOperand::createReg(Mips::A2));
1926     break;
1927   case 7:
1928     Inst.addOperand(MCOperand::createReg(Mips::A0));
1929     Inst.addOperand(MCOperand::createReg(Mips::A3));
1930     break;
1931   }
1932
1933   return MCDisassembler::Success;
1934 }
1935
1936 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1937                                      uint64_t Address, const void *Decoder) {
1938   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1939   return MCDisassembler::Success;
1940 }