1 //===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MSP430RegisterInfo.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
29 #define DEBUG_TYPE "msp430-reg-info"
31 #define GET_REGINFO_TARGET_DESC
32 #include "MSP430GenRegisterInfo.inc"
34 // FIXME: Provide proper call frame setup / destroy opcodes.
35 MSP430RegisterInfo::MSP430RegisterInfo()
36 : MSP430GenRegisterInfo(MSP430::PCW) {}
39 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 const TargetFrameLowering *TFI =
41 MF->getTarget().getSubtargetImpl()->getFrameLowering();
42 const Function* F = MF->getFunction();
43 static const MCPhysReg CalleeSavedRegs[] = {
44 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
45 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
48 static const MCPhysReg CalleeSavedRegsFP[] = {
49 MSP430::R5W, MSP430::R6W, MSP430::R7W,
50 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
53 static const MCPhysReg CalleeSavedRegsIntr[] = {
54 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
55 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
56 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
59 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
60 MSP430::R5W, MSP430::R6W, MSP430::R7W,
61 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
62 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
67 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
68 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
70 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
71 CalleeSavedRegsIntr : CalleeSavedRegs);
75 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
76 BitVector Reserved(getNumRegs());
77 const TargetFrameLowering *TFI =
78 MF.getTarget().getSubtargetImpl()->getFrameLowering();
80 // Mark 4 special registers with subregisters as reserved.
81 Reserved.set(MSP430::PCB);
82 Reserved.set(MSP430::SPB);
83 Reserved.set(MSP430::SRB);
84 Reserved.set(MSP430::CGB);
85 Reserved.set(MSP430::PCW);
86 Reserved.set(MSP430::SPW);
87 Reserved.set(MSP430::SRW);
88 Reserved.set(MSP430::CGW);
90 // Mark frame pointer as reserved if needed.
92 Reserved.set(MSP430::FPB);
93 Reserved.set(MSP430::FPW);
99 const TargetRegisterClass *
100 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
102 return &MSP430::GR16RegClass;
106 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
107 int SPAdj, unsigned FIOperandNum,
108 RegScavenger *RS) const {
109 assert(SPAdj == 0 && "Unexpected");
111 MachineInstr &MI = *II;
112 MachineBasicBlock &MBB = *MI.getParent();
113 MachineFunction &MF = *MBB.getParent();
114 const TargetFrameLowering *TFI =
115 MF.getTarget().getSubtargetImpl()->getFrameLowering();
116 DebugLoc dl = MI.getDebugLoc();
117 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
119 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
120 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
126 Offset += MF.getFrameInfo()->getStackSize();
128 Offset += 2; // Skip the saved FPW
130 // Fold imm into offset
131 Offset += MI.getOperand(FIOperandNum + 1).getImm();
133 if (MI.getOpcode() == MSP430::ADD16ri) {
134 // This is actually "load effective address" of the stack slot
135 // instruction. We have only two-address instructions, thus we need to
136 // expand it into mov + add
137 const TargetInstrInfo &TII =
138 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
140 MI.setDesc(TII.get(MSP430::MOV16rr));
141 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
146 // We need to materialize the offset via add instruction.
147 unsigned DstReg = MI.getOperand(0).getReg();
149 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
150 .addReg(DstReg).addImm(-Offset);
152 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
153 .addReg(DstReg).addImm(Offset);
158 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
159 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
162 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
163 const TargetFrameLowering *TFI =
164 MF.getTarget().getSubtargetImpl()->getFrameLowering();
166 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;