1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
27 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
28 : TargetLowering(TM) {
30 // register class for general registers
31 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
33 // register class for FP registers
34 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
36 // register class for predicate registers
37 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
39 setLoadExtAction(ISD::EXTLOAD , MVT::i1 , Promote);
41 setLoadExtAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
43 setLoadExtAction(ISD::SEXTLOAD , MVT::i1 , Promote);
44 setLoadExtAction(ISD::SEXTLOAD , MVT::i8 , Expand);
45 setLoadExtAction(ISD::SEXTLOAD , MVT::i16 , Expand);
46 setLoadExtAction(ISD::SEXTLOAD , MVT::i32 , Expand);
48 setOperationAction(ISD::BRIND , MVT::Other, Expand);
49 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
50 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
51 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
53 // ia64 uses SELECT not SELECT_CC
54 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
56 // We need to handle ISD::RET for void functions ourselves,
57 // so we get a chance to restore ar.pfs before adding a
59 setOperationAction(ISD::RET, MVT::Other, Custom);
61 setShiftAmountType(MVT::i64);
63 setOperationAction(ISD::FREM , MVT::f32 , Expand);
64 setOperationAction(ISD::FREM , MVT::f64 , Expand);
66 setOperationAction(ISD::UREM , MVT::f32 , Expand);
67 setOperationAction(ISD::UREM , MVT::f64 , Expand);
69 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
71 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
72 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
74 // We don't support sin/cos/sqrt/pow
75 setOperationAction(ISD::FSIN , MVT::f64, Expand);
76 setOperationAction(ISD::FCOS , MVT::f64, Expand);
77 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
78 setOperationAction(ISD::FPOW , MVT::f64, Expand);
79 setOperationAction(ISD::FSIN , MVT::f32, Expand);
80 setOperationAction(ISD::FCOS , MVT::f32, Expand);
81 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
82 setOperationAction(ISD::FPOW , MVT::f32, Expand);
84 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
86 // FIXME: IA64 supports fcopysign natively!
87 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
88 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
90 // We don't have line number support yet.
91 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
92 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
93 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
94 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
96 // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
97 // expansion for ctlz/cttz in terms of ctpop is much larger, but lower
99 // FIXME: Custom lower CTLZ when compiling for size?
100 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
101 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
102 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
103 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
105 // FIXME: IA64 has this, but is not implemented. should be mux @rev
106 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
108 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
109 setOperationAction(ISD::VAARG , MVT::Other, Custom);
110 setOperationAction(ISD::VASTART , MVT::Other, Custom);
112 // FIXME: These should be legal
113 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
114 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
116 // Use the default implementation.
117 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
118 setOperationAction(ISD::VAEND , MVT::Other, Expand);
119 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
120 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
121 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
123 // Thread Local Storage
124 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
126 setStackPointerRegisterToSaveRestore(IA64::r12);
128 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
129 setJumpBufAlignment(16); // ...and must be 16-byte aligned
131 computeRegisterProperties();
133 addLegalFPImmediate(APFloat(+0.0));
134 addLegalFPImmediate(APFloat(-0.0));
135 addLegalFPImmediate(APFloat(+1.0));
136 addLegalFPImmediate(APFloat(-1.0));
139 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
142 case IA64ISD::GETFD: return "IA64ISD::GETFD";
143 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
144 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
148 MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
152 /// getFunctionAlignment - Return the Log2 alignment of this function.
153 unsigned IA64TargetLowering::getFunctionAlignment(const Function *) const {
157 void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
158 SmallVectorImpl<SDValue> &ArgValues,
161 // add beautiful description of IA64 stack frame format
162 // here (from intel 24535803.pdf most likely)
164 MachineFunction &MF = DAG.getMachineFunction();
165 MachineFrameInfo *MFI = MF.getFrameInfo();
166 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
168 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
169 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
170 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
172 MachineBasicBlock& BB = MF.front();
174 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
175 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
177 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
178 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
184 unsigned used_FPArgs = 0; // how many FP args have been used so far?
186 unsigned ArgOffset = 0;
189 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
191 SDValue newroot, argt;
192 if(count < 8) { // need to fix this logic? maybe.
194 switch (getValueType(I->getType()).getSimpleVT()) {
196 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
198 // fixme? (well, will need to for weird FP structy stuff,
199 // see intel ABI docs)
201 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
202 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
203 // mark this reg as liveIn
204 // floating point args go into f8..f15 as-needed, the increment
205 argVreg[count] = // is below..:
206 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
207 // FP args go into f8..f15 as needed: (hence the ++)
208 argPreg[count] = args_FP[used_FPArgs++];
209 argOpc[count] = IA64::FMOV;
210 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl,
211 argVreg[count], MVT::f64);
212 if (I->getType() == Type::FloatTy)
213 argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
214 DAG.getIntPtrConstant(0));
216 case MVT::i1: // NOTE: as far as C abi stuff goes,
217 // bools are just boring old ints
222 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
223 MF.getRegInfo().addLiveIn(args_int[count]);
224 // mark this register as liveIn
226 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
227 argPreg[count] = args_int[count];
228 argOpc[count] = IA64::MOV;
230 DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64);
231 if ( getValueType(I->getType()) != MVT::i64)
232 argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
236 } else { // more than 8 args go into the frame
237 // Create the frame index object for this incoming parameter...
238 ArgOffset = 16 + 8 * (count - 8);
239 int FI = MFI->CreateFixedObject(8, ArgOffset);
241 // Create the SelectionDAG nodes corresponding to a load
242 //from this parameter
243 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
244 argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
245 DAG.getEntryNode(), FIN, NULL, 0);
248 DAG.setRoot(newroot.getValue(1));
249 ArgValues.push_back(argt);
253 // Create a vreg to hold the output of (what will become)
254 // the "alloc" instruction
255 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
256 BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
257 // we create a PSEUDO_ALLOC (pseudo)instruction for now
259 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
262 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
263 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
266 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
269 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
270 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
274 unsigned tempOffset=0;
276 // if this is a varargs function, we simply lower llvm.va_start by
277 // pointing to the first entry
280 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
283 // here we actually do the moving of args, and store them to the stack
284 // too if this is a varargs function:
285 for (int i = 0; i < count && i < 8; ++i) {
286 BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
288 // if this is a varargs function, we copy the input registers to the stack
289 int FI = MFI->CreateFixedObject(8, tempOffset);
290 tempOffset+=8; //XXX: is it safe to use r22 like this?
291 BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
292 // FIXME: we should use st8.spill here, one day
293 BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
297 // Finally, inform the code generator which regs we return values in.
298 // (see the ISD::RET: case in the instruction selector)
299 switch (getValueType(F.getReturnType()).getSimpleVT()) {
300 default: assert(0 && "i have no idea where to return this type!");
301 case MVT::isVoid: break;
307 MF.getRegInfo().addLiveOut(IA64::r8);
311 MF.getRegInfo().addLiveOut(IA64::F8);
316 std::pair<SDValue, SDValue>
317 IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
318 bool RetSExt, bool RetZExt, bool isVarArg,
319 bool isInreg, unsigned NumFixedArgs,
320 unsigned CallingConv,
321 bool isTailCall, SDValue Callee,
322 ArgListTy &Args, SelectionDAG &DAG,
325 MachineFunction &MF = DAG.getMachineFunction();
327 unsigned NumBytes = 16;
328 unsigned outRegsUsed = 0;
330 if (Args.size() > 8) {
331 NumBytes += (Args.size() - 8) * 8;
334 outRegsUsed = Args.size();
337 // FIXME? this WILL fail if we ever try to pass around an arg that
338 // consumes more than a single output slot (a 'real' double, int128
339 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
340 // registers we use. Hopefully, the assembler will notice.
341 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
342 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
344 // keep stack frame 16-byte aligned
345 // assert(NumBytes==((NumBytes+15) & ~15) &&
346 // "stack frame not 16-byte aligned!");
347 NumBytes = (NumBytes+15) & ~15;
349 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
352 std::vector<SDValue> Stores;
353 std::vector<SDValue> Converts;
354 std::vector<SDValue> RegValuesToPass;
355 unsigned ArgOffset = 16;
357 for (unsigned i = 0, e = Args.size(); i != e; ++i)
359 SDValue Val = Args[i].Node;
360 MVT ObjectVT = Val.getValueType();
361 SDValue ValToStore(0, 0), ValToConvert(0, 0);
363 switch (ObjectVT.getSimpleVT()) {
364 default: assert(0 && "unexpected argument type!");
369 //promote to 64-bits, sign/zero extending based on type
371 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
373 ExtendKind = ISD::SIGN_EXTEND;
374 else if (Args[i].isZExt)
375 ExtendKind = ISD::ZERO_EXTEND;
376 Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
381 if(RegValuesToPass.size() >= 8) {
384 RegValuesToPass.push_back(Val);
389 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
392 if(RegValuesToPass.size() >= 8) {
395 RegValuesToPass.push_back(Val);
396 if(1 /* TODO: if(calling external or varadic function)*/ ) {
397 ValToConvert = Val; // additionally pass this FP value as an int
403 if(ValToStore.getNode()) {
404 if(!StackPtr.getNode()) {
405 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
407 SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
408 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
409 Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
410 ArgOffset += ObjSize;
413 if(ValToConvert.getNode()) {
414 Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
415 MVT::i64, ValToConvert));
419 // Emit all stores, make sure they occur before any copies into physregs.
421 Chain = DAG.getNode(ISD::TokenFactor, dl,
422 MVT::Other, &Stores[0],Stores.size());
424 static const unsigned IntArgRegs[] = {
425 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
426 IA64::out4, IA64::out5, IA64::out6, IA64::out7
429 static const unsigned FPArgRegs[] = {
430 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
431 IA64::F12, IA64::F13, IA64::F14, IA64::F15
436 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
437 SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1,
439 Chain = GPBeforeCall.getValue(1);
440 InFlag = Chain.getValue(2);
441 SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12,
443 Chain = SPBeforeCall.getValue(1);
444 InFlag = Chain.getValue(2);
445 SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp,
447 Chain = RPBeforeCall.getValue(1);
448 InFlag = Chain.getValue(2);
450 // Build a sequence of copy-to-reg nodes chained together with token chain
451 // and flag operands which copy the outgoing integer args into regs out[0-7]
452 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
453 // TODO: for performance, we should only copy FP args into int regs when we
454 // know this is required (i.e. for varardic or external (unknown) functions)
456 // first to the FP->(integer representation) conversions, these are
457 // flagged for now, but shouldn't have to be (TODO)
458 unsigned seenConverts = 0;
459 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
460 if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
461 Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i],
462 Converts[seenConverts++], InFlag);
463 InFlag = Chain.getValue(1);
467 // next copy args into the usual places, these are flagged
468 unsigned usedFPArgs = 0;
469 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
470 Chain = DAG.getCopyToReg(Chain, dl,
471 RegValuesToPass[i].getValueType().isInteger() ?
472 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
473 InFlag = Chain.getValue(1);
476 // If the callee is a GlobalAddress node (quite common, every direct call is)
477 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
479 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
480 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
484 std::vector<MVT> NodeTys;
485 std::vector<SDValue> CallOperands;
486 NodeTys.push_back(MVT::Other); // Returns a chain
487 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
488 CallOperands.push_back(Chain);
489 CallOperands.push_back(Callee);
491 // emit the call itself
492 if (InFlag.getNode())
493 CallOperands.push_back(InFlag);
495 assert(0 && "this should never happen!\n");
497 // to make way for a hack:
498 Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
499 &CallOperands[0], CallOperands.size());
500 InFlag = Chain.getValue(1);
502 // restore the GP, SP and RP after the call
503 Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag);
504 InFlag = Chain.getValue(1);
505 Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag);
506 InFlag = Chain.getValue(1);
507 Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag);
508 InFlag = Chain.getValue(1);
510 std::vector<MVT> RetVals;
511 RetVals.push_back(MVT::Other);
512 RetVals.push_back(MVT::Flag);
514 MVT RetTyVT = getValueType(RetTy);
516 if (RetTyVT != MVT::isVoid) {
517 switch (RetTyVT.getSimpleVT()) {
518 default: assert(0 && "Unknown value type to return!");
519 case MVT::i1: { // bools are just like other integers (returned in r8)
520 // we *could* fall through to the truncate below, but this saves a
521 // few redundant predicate ops
522 SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8,
524 InFlag = boolInR8.getValue(2);
525 Chain = boolInR8.getValue(1);
526 SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0,
528 InFlag = zeroReg.getValue(2);
529 Chain = zeroReg.getValue(1);
531 RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
537 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
538 Chain = RetVal.getValue(1);
540 // keep track of whether it is sign or zero extended (todo: bools?)
542 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
543 dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
545 RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
548 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
549 Chain = RetVal.getValue(1);
550 InFlag = RetVal.getValue(2); // XXX dead
553 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
554 Chain = RetVal.getValue(1);
555 RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
556 DAG.getIntPtrConstant(0));
559 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
560 Chain = RetVal.getValue(1);
561 InFlag = RetVal.getValue(2); // XXX dead
566 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
567 DAG.getIntPtrConstant(0, true), SDValue());
568 return std::make_pair(RetVal, Chain);
571 SDValue IA64TargetLowering::
572 LowerOperation(SDValue Op, SelectionDAG &DAG) {
573 DebugLoc dl = Op.getDebugLoc();
574 switch (Op.getOpcode()) {
575 default: assert(0 && "Should not custom lower this!");
576 case ISD::GlobalTLSAddress:
577 assert(0 && "TLS not implemented for IA64.");
579 SDValue AR_PFSVal, Copy;
581 switch(Op.getNumOperands()) {
583 LLVM_UNREACHABLE("Do not know how to return this many arguments!");
585 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
586 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
588 return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal);
590 // Copy the result into the output register & restore ar.pfs
591 MVT ArgVT = Op.getOperand(1).getValueType();
592 unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
594 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
595 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg,
596 Op.getOperand(1), SDValue());
597 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl,
598 IA64::AR_PFS, AR_PFSVal, Copy.getValue(1));
599 return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other,
600 AR_PFSVal, AR_PFSVal.getValue(1));
606 MVT VT = getPointerTy();
607 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
608 SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1),
610 // Increment the pointer, VAList, to the next vaarg
611 SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList,
612 DAG.getConstant(VT.getSizeInBits()/8,
614 // Store the incremented VAList to the legalized pointer
615 VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr,
616 Op.getOperand(1), SV, 0);
617 // Load the actual argument out of the pointer VAList
618 return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0);
621 // vastart just stores the address of the VarArgsFrameIndex slot into the
622 // memory location argument.
623 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
624 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
625 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
627 // Frame & Return address. Currently unimplemented
628 case ISD::RETURNADDR: break;
629 case ISD::FRAMEADDR: break;