1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
12 //===----------------------------------------------------------------------===//
14 #include "HexagonMCInstrInfo.h"
17 #include "HexagonBaseInfo.h"
18 #include "HexagonMCChecker.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
26 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
28 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
31 void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
32 MCInstrInfo const &MCII, MCInst &MCB,
34 assert(HexagonMCInstrInfo::isBundle(MCB));
35 MCOperand const &exOp =
36 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
38 // Create the extender.
40 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
42 MCB.addOperand(MCOperand::createInst(XMCI));
45 iterator_range<MCInst::const_iterator>
46 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
47 assert(isBundle(MCI));
48 return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
51 size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
52 if (HexagonMCInstrInfo::isBundle(MCI))
53 return (MCI.size() - bundleInstructionsOffset);
58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
59 MCSubtargetInfo const &STI,
60 MCContext &Context, MCInst &MCB,
61 HexagonMCChecker *Check) {
62 // Examine the packet and convert pairs of instructions to compound
63 // instructions when possible.
64 if (!HexagonDisableCompound)
65 HexagonMCInstrInfo::tryCompound(MCII, Context, MCB);
66 // Check the bundle for errors.
67 bool CheckOk = Check ? Check->check() : true;
70 HexagonMCShuffle(MCII, STI, MCB);
71 // Examine the packet and convert pairs of instructions to duplex
72 // instructions when possible.
73 MCInst InstBundlePreDuplex = MCInst(MCB);
74 if (!HexagonDisableDuplex) {
75 SmallVector<DuplexCandidate, 8> possibleDuplexes;
76 possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);
77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);
79 // Examines packet and pad the packet, if needed, when an
80 // end-loop is in the bundle.
81 HexagonMCInstrInfo::padEndloop(Context, MCB);
82 // If compounding and duplexing didn't reduce the size below
83 // 4 or less we have a packet that is too big.
84 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
86 HexagonMCShuffle(MCII, STI, MCB);
90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
91 MCContext &Context, MCInst &MCI) {
92 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
93 HexagonMCInstrInfo::isExtended(MCII, MCI));
95 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
96 // If the extended value is a constant, then use it for the extended and
97 // for the extender instructions, masking off the lower 6 bits and
98 // including the assumed bits.
100 if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
101 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
102 exOp.setExpr(MCConstantExpr::create((Value & 0x3f) << Shift, Context));
106 MCInst HexagonMCInstrInfo::createBundle() {
108 Result.setOpcode(Hexagon::BUNDLE);
109 Result.addOperand(MCOperand::createImm(0));
113 MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
115 MCInst const &inst1) {
116 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
117 MCInst *duplexInst = new (Context) MCInst;
118 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
120 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
121 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
122 duplexInst->addOperand(MCOperand::createInst(SubInst0));
123 duplexInst->addOperand(MCOperand::createInst(SubInst1));
127 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
129 MCOperand const &MO) {
130 assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
131 HexagonMCInstrInfo::isExtended(MCII, Inst));
133 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
135 XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||
136 HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
140 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
141 else if (MO.isExpr())
142 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
144 llvm_unreachable("invalid extendable operand");
148 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
150 assert(Index <= bundleSize(MCB));
154 MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
160 void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
161 MCInstrInfo const &MCII, MCInst &MCB,
162 MCInst const &MCI, bool MustExtend) {
163 if (isConstExtended(MCII, MCI) || MustExtend)
164 addConstExtender(Context, MCII, MCB, MCI);
167 HexagonII::MemAccessSize
168 HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
169 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
171 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
172 HexagonII::MemAccesSizeMask));
175 unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII,
177 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
178 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
181 // Return constant extended operand number.
182 unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII,
184 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
185 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
188 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
190 return (MCII.get(MCI.getOpcode()));
193 unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
195 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
196 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
200 HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
202 unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
203 MCOperand const &MO = MCI.getOperand(O);
205 assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
206 HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
207 (MO.isImm() || MO.isExpr()));
211 unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
213 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
214 return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
217 unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
219 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
220 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
223 // Return the max value that a constant extendable operand can have
224 // without being extended.
225 int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
227 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
229 (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
230 unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
232 if (isSigned) // if value is signed
233 return ~(-1U << (bits - 1));
235 return ~(-1U << bits);
238 // Return the min value that a constant extendable operand can have
239 // without being extended.
240 int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
242 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
244 (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
245 unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
247 if (isSigned) // if value is signed
248 return -1U << (bits - 1);
253 char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
255 return MCII.getName(MCI.getOpcode());
258 unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
260 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
261 return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
264 MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
266 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
268 (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
269 MCOperand const &MCO = MCI.getOperand(O);
271 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
272 HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
277 /// Return the new value or the newly produced value.
278 unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
280 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
281 return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
285 HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
287 unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
288 MCOperand const &MCO = MCI.getOperand(O);
290 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
291 HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
296 int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,
298 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
300 HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>(
301 (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask);
305 return Hexagon::ArchV4;
306 case HexagonII::HasV5SubT:
307 return Hexagon::ArchV5;
311 // Return the Hexagon ISA class for the insn.
312 unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
314 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
316 return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
319 unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
320 MCSubtargetInfo const &STI,
323 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
324 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
325 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
328 bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
329 if (!HexagonMCInstrInfo::isBundle(MCI))
332 for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
333 auto MI = I.getInst();
341 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
342 return extenderForIndex(MCB, Index) != nullptr;
345 // Return whether the instruction is a legal new-value producer.
346 bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
349 return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
352 /// Return whether the insn produces a second value.
353 bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
355 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
356 return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
359 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
360 assert(isBundle(MCB));
361 assert(Index < HEXAGON_PACKET_SIZE);
362 return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
365 bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
366 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
367 assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
371 // Return whether the insn is an actual insn.
372 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
373 return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
374 !HexagonMCInstrInfo::isPrefix(MCII, MCI) &&
375 HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);
378 bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
380 return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
383 bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
384 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
385 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
388 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
389 return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
392 // Return whether the instruction needs to be constant extended.
393 // 1) Always return true if the instruction has 'isExtended' flag set.
396 // 2) For immediate extended operands, return true only if the value is
398 // 3) For global address, always return true.
400 bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
402 if (HexagonMCInstrInfo::isExtended(MCII, MCI))
404 // Branch insns are handled as necessary by relaxation.
405 if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
406 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
407 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
408 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
409 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
411 // Otherwise loop instructions and other CR insts are handled by relaxation
412 else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
413 (MCI.getOpcode() != Hexagon::C4_addipc))
415 else if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
418 MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
420 // We could be using an instruction with an extendable immediate and shoehorn
421 // a global address into it. If it is a global address it will be constant
422 // extended. We do this for COMBINE.
423 // We currently only handle isGlobal() because it is the only kind of
424 // object we are going to end up with here for now.
425 // In the future we probably should add isSymbol(), etc.
428 if (!MO.getExpr()->evaluateAsAbsolute(Value))
430 int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
431 int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
432 return (MinValue > Value || Value > MaxValue);
435 bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
437 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
438 return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
441 bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
443 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
444 return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
447 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
448 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
449 return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
452 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
453 auto Op = MCI.getOpcode();
454 return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
455 Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
458 bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
459 assert(isBundle(MCI));
460 int64_t Flags = MCI.getOperand(0).getImm();
461 return (Flags & innerLoopMask) != 0;
464 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
465 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
468 bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
469 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
470 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
473 // Return whether the insn is a new-value consumer.
474 bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
476 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
477 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
480 // Return whether the operand can be constant extended.
481 bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII,
483 unsigned short OperandNum) {
484 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
485 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
489 bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
490 assert(isBundle(MCI));
491 int64_t Flags = MCI.getOperand(0).getImm();
492 return (Flags & outerLoopMask) != 0;
495 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
497 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
498 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
501 bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
503 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
504 return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
507 /// Return whether the insn is newly predicated.
508 bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
510 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
511 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
514 bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
516 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
518 !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
521 bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
522 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
525 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
526 return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
529 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
530 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
531 return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
534 bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
535 assert(isBundle(MCI));
536 auto Flags = MCI.getOperand(0).getImm();
537 return (Flags & memReorderDisabledMask) != 0;
540 bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
541 assert(isBundle(MCI));
542 auto Flags = MCI.getOperand(0).getImm();
543 return (Flags & memStoreReorderEnabledMask) != 0;
546 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
547 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
548 return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
551 bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
553 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
554 return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
557 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
558 if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
559 (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
564 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
565 auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
567 if (MCI.size() <= Index)
569 MCOperand const &MCO = MCI.getOperand(Index);
573 if (!MCO.getExpr()->evaluateAsAbsolute(Value))
578 void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) {
580 Nop.setOpcode(Hexagon::A2_nop);
581 assert(isBundle(MCB));
582 while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
583 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
584 ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
585 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
586 MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
589 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
591 if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR)
594 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
595 switch (SchedClass) {
596 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
597 case Hexagon::Sched::ALU64_tc_2_SLOT23:
598 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
599 case Hexagon::Sched::M_tc_2_SLOT23:
600 case Hexagon::Sched::M_tc_3x_SLOT23:
601 case Hexagon::Sched::S_2op_tc_2_SLOT23:
602 case Hexagon::Sched::S_3op_tc_2_SLOT23:
603 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
609 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
610 DuplexCandidate Candidate) {
611 assert(Candidate.packetIndexI < MCB.size());
612 assert(Candidate.packetIndexJ < MCB.size());
613 assert(isBundle(MCB));
615 deriveDuplex(Context, Candidate.iClass,
616 *MCB.getOperand(Candidate.packetIndexJ).getInst(),
617 *MCB.getOperand(Candidate.packetIndexI).getInst());
618 assert(Duplex != nullptr);
619 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
620 MCB.erase(MCB.begin() + Candidate.packetIndexJ);
623 void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
624 assert(isBundle(MCI));
625 MCOperand &Operand = MCI.getOperand(0);
626 Operand.setImm(Operand.getImm() | innerLoopMask);
629 void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
630 assert(isBundle(MCI));
631 MCOperand &Operand = MCI.getOperand(0);
632 Operand.setImm(Operand.getImm() | memReorderDisabledMask);
633 assert(isMemReorderDisabled(MCI));
636 void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
637 assert(isBundle(MCI));
638 MCOperand &Operand = MCI.getOperand(0);
639 Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
640 assert(isMemStoreReorderEnabled(MCI));
643 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
644 assert(isBundle(MCI));
645 MCOperand &Operand = MCI.getOperand(0);
646 Operand.setImm(Operand.getImm() | outerLoopMask);