1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
12 //===----------------------------------------------------------------------===//
14 #include "HexagonMCInstrInfo.h"
17 #include "HexagonBaseInfo.h"
18 #include "HexagonMCChecker.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
26 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
28 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
31 void HexagonMCInstrInfo::addConstExtender(MCInstrInfo const &MCII, MCInst &MCB,
33 assert(HexagonMCInstrInfo::isBundle(MCB));
34 MCOperand const &exOp =
35 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
37 // Create the extender.
39 new MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
41 MCB.addOperand(MCOperand::createInst(XMCI));
44 iterator_range<MCInst::const_iterator>
45 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
46 assert(isBundle(MCI));
47 return iterator_range<MCInst::const_iterator>(
48 MCI.begin() + bundleInstructionsOffset, MCI.end());
51 size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
52 if (HexagonMCInstrInfo::isBundle(MCI))
53 return (MCI.size() - bundleInstructionsOffset);
58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
59 MCSubtargetInfo const &STI,
60 MCContext &Context, MCInst &MCB,
61 HexagonMCChecker *Check) {
62 // Examine the packet and convert pairs of instructions to compound
63 // instructions when possible.
64 if (!HexagonDisableCompound)
65 HexagonMCInstrInfo::tryCompound(MCII, Context, MCB);
66 // Check the bundle for errors.
67 bool CheckOk = Check ? Check->check() : true;
70 HexagonMCShuffle(MCII, STI, MCB);
71 // Examine the packet and convert pairs of instructions to duplex
72 // instructions when possible.
73 MCInst InstBundlePreDuplex = MCInst(MCB);
74 if (!HexagonDisableDuplex) {
75 SmallVector<DuplexCandidate, 8> possibleDuplexes;
76 possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);
77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);
79 // Examines packet and pad the packet, if needed, when an
80 // end-loop is in the bundle.
81 HexagonMCInstrInfo::padEndloop(MCB);
82 // If compounding and duplexing didn't reduce the size below
83 // 4 or less we have a packet that is too big.
84 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
86 HexagonMCShuffle(MCII, STI, MCB);
90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, MCInst &MCI) {
91 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
92 HexagonMCInstrInfo::isExtended(MCII, MCI));
94 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
95 // If the extended value is a constant, then use it for the extended and
96 // for the extender instructions, masking off the lower 6 bits and
97 // including the assumed bits.
99 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
100 int64_t Bits = exOp.getImm();
101 exOp.setImm((Bits & 0x3f) << Shift);
105 MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
107 MCInst const &inst1) {
108 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
109 MCInst *duplexInst = new (Context) MCInst;
110 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
112 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
113 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
114 duplexInst->addOperand(MCOperand::createInst(SubInst0));
115 duplexInst->addOperand(MCOperand::createInst(SubInst1));
119 MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
121 MCOperand const &MO) {
122 assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
123 HexagonMCInstrInfo::isExtended(MCII, Inst));
125 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
127 XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||
128 HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
132 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
133 else if (MO.isExpr())
134 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
136 llvm_unreachable("invalid extendable operand");
140 MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
142 assert(Index <= bundleSize(MCB));
146 MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
152 void HexagonMCInstrInfo::extendIfNeeded(MCInstrInfo const &MCII, MCInst &MCB,
153 MCInst const &MCI, bool MustExtend) {
154 if (isConstExtended(MCII, MCI) || MustExtend)
155 addConstExtender(MCII, MCB, MCI);
158 HexagonII::MemAccessSize
159 HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
160 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
162 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
163 HexagonII::MemAccesSizeMask));
166 unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII,
168 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
169 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
172 // Return constant extended operand number.
173 unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII,
175 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
176 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
179 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
181 return (MCII.get(MCI.getOpcode()));
184 unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
186 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
187 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
191 HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
193 unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
194 MCOperand const &MO = MCI.getOperand(O);
196 assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
197 HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
198 (MO.isImm() || MO.isExpr()));
202 unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
204 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
205 return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
208 unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
210 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
211 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
214 // Return the max value that a constant extendable operand can have
215 // without being extended.
216 int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
218 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
220 (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
221 unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
223 if (isSigned) // if value is signed
224 return ~(-1U << (bits - 1));
226 return ~(-1U << bits);
229 // Return the min value that a constant extendable operand can have
230 // without being extended.
231 int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
233 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
235 (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
236 unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
238 if (isSigned) // if value is signed
239 return -1U << (bits - 1);
244 char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
246 return MCII.getName(MCI.getOpcode());
249 unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
251 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
252 return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
255 MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
257 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
259 (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
260 MCOperand const &MCO = MCI.getOperand(O);
262 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
263 HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
268 /// Return the new value or the newly produced value.
269 unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
271 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
272 return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
276 HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
278 unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
279 MCOperand const &MCO = MCI.getOperand(O);
281 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
282 HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
287 int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,
289 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
291 HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>(
292 (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask);
296 return Hexagon::ArchV4;
297 case HexagonII::HasV5SubT:
298 return Hexagon::ArchV5;
302 // Return the Hexagon ISA class for the insn.
303 unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
305 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
307 return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
310 unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
311 MCSubtargetInfo const &STI,
314 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
315 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
316 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
319 bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
320 if (!HexagonMCInstrInfo::isBundle(MCI))
323 for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
324 auto MI = I.getInst();
332 bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
333 return extenderForIndex(MCB, Index) != nullptr;
336 // Return whether the instruction is a legal new-value producer.
337 bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
339 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
340 return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
343 /// Return whether the insn produces a second value.
344 bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
346 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
347 return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
350 MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
351 assert(isBundle(MCB));
352 assert(Index < HEXAGON_PACKET_SIZE);
353 return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
356 bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
357 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
358 assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
362 // Return whether the insn is an actual insn.
363 bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
364 return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
365 !HexagonMCInstrInfo::isPrefix(MCII, MCI) &&
366 HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);
369 bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
371 return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
374 bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
375 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
376 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
379 bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
380 return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
383 // Return whether the instruction needs to be constant extended.
384 // 1) Always return true if the instruction has 'isExtended' flag set.
387 // 2) For immediate extended operands, return true only if the value is
389 // 3) For global address, always return true.
391 bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
393 if (HexagonMCInstrInfo::isExtended(MCII, MCI))
395 // Branch insns are handled as necessary by relaxation.
396 if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
397 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
398 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
399 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
400 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
402 // Otherwise loop instructions and other CR insts are handled by relaxation
403 else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
404 (MCI.getOpcode() != Hexagon::C4_addipc))
406 else if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
409 MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
411 // We could be using an instruction with an extendable immediate and shoehorn
412 // a global address into it. If it is a global address it will be constant
413 // extended. We do this for COMBINE.
414 // We currently only handle isGlobal() because it is the only kind of
415 // object we are going to end up with here for now.
416 // In the future we probably should add isSymbol(), etc.
419 if (!MO.getExpr()->evaluateAsAbsolute(Value))
421 int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
422 int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
423 return (MinValue > Value || Value > MaxValue);
426 bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
428 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
429 return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
432 bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
434 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
435 return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
438 bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
439 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
440 return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
443 bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
444 auto Op = MCI.getOpcode();
445 return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
446 Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
449 bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
450 assert(isBundle(MCI));
451 int64_t Flags = MCI.getOperand(0).getImm();
452 return (Flags & innerLoopMask) != 0;
455 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
456 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
459 bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
460 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
461 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
464 // Return whether the insn is a new-value consumer.
465 bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
467 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
468 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
471 // Return whether the operand can be constant extended.
472 bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII,
474 unsigned short OperandNum) {
475 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
476 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
480 bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
481 assert(isBundle(MCI));
482 int64_t Flags = MCI.getOperand(0).getImm();
483 return (Flags & outerLoopMask) != 0;
486 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
488 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
489 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
492 bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
494 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
495 return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
498 /// Return whether the insn is newly predicated.
499 bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
501 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
502 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
505 bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
507 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
509 !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
512 bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
513 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
516 bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
517 return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
520 bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
521 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
522 return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
525 bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
526 assert(isBundle(MCI));
527 auto Flags = MCI.getOperand(0).getImm();
528 return (Flags & memReorderDisabledMask) != 0;
531 bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
532 assert(isBundle(MCI));
533 auto Flags = MCI.getOperand(0).getImm();
534 return (Flags & memStoreReorderEnabledMask) != 0;
537 bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
538 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
539 return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
542 bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
544 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
545 return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
548 bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
549 if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
550 (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
555 int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
556 auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
558 if (MCI.size() <= Index)
560 MCOperand const &MCO = MCI.getOperand(Index);
564 if (!MCO.getExpr()->evaluateAsAbsolute(Value))
569 void HexagonMCInstrInfo::padEndloop(MCInst &MCB) {
571 Nop.setOpcode(Hexagon::A2_nop);
572 assert(isBundle(MCB));
573 while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
574 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
575 ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
576 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
577 MCB.addOperand(MCOperand::createInst(new MCInst(Nop)));
580 bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
582 if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR)
585 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
586 switch (SchedClass) {
587 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
588 case Hexagon::Sched::ALU64_tc_2_SLOT23:
589 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
590 case Hexagon::Sched::M_tc_2_SLOT23:
591 case Hexagon::Sched::M_tc_3x_SLOT23:
592 case Hexagon::Sched::S_2op_tc_2_SLOT23:
593 case Hexagon::Sched::S_3op_tc_2_SLOT23:
594 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
600 void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
601 DuplexCandidate Candidate) {
602 assert(Candidate.packetIndexI < MCB.size());
603 assert(Candidate.packetIndexJ < MCB.size());
604 assert(isBundle(MCB));
606 deriveDuplex(Context, Candidate.iClass,
607 *MCB.getOperand(Candidate.packetIndexJ).getInst(),
608 *MCB.getOperand(Candidate.packetIndexI).getInst());
609 assert(Duplex != nullptr);
610 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
611 MCB.erase(MCB.begin() + Candidate.packetIndexJ);
614 void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
615 assert(isBundle(MCI));
616 MCOperand &Operand = MCI.getOperand(0);
617 Operand.setImm(Operand.getImm() | innerLoopMask);
620 void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
621 assert(isBundle(MCI));
622 MCOperand &Operand = MCI.getOperand(0);
623 Operand.setImm(Operand.getImm() | memReorderDisabledMask);
624 assert(isMemReorderDisabled(MCI));
627 void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
628 assert(isBundle(MCI));
629 MCOperand &Operand = MCI.getOperand(0);
630 Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
631 assert(isMemStoreReorderEnabled(MCI));
634 void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
635 assert(isBundle(MCI));
636 MCOperand &Operand = MCI.getOperand(0);
637 Operand.setImm(Operand.getImm() | outerLoopMask);