1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
53 #define DEBUG_TYPE "packets"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56 cl::ZeroOrMore, cl::Hidden, cl::init(true),
57 cl::desc("Allow non-solo packetization of volatile memory references"));
60 void initializeHexagonPacketizerPass(PassRegistry&);
65 class HexagonPacketizer : public MachineFunctionPass {
69 HexagonPacketizer() : MachineFunctionPass(ID) {
70 initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
73 void getAnalysisUsage(AnalysisUsage &AU) const override {
75 AU.addRequired<MachineDominatorTree>();
76 AU.addRequired<MachineBranchProbabilityInfo>();
77 AU.addPreserved<MachineDominatorTree>();
78 AU.addRequired<MachineLoopInfo>();
79 AU.addPreserved<MachineLoopInfo>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 const char *getPassName() const override {
84 return "Hexagon Packetizer";
87 bool runOnMachineFunction(MachineFunction &Fn) override;
89 char HexagonPacketizer::ID = 0;
91 class HexagonPacketizerList : public VLIWPacketizerList {
95 // Has the instruction been promoted to a dot-new instruction.
96 bool PromotedToDotNew;
98 // Has the instruction been glued to allocframe.
99 bool GlueAllocframeStore;
101 // Has the feeder instruction been glued to new value jump.
102 bool GlueToNewValueJump;
104 // Check if there is a dependence between some instruction already in this
105 // packet and this instruction.
108 // Only check for dependence if there are resources available to
109 // schedule this instruction.
110 bool FoundSequentialDependence;
112 /// \brief A handle to the branch probability pass.
113 const MachineBranchProbabilityInfo *MBPI;
115 // Track MIs with ignored dependece.
116 std::vector<MachineInstr*> IgnoreDepMIs;
120 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
121 MachineDominatorTree &MDT,
122 const MachineBranchProbabilityInfo *MBPI);
124 // initPacketizerState - initialize some internal flags.
125 void initPacketizerState() override;
127 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
128 bool ignorePseudoInstruction(MachineInstr *MI,
129 MachineBasicBlock *MBB) override;
131 // isSoloInstruction - return true if instruction MI can not be packetized
132 // with any other instruction, which means that MI itself is a packet.
133 bool isSoloInstruction(MachineInstr *MI) override;
135 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
137 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
139 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
141 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
143 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
145 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
146 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
147 MachineBasicBlock::iterator &MII,
148 const TargetRegisterClass* RC);
149 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
151 std::map <MachineInstr*, SUnit*> MIToSUnit,
152 MachineBasicBlock::iterator &MII,
153 const TargetRegisterClass* RC);
154 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
156 std::map <MachineInstr*, SUnit*> MIToSUnit,
157 MachineBasicBlock::iterator &MII);
158 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
160 std::map <MachineInstr*, SUnit*> MIToSUnit);
161 bool DemoteToDotOld(MachineInstr* MI);
162 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
163 std::map <MachineInstr*, SUnit*> MIToSUnit);
164 bool RestrictingDepExistInPacket(MachineInstr*,
165 unsigned, std::map <MachineInstr*, SUnit*>);
166 bool isNewifiable(MachineInstr* MI);
167 bool isCondInst(MachineInstr* MI);
168 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
169 bool canReserveResourcesForConstExt(MachineInstr *MI);
170 void reserveResourcesForConstExt(MachineInstr* MI);
171 bool isNewValueInst(MachineInstr* MI);
175 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
177 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
178 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
179 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
180 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
181 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
185 // HexagonPacketizerList Ctor.
186 HexagonPacketizerList::HexagonPacketizerList(
187 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
188 const MachineBranchProbabilityInfo *MBPI)
189 : VLIWPacketizerList(MF, MLI, MDT, true){
193 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
194 const TargetInstrInfo *TII =
195 Fn.getTarget().getSubtargetImpl()->getInstrInfo();
196 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
197 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
198 const MachineBranchProbabilityInfo *MBPI =
199 &getAnalysis<MachineBranchProbabilityInfo>();
200 // Instantiate the packetizer.
201 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
203 // DFA state table should not be empty.
204 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
207 // Loop over all basic blocks and remove KILL pseudo-instructions
208 // These instructions confuse the dependence analysis. Consider:
210 // R0 = KILL R0, D0 (Insn 1)
212 // Here, Insn 1 will result in the dependence graph not emitting an output
213 // dependence between Insn 0 and Insn 2. This can lead to incorrect
216 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
217 MBB != MBBe; ++MBB) {
218 MachineBasicBlock::iterator End = MBB->end();
219 MachineBasicBlock::iterator MI = MBB->begin();
222 MachineBasicBlock::iterator DeleteMI = MI;
224 MBB->erase(DeleteMI);
232 // Loop over all of the basic blocks.
233 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
234 MBB != MBBe; ++MBB) {
235 // Find scheduling regions and schedule / packetize each region.
236 unsigned RemainingCount = MBB->size();
237 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
238 RegionEnd != MBB->begin();) {
239 // The next region starts above the previous region. Look backward in the
240 // instruction stream until we find the nearest boundary.
241 MachineBasicBlock::iterator I = RegionEnd;
242 for(;I != MBB->begin(); --I, --RemainingCount) {
243 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
248 // Skip empty scheduling regions.
249 if (I == RegionEnd) {
250 RegionEnd = std::prev(RegionEnd);
254 // Skip regions with one instruction.
255 if (I == std::prev(RegionEnd)) {
256 RegionEnd = std::prev(RegionEnd);
260 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
269 static bool IsIndirectCall(MachineInstr* MI) {
270 return ((MI->getOpcode() == Hexagon::CALLR) ||
271 (MI->getOpcode() == Hexagon::CALLRv3));
274 // Reserve resources for constant extender. Trigure an assertion if
276 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
277 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
278 MachineFunction *MF = MI->getParent()->getParent();
279 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
282 if (ResourceTracker->canReserveResources(PseudoMI)) {
283 ResourceTracker->reserveResources(PseudoMI);
284 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
286 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
287 llvm_unreachable("can not reserve resources for constant extender.");
292 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
293 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
294 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
295 "Should only be called for constant extended instructions");
296 MachineFunction *MF = MI->getParent()->getParent();
297 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
299 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
300 MF->DeleteMachineInstr(PseudoMI);
304 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
305 // true, otherwise, return false.
306 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
307 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
308 MachineFunction *MF = MI->getParent()->getParent();
309 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
312 if (ResourceTracker->canReserveResources(PseudoMI)) {
313 ResourceTracker->reserveResources(PseudoMI);
314 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
317 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
323 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
327 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
328 const HexagonRegisterInfo *QRI =
329 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
331 // Check for lr dependence
332 if (DepReg == QRI->getRARegister()) {
336 if (QII->isDeallocRet(MI)) {
337 if (DepReg == QRI->getFrameRegister() ||
338 DepReg == QRI->getStackRegister())
342 // Check if this is a predicate dependence
343 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
344 if (RC == &Hexagon::PredRegsRegClass) {
349 // Lastly check for an operand used in an indirect call
350 // If we had an attribute for checking if an instruction is an indirect call,
351 // then we could have avoided this relatively brittle implementation of
354 // Assumes that the first operand of the CALLr is the function address
356 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
357 MachineOperand MO = MI->getOperand(0);
358 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
366 static bool IsRegDependence(const SDep::Kind DepType) {
367 return (DepType == SDep::Data || DepType == SDep::Anti ||
368 DepType == SDep::Output);
371 static bool IsDirectJump(MachineInstr* MI) {
372 return (MI->getOpcode() == Hexagon::JMP);
375 static bool IsSchedBarrier(MachineInstr* MI) {
376 switch (MI->getOpcode()) {
377 case Hexagon::BARRIER:
383 static bool IsControlFlow(MachineInstr* MI) {
384 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
387 static bool IsLoopN(MachineInstr *MI) {
388 return (MI->getOpcode() == Hexagon::LOOP0_i ||
389 MI->getOpcode() == Hexagon::LOOP0_r);
392 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
393 /// callee-saved register.
394 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
395 const TargetRegisterInfo *TRI) {
396 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
397 unsigned CalleeSavedReg = *CSR;
398 if (MI->modifiesRegister(CalleeSavedReg, TRI))
404 // Returns true if an instruction can be promoted to .new predicate
405 // or new-value store.
406 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
407 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
408 if ( isCondInst(MI) || QII->mayBeNewStore(MI))
414 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
415 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
416 const MCInstrDesc& TID = MI->getDesc();
417 // bug 5670: until that is fixed,
418 // this portion is disabled.
419 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
420 || QII->isConditionalTransfer(MI)
421 || QII->isConditionalALU32(MI)
422 || QII->isConditionalLoad(MI)
423 || QII->isConditionalStore(MI)) {
430 // Promote an instructiont to its .new form.
431 // At this time, we have already made a call to CanPromoteToDotNew
432 // and made sure that it can *indeed* be promoted.
433 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
434 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
435 const TargetRegisterClass* RC) {
437 assert (DepType == SDep::Data);
438 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
441 if (RC == &Hexagon::PredRegsRegClass)
442 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
444 NewOpcode = QII->GetDotNewOp(MI);
445 MI->setDesc(QII->get(NewOpcode));
450 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
451 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
452 int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
453 MI->setDesc(QII->get(NewOpcode));
463 /// Returns true if an instruction is predicated on p0 and false if it's
464 /// predicated on !p0.
465 static PredicateKind getPredicateSense(MachineInstr* MI,
466 const HexagonInstrInfo *QII) {
467 if (!QII->isPredicated(MI))
470 if (QII->isPredicatedTrue(MI))
476 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
477 const HexagonInstrInfo *QII) {
478 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
480 // Post Increment means duplicates. Use dense map to find duplicates in the
481 // list. Caution: Densemap initializes with the minimum of 64 buckets,
482 // whereas there are at most 5 operands in the post increment.
483 DenseMap<unsigned, unsigned> DefRegsSet;
484 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
485 if (MI->getOperand(opNum).isReg() &&
486 MI->getOperand(opNum).isDef()) {
487 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
490 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
491 if (MI->getOperand(opNum).isReg() &&
492 MI->getOperand(opNum).isUse()) {
493 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
494 return MI->getOperand(opNum);
498 if (MI->getDesc().mayLoad()) {
499 // The 2nd operand is always the post increment operand in load.
500 assert(MI->getOperand(1).isReg() &&
501 "Post increment operand has be to a register.");
502 return (MI->getOperand(1));
504 if (MI->getDesc().mayStore()) {
505 // The 1st operand is always the post increment operand in store.
506 assert(MI->getOperand(0).isReg() &&
507 "Post increment operand has be to a register.");
508 return (MI->getOperand(0));
511 // we should never come here.
512 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
515 // get the value being stored
516 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
517 // value being stored is always the last operand.
518 return (MI->getOperand(MI->getNumOperands()-1));
521 // can be new value store?
522 // Following restrictions are to be respected in convert a store into
523 // a new value store.
524 // 1. If an instruction uses auto-increment, its address register cannot
525 // be a new-value register. Arch Spec 5.4.2.1
526 // 2. If an instruction uses absolute-set addressing mode,
527 // its address register cannot be a new-value register.
528 // Arch Spec 5.4.2.1.TODO: This is not enabled as
529 // as absolute-set address mode patters are not implemented.
530 // 3. If an instruction produces a 64-bit result, its registers cannot be used
531 // as new-value registers. Arch Spec 5.4.2.2.
532 // 4. If the instruction that sets a new-value register is conditional, then
533 // the instruction that uses the new-value register must also be conditional,
534 // and both must always have their predicates evaluate identically.
535 // Arch Spec 5.4.2.3.
536 // 5. There is an implied restriction of a packet can not have another store,
537 // if there is a new value store in the packet. Corollary, if there is
538 // already a store in a packet, there can not be a new value store.
539 // Arch Spec: 3.4.4.2
540 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
541 MachineInstr *PacketMI, unsigned DepReg,
542 std::map <MachineInstr*, SUnit*> MIToSUnit) {
543 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
544 // Make sure we are looking at the store, that can be promoted.
545 if (!QII->mayBeNewStore(MI))
548 // Make sure there is dependency and can be new value'ed
549 if (GetStoreValueOperand(MI).isReg() &&
550 GetStoreValueOperand(MI).getReg() != DepReg)
553 const HexagonRegisterInfo *QRI =
554 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
555 const MCInstrDesc& MCID = PacketMI->getDesc();
556 // first operand is always the result
558 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
560 // if there is already an store in the packet, no can do new value store
561 // Arch Spec 3.4.4.2.
562 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
563 VE = CurrentPacketMIs.end();
565 SUnit* PacketSU = MIToSUnit[*VI];
566 if (PacketSU->getInstr()->getDesc().mayStore() ||
567 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
568 // then we don't need this
569 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
570 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
574 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
575 // new value store constraint: double regs can not feed into new value store
576 // arch spec section: 5.4.2.2
580 // Make sure it's NOT the post increment register that we are going to
582 if (QII->isPostIncrement(MI) &&
583 MI->getDesc().mayStore() &&
584 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
588 if (QII->isPostIncrement(PacketMI) &&
589 PacketMI->getDesc().mayLoad() &&
590 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
591 // if source is post_inc, or absolute-set addressing,
592 // it can not feed into new value store
594 // memw(r30 + #-1404) = r2.new -> can not be new value store
595 // arch spec section: 5.4.2.1
599 // If the source that feeds the store is predicated, new value store must
600 // also be predicated.
601 if (QII->isPredicated(PacketMI)) {
602 if (!QII->isPredicated(MI))
605 // Check to make sure that they both will have their predicates
606 // evaluate identically
607 unsigned predRegNumSrc = 0;
608 unsigned predRegNumDst = 0;
609 const TargetRegisterClass* predRegClass = nullptr;
611 // Get predicate register used in the source instruction
612 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
613 if ( PacketMI->getOperand(opNum).isReg())
614 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
615 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
616 if (predRegClass == &Hexagon::PredRegsRegClass) {
620 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
621 ("predicate register not found in a predicated PacketMI instruction"));
623 // Get predicate register used in new-value store instruction
624 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
625 if ( MI->getOperand(opNum).isReg())
626 predRegNumDst = MI->getOperand(opNum).getReg();
627 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
628 if (predRegClass == &Hexagon::PredRegsRegClass) {
632 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
633 ("predicate register not found in a predicated MI instruction"));
635 // New-value register producer and user (store) need to satisfy these
637 // 1) Both instructions should be predicated on the same register.
638 // 2) If producer of the new-value register is .new predicated then store
639 // should also be .new predicated and if producer is not .new predicated
640 // then store should not be .new predicated.
641 // 3) Both new-value register producer and user should have same predicate
642 // sense, i.e, either both should be negated or both should be none negated.
644 if (( predRegNumDst != predRegNumSrc) ||
645 QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
646 getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
651 // Make sure that other than the new-value register no other store instruction
652 // register has been modified in the same packet. Predicate registers can be
653 // modified by they should not be modified between the producer and the store
654 // instruction as it will make them both conditional on different values.
655 // We already know this to be true for all the instructions before and
656 // including PacketMI. Howerver, we need to perform the check for the
657 // remaining instructions in the packet.
659 std::vector<MachineInstr*>::iterator VI;
660 std::vector<MachineInstr*>::iterator VE;
661 unsigned StartCheck = 0;
663 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
665 SUnit* TempSU = MIToSUnit[*VI];
666 MachineInstr* TempMI = TempSU->getInstr();
668 // Following condition is true for all the instructions until PacketMI is
669 // reached (StartCheck is set to 0 before the for loop).
670 // StartCheck flag is 1 for all the instructions after PacketMI.
671 if (TempMI != PacketMI && !StartCheck) // start processing only after
672 continue; // encountering PacketMI
675 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
678 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
679 if (MI->getOperand(opNum).isReg() &&
680 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
686 // Make sure that for non-POST_INC stores:
687 // 1. The only use of reg is DepReg and no other registers.
688 // This handles V4 base+index registers.
689 // The following store can not be dot new.
690 // Eg. r0 = add(r0, #3)a
691 // memw(r1+r0<<#2) = r0
692 if (!QII->isPostIncrement(MI) &&
693 GetStoreValueOperand(MI).isReg() &&
694 GetStoreValueOperand(MI).getReg() == DepReg) {
695 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
696 if (MI->getOperand(opNum).isReg() &&
697 MI->getOperand(opNum).getReg() == DepReg) {
701 // 2. If data definition is because of implicit definition of the register,
702 // do not newify the store. Eg.
703 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
704 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
705 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
706 if (PacketMI->getOperand(opNum).isReg() &&
707 PacketMI->getOperand(opNum).getReg() == DepReg &&
708 PacketMI->getOperand(opNum).isDef() &&
709 PacketMI->getOperand(opNum).isImplicit()) {
715 // Can be dot new store.
719 // can this MI to promoted to either
720 // new value store or new value jump
721 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
722 SUnit *PacketSU, unsigned DepReg,
723 std::map <MachineInstr*, SUnit*> MIToSUnit,
724 MachineBasicBlock::iterator &MII)
727 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
728 const HexagonRegisterInfo *QRI =
729 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
730 if (!QRI->Subtarget.hasV4TOps() ||
731 !QII->mayBeNewStore(MI))
734 MachineInstr *PacketMI = PacketSU->getInstr();
736 // Check to see the store can be new value'ed.
737 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
740 // Check to see the compare/jump can be new value'ed.
741 // This is done as a pass on its own. Don't need to check it here.
745 // Check to see if an instruction can be dot new
746 // There are three kinds.
747 // 1. dot new on predicate - V2/V3/V4
748 // 2. dot new on stores NV/ST - V4
749 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
750 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
751 SUnit *PacketSU, unsigned DepReg,
752 std::map <MachineInstr*, SUnit*> MIToSUnit,
753 MachineBasicBlock::iterator &MII,
754 const TargetRegisterClass* RC )
756 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
757 // Already a dot new instruction.
758 if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
761 if (!isNewifiable(MI))
765 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
767 else if (RC != &Hexagon::PredRegsRegClass &&
768 !QII->mayBeNewStore(MI)) // MI is not a new-value store
771 // Create a dot new machine instruction to see if resources can be
772 // allocated. If not, bail out now.
773 int NewOpcode = QII->GetDotNewOp(MI);
774 const MCInstrDesc &desc = QII->get(NewOpcode);
776 MachineInstr *NewMI =
777 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
778 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
779 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
781 if (!ResourcesAvailable)
784 // new value store only
785 // new new value jump generated as a passes
786 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
793 // Go through the packet instructions and search for anti dependency
794 // between them and DepReg from MI
795 // Consider this case:
797 // a) %R1<def> = TFRI_cdNotPt %P3, 2
800 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
801 // c) %P3<def> = TFR_PdRs %R23
802 // d) %R1<def> = TFRI_cdnPt %P3, 4
804 // The P3 from a) and d) will be complements after
805 // a)'s P3 is converted to .new form
806 // Anti Dep between c) and b) is irrelevant for this case
807 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
809 std::map <MachineInstr*, SUnit*> MIToSUnit) {
811 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
812 SUnit* PacketSUDep = MIToSUnit[MI];
814 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
815 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
817 // We only care for dependencies to predicated instructions
818 if(!QII->isPredicated(*VIN)) continue;
820 // Scheduling Unit for current insn in the packet
821 SUnit* PacketSU = MIToSUnit[*VIN];
823 // Look at dependencies between current members of the packet
824 // and predicate defining instruction MI.
825 // Make sure that dependency is on the exact register
827 if (PacketSU->isSucc(PacketSUDep)) {
828 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
829 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
830 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
831 (PacketSU->Succs[i].getReg() == DepReg)) {
842 /// Gets the predicate register of a predicated instruction.
843 static unsigned getPredicatedRegister(MachineInstr *MI,
844 const HexagonInstrInfo *QII) {
845 /// We use the following rule: The first predicate register that is a use is
846 /// the predicate register of a predicated instruction.
848 assert(QII->isPredicated(MI) && "Must be predicated instruction");
850 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
851 OE = MI->operands_end(); OI != OE; ++OI) {
852 MachineOperand &Op = *OI;
853 if (Op.isReg() && Op.getReg() && Op.isUse() &&
854 Hexagon::PredRegsRegClass.contains(Op.getReg()))
858 llvm_unreachable("Unknown instruction operand layout");
863 // Given two predicated instructions, this function detects whether
864 // the predicates are complements
865 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
866 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
868 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
870 // If we don't know the predicate sense of the instructions bail out early, we
872 if (getPredicateSense(MI1, QII) == PK_Unknown ||
873 getPredicateSense(MI2, QII) == PK_Unknown)
876 // Scheduling unit for candidate
877 SUnit* SU = MIToSUnit[MI1];
879 // One corner case deals with the following scenario:
881 // a) %R24<def> = TFR_cPt %P0, %R25
885 // b) %R25<def> = TFR_cNotPt %P0, %R24
886 // c) %P0<def> = CMPEQri %R26, 1
889 // On general check a) and b) are complements, but
890 // presence of c) will convert a) to .new form, and
891 // then it is not a complement
892 // We attempt to detect it by analyzing existing
893 // dependencies in the packet
895 // Analyze relationships between all existing members of the packet.
896 // Look for Anti dependecy on the same predicate reg
897 // as used in the candidate
898 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
899 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
901 // Scheduling Unit for current insn in the packet
902 SUnit* PacketSU = MIToSUnit[*VIN];
904 // If this instruction in the packet is succeeded by the candidate...
905 if (PacketSU->isSucc(SU)) {
906 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
907 // The corner case exist when there is true data
908 // dependency between candidate and one of current
909 // packet members, this dep is on predicate reg, and
910 // there already exist anti dep on the same pred in
912 if (PacketSU->Succs[i].getSUnit() == SU &&
913 PacketSU->Succs[i].getKind() == SDep::Data &&
914 Hexagon::PredRegsRegClass.contains(
915 PacketSU->Succs[i].getReg()) &&
916 // Here I know that *VIN is predicate setting instruction
917 // with true data dep to candidate on the register
918 // we care about - c) in the above example.
919 // Now I need to see if there is an anti dependency
920 // from c) to any other instruction in the
921 // same packet on the pred reg of interest
922 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
930 // If the above case does not apply, check regular
931 // complement condition.
932 // Check that the predicate register is the same and
933 // that the predicate sense is different
934 // We also need to differentiate .old vs. .new:
935 // !p0 is not complimentary to p0.new
936 unsigned PReg1 = getPredicatedRegister(MI1, QII);
937 unsigned PReg2 = getPredicatedRegister(MI2, QII);
938 return ((PReg1 == PReg2) &&
939 Hexagon::PredRegsRegClass.contains(PReg1) &&
940 Hexagon::PredRegsRegClass.contains(PReg2) &&
941 (getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
942 (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
945 // initPacketizerState - Initialize packetizer flags
946 void HexagonPacketizerList::initPacketizerState() {
949 PromotedToDotNew = false;
950 GlueToNewValueJump = false;
951 GlueAllocframeStore = false;
952 FoundSequentialDependence = false;
957 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
958 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
959 MachineBasicBlock *MBB) {
960 if (MI->isDebugValue())
963 // We must print out inline assembly
964 if (MI->isInlineAsm())
967 // We check if MI has any functional units mapped to it.
968 // If it doesn't, we ignore the instruction.
969 const MCInstrDesc& TID = MI->getDesc();
970 unsigned SchedClass = TID.getSchedClass();
971 const InstrStage* IS =
972 ResourceTracker->getInstrItins()->beginStage(SchedClass);
973 unsigned FuncUnits = IS->getUnits();
977 // isSoloInstruction: - Returns true for instructions that must be
978 // scheduled in their own packet.
979 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
981 if (MI->isInlineAsm())
987 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
988 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
989 // They must not be grouped with other instructions in a packet.
990 if (IsSchedBarrier(MI))
996 // isLegalToPacketizeTogether:
997 // SUI is the current instruction that is out side of the current packet.
998 // SUJ is the current instruction inside the current packet against which that
999 // SUI will be packetized.
1000 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
1001 MachineInstr *I = SUI->getInstr();
1002 MachineInstr *J = SUJ->getInstr();
1003 assert(I && J && "Unable to packetize null instruction!");
1005 const MCInstrDesc &MCIDI = I->getDesc();
1006 const MCInstrDesc &MCIDJ = J->getDesc();
1008 MachineBasicBlock::iterator II = I;
1010 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1011 const HexagonRegisterInfo *QRI =
1012 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
1013 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1015 // Inline asm cannot go in the packet.
1016 if (I->getOpcode() == Hexagon::INLINEASM)
1017 llvm_unreachable("Should not meet inline asm here!");
1019 if (isSoloInstruction(I))
1020 llvm_unreachable("Should not meet solo instr here!");
1022 // A save callee-save register function call can only be in a packet
1023 // with instructions that don't write to the callee-save registers.
1024 if ((QII->isSaveCalleeSavedRegsCall(I) &&
1025 DoesModifyCalleeSavedReg(J, QRI)) ||
1026 (QII->isSaveCalleeSavedRegsCall(J) &&
1027 DoesModifyCalleeSavedReg(I, QRI))) {
1032 // Two control flow instructions cannot go in the same packet.
1033 if (IsControlFlow(I) && IsControlFlow(J)) {
1038 // A LoopN instruction cannot appear in the same packet as a jump or call.
1040 (IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
1045 (IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
1050 // dealloc_return cannot appear in the same packet as a conditional or
1051 // unconditional jump.
1052 if (QII->isDeallocRet(I) &&
1053 (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
1059 // V4 allows dual store. But does not allow second store, if the
1060 // first store is not in SLOT0. New value store, new value jump,
1061 // dealloc_return and memop always take SLOT0.
1062 // Arch spec 3.4.4.2
1063 if (QRI->Subtarget.hasV4TOps()) {
1064 if (MCIDI.mayStore() && MCIDJ.mayStore() &&
1065 (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
1070 if ((QII->isMemOp(J) && MCIDI.mayStore())
1071 || (MCIDJ.mayStore() && QII->isMemOp(I))
1072 || (QII->isMemOp(J) && QII->isMemOp(I))) {
1078 if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
1083 // If an instruction feeds new value jump, glue it.
1084 MachineBasicBlock::iterator NextMII = I;
1086 if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
1087 MachineInstr *NextMI = NextMII;
1089 bool secondRegMatch = false;
1090 bool maintainNewValueJump = false;
1092 if (NextMI->getOperand(1).isReg() &&
1093 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
1094 secondRegMatch = true;
1095 maintainNewValueJump = true;
1098 if (!secondRegMatch &&
1099 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
1100 maintainNewValueJump = true;
1103 for (std::vector<MachineInstr*>::iterator
1104 VI = CurrentPacketMIs.begin(),
1105 VE = CurrentPacketMIs.end();
1106 (VI != VE && maintainNewValueJump); ++VI) {
1107 SUnit* PacketSU = MIToSUnit[*VI];
1109 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
1110 if (PacketSU->getInstr()->getDesc().isCall()) {
1115 // 1. Packet does not have a store in it.
1116 // 2. If the first operand of the nvj is newified, and the second
1117 // operand is also a reg, it (second reg) is not defined in
1119 // 3. If the second operand of the nvj is newified, (which means
1120 // first operand is also a reg), first reg is not defined in
1122 if (PacketSU->getInstr()->getDesc().mayStore() ||
1123 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
1125 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
1126 PacketSU->getInstr()->modifiesRegister(
1127 NextMI->getOperand(1).getReg(), QRI)) ||
1130 PacketSU->getInstr()->modifiesRegister(
1131 NextMI->getOperand(0).getReg(), QRI))) {
1137 GlueToNewValueJump = true;
1143 if (SUJ->isSucc(SUI)) {
1144 for (unsigned i = 0;
1145 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
1148 if (SUJ->Succs[i].getSUnit() != SUI) {
1152 SDep::Kind DepType = SUJ->Succs[i].getKind();
1154 // For direct calls:
1155 // Ignore register dependences for call instructions for
1156 // packetization purposes except for those due to r31 and
1157 // predicate registers.
1159 // For indirect calls:
1160 // Same as direct calls + check for true dependences to the register
1161 // used in the indirect call.
1163 // We completely ignore Order dependences for call instructions
1166 // Ignore register dependences for return instructions like jumpr,
1167 // dealloc return unless we have dependencies on the explicit uses
1168 // of the registers used by jumpr (like r31) or dealloc return
1169 // (like r29 or r30).
1171 // TODO: Currently, jumpr is handling only return of r31. So, the
1172 // following logic (specificaly IsCallDependent) is working fine.
1173 // We need to enable jumpr for register other than r31 and then,
1174 // we need to rework the last part, where it handles indirect call
1175 // of that (IsCallDependent) function. Bug 6216 is opened for this.
1177 unsigned DepReg = 0;
1178 const TargetRegisterClass* RC = nullptr;
1179 if (DepType == SDep::Data) {
1180 DepReg = SUJ->Succs[i].getReg();
1181 RC = QRI->getMinimalPhysRegClass(DepReg);
1183 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
1184 (!IsRegDependence(DepType) ||
1185 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
1189 // For instructions that can be promoted to dot-new, try to promote.
1190 else if ((DepType == SDep::Data) &&
1191 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
1192 PromoteToDotNew(I, DepType, II, RC)) {
1193 PromotedToDotNew = true;
1197 else if ((DepType == SDep::Data) &&
1198 (QII->isNewValueJump(I))) {
1202 // For predicated instructions, if the predicates are complements
1203 // then there can be no dependence.
1204 else if (QII->isPredicated(I) &&
1205 QII->isPredicated(J) &&
1206 ArePredicatesComplements(I, J, MIToSUnit)) {
1210 else if (IsDirectJump(I) &&
1211 !MCIDJ.isBranch() &&
1213 (DepType == SDep::Order)) {
1214 // Ignore Order dependences between unconditional direct branches
1215 // and non-control-flow instructions
1218 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
1219 (DepType != SDep::Output)) {
1220 // Ignore all dependences for jumps except for true and output
1225 // Ignore output dependences due to superregs. We can
1226 // write to two different subregisters of R1:0 for instance
1227 // in the same cycle
1232 // If neither I nor J defines DepReg, then this is a
1233 // superfluous output dependence. The dependence must be of the
1237 // and there is an output dependence between the two instructions
1240 // We want to ignore these dependences.
1241 // Ideally, the dependence constructor should annotate such
1242 // dependences. We can then avoid this relatively expensive check.
1244 else if (DepType == SDep::Output) {
1245 // DepReg is the register that's responsible for the dependence.
1246 unsigned DepReg = SUJ->Succs[i].getReg();
1248 // Check if I and J really defines DepReg.
1249 if (I->definesRegister(DepReg) ||
1250 J->definesRegister(DepReg)) {
1251 FoundSequentialDependence = true;
1256 // We ignore Order dependences for
1257 // 1. Two loads unless they are volatile.
1258 // 2. Two stores in V4 unless they are volatile.
1259 else if ((DepType == SDep::Order) &&
1260 !I->hasOrderedMemoryRef() &&
1261 !J->hasOrderedMemoryRef()) {
1262 if (QRI->Subtarget.hasV4TOps() &&
1263 // hexagonv4 allows dual store.
1264 MCIDI.mayStore() && MCIDJ.mayStore()) {
1267 // store followed by store-- not OK on V2
1268 // store followed by load -- not OK on all (OK if addresses
1270 // load followed by store -- OK on all
1271 // load followed by load -- OK on all
1272 else if ( !MCIDJ.mayStore()) {
1276 FoundSequentialDependence = true;
1281 // For V4, special case ALLOCFRAME. Even though there is dependency
1282 // between ALLOCAFRAME and subsequent store, allow it to be
1283 // packetized in a same packet. This implies that the store is using
1284 // caller's SP. Hense, offset needs to be updated accordingly.
1285 else if (DepType == SDep::Data
1286 && QRI->Subtarget.hasV4TOps()
1287 && J->getOpcode() == Hexagon::ALLOCFRAME
1288 && (I->getOpcode() == Hexagon::STrid
1289 || I->getOpcode() == Hexagon::STriw
1290 || I->getOpcode() == Hexagon::STrib)
1291 && I->getOperand(0).getReg() == QRI->getStackRegister()
1292 && QII->isValidOffset(I->getOpcode(),
1293 I->getOperand(1).getImm() -
1294 (FrameSize + HEXAGON_LRFP_SIZE)))
1296 GlueAllocframeStore = true;
1297 // Since this store is to be glued with allocframe in the same
1298 // packet, it will use SP of the previous stack frame, i.e
1299 // caller's SP. Therefore, we need to recalculate offset according
1301 I->getOperand(1).setImm(I->getOperand(1).getImm() -
1302 (FrameSize + HEXAGON_LRFP_SIZE));
1306 // Skip over anti-dependences. Two instructions that are
1307 // anti-dependent can share a packet
1309 else if (DepType != SDep::Anti) {
1310 FoundSequentialDependence = true;
1315 if (FoundSequentialDependence) {
1324 // isLegalToPruneDependencies
1325 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1326 MachineInstr *I = SUI->getInstr();
1327 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
1329 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1333 // Check if the instruction was promoted to a dot-new. If so, demote it
1334 // back into a dot-old.
1335 if (PromotedToDotNew) {
1339 // Check if the instruction (must be a store) was glued with an Allocframe
1340 // instruction. If so, restore its offset to its original value, i.e. use
1341 // curent SP instead of caller's SP.
1342 if (GlueAllocframeStore) {
1343 I->getOperand(1).setImm(I->getOperand(1).getImm() +
1344 FrameSize + HEXAGON_LRFP_SIZE);
1352 MachineBasicBlock::iterator
1353 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
1355 MachineBasicBlock::iterator MII = MI;
1356 MachineBasicBlock *MBB = MI->getParent();
1358 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1360 if (GlueToNewValueJump) {
1363 MachineInstr *nvjMI = MII;
1364 assert(ResourceTracker->canReserveResources(MI));
1365 ResourceTracker->reserveResources(MI);
1366 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
1367 !tryAllocateResourcesForConstExt(MI)) {
1369 ResourceTracker->reserveResources(MI);
1370 assert(canReserveResourcesForConstExt(MI) &&
1371 "Ensure that there is a slot");
1372 reserveResourcesForConstExt(MI);
1373 // Reserve resources for new value jump constant extender.
1374 assert(canReserveResourcesForConstExt(MI) &&
1375 "Ensure that there is a slot");
1376 reserveResourcesForConstExt(nvjMI);
1377 assert(ResourceTracker->canReserveResources(nvjMI) &&
1378 "Ensure that there is a slot");
1380 } else if ( // Extended instruction takes two slots in the packet.
1381 // Try reserve and allocate 4-byte in the current packet first.
1382 (QII->isExtended(nvjMI)
1383 && (!tryAllocateResourcesForConstExt(nvjMI)
1384 || !ResourceTracker->canReserveResources(nvjMI)))
1385 || // For non-extended instruction, no need to allocate extra 4 bytes.
1386 (!QII->isExtended(nvjMI) &&
1387 !ResourceTracker->canReserveResources(nvjMI)))
1390 // A new and empty packet starts.
1391 // We are sure that the resources requirements can be satisfied.
1392 // Therefore, do not need to call "canReserveResources" anymore.
1393 ResourceTracker->reserveResources(MI);
1394 if (QII->isExtended(nvjMI))
1395 reserveResourcesForConstExt(nvjMI);
1397 // Here, we are sure that "reserveResources" would succeed.
1398 ResourceTracker->reserveResources(nvjMI);
1399 CurrentPacketMIs.push_back(MI);
1400 CurrentPacketMIs.push_back(nvjMI);
1402 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
1403 && ( !tryAllocateResourcesForConstExt(MI)
1404 || !ResourceTracker->canReserveResources(MI)))
1407 // Check if the instruction was promoted to a dot-new. If so, demote it
1408 // back into a dot-old
1409 if (PromotedToDotNew) {
1412 reserveResourcesForConstExt(MI);
1414 // In case that "MI" is not an extended insn,
1415 // the resource availability has already been checked.
1416 ResourceTracker->reserveResources(MI);
1417 CurrentPacketMIs.push_back(MI);
1422 //===----------------------------------------------------------------------===//
1423 // Public Constructor Functions
1424 //===----------------------------------------------------------------------===//
1426 FunctionPass *llvm::createHexagonPacketizer() {
1427 return new HexagonPacketizer();