1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
32 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon MI Scheduling"));
36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37 cl::Hidden, cl::ZeroOrMore, cl::init(false),
38 cl::desc("Disable Hexagon CFG Optimization"));
41 /// HexagonTargetMachineModule - Note that this is used on hosts that
42 /// cannot link in a library unless there are references into the
43 /// library. In particular, it seems that it is not possible to get
44 /// things to work on Win32 without this. Though it is unused, do not
46 extern "C" int HexagonTargetMachineModule;
47 int HexagonTargetMachineModule = 0;
49 extern "C" void LLVMInitializeHexagonTarget() {
50 // Register the target.
51 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
54 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
55 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
58 static MachineSchedRegistry
59 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
60 createVLIWMachineSched);
62 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
65 /// Hexagon_TODO: Do I need an aggregate alignment?
67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
68 StringRef CPU, StringRef FS,
69 const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS),
74 InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this),
80 /// Hexagon Code Generator Pass Configuration Options.
81 class HexagonPassConfig : public TargetPassConfig {
83 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
84 : TargetPassConfig(TM, PM) {
85 // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
86 // HexagonSubtarget::enableMachineScheduler() { return true; }.
87 // That will bypass the SelectionDAG VLIW scheduler, which is probably just
88 // hurting compile time and will be removed eventually anyway.
89 if (DisableHexagonMISched)
90 disablePass(&MachineSchedulerID);
92 enablePass(&MachineSchedulerID);
95 HexagonTargetMachine &getHexagonTargetMachine() const {
96 return getTM<HexagonTargetMachine>();
100 createMachineScheduler(MachineSchedContext *C) const override {
101 return createVLIWMachineSched(C);
104 bool addInstSelector() override;
105 bool addPreRegAlloc() override;
106 bool addPostRegAlloc() override;
107 bool addPreSched2() override;
108 bool addPreEmitPass() override;
112 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
113 return new HexagonPassConfig(this, PM);
116 bool HexagonPassConfig::addInstSelector() {
117 HexagonTargetMachine &TM = getHexagonTargetMachine();
118 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
121 addPass(createHexagonRemoveExtendArgs(TM));
123 addPass(createHexagonISelDag(TM, getOptLevel()));
126 addPass(createHexagonPeephole());
127 printAndVerify("After hexagon peephole pass");
133 bool HexagonPassConfig::addPreRegAlloc() {
134 if (getOptLevel() != CodeGenOpt::None)
135 if (!DisableHardwareLoops)
136 addPass(createHexagonHardwareLoops());
140 bool HexagonPassConfig::addPostRegAlloc() {
141 const HexagonTargetMachine &TM = getHexagonTargetMachine();
142 if (getOptLevel() != CodeGenOpt::None)
143 if (!DisableHexagonCFGOpt)
144 addPass(createHexagonCFGOptimizer(TM));
148 bool HexagonPassConfig::addPreSched2() {
149 const HexagonTargetMachine &TM = getHexagonTargetMachine();
151 addPass(createHexagonCopyToCombine());
152 if (getOptLevel() != CodeGenOpt::None)
153 addPass(&IfConverterID);
154 addPass(createHexagonSplitConst32AndConst64(TM));
155 printAndVerify("After hexagon split const32/64 pass");
159 bool HexagonPassConfig::addPreEmitPass() {
160 const HexagonTargetMachine &TM = getHexagonTargetMachine();
161 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
164 addPass(createHexagonNewValueJump());
166 // Expand Spill code for predicate registers.
167 addPass(createHexagonExpandPredSpillCode(TM));
169 // Split up TFRcondsets into conditional transfers.
170 addPass(createHexagonSplitTFRCondSets(TM));
174 if (!DisableHardwareLoops)
175 addPass(createHexagonFixupHwLoops());
176 addPass(createHexagonPacketizer());