1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the Hexagon register file.
12 //===----------------------------------------------------------------------===//
14 let Namespace = "Hexagon" in {
16 class HexagonReg<bits<5> num, string n, list<string> alt = [],
17 list<Register> alias = []> : Register<n> {
20 let HWEncoding{4-0} = num;
23 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs> :
24 RegisterWithSubRegs<n, subregs> {
26 let HWEncoding{4-0} = num;
29 // Registers are identified with 5-bit ID numbers.
30 // Ri - 32-bit integer registers.
31 class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt> {
35 // Rf - 32-bit floating-point registers.
36 class Rf<bits<5> num, string n> : HexagonReg<num, n> {
41 // Rd - 64-bit registers.
42 class Rd<bits<5> num, string n, list<Register> subregs> :
43 HexagonDoubleReg<num, n, subregs> {
45 let SubRegs = subregs;
48 // Rp - predicate registers
49 class Rp<bits<5> num, string n> : HexagonReg<num, n> {
53 // Rc - control registers
54 class Rc<bits<5> num, string n> : HexagonReg<num, n> {
58 def subreg_loreg : SubRegIndex<32>;
59 def subreg_hireg : SubRegIndex<32, 32>;
63 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
66 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
67 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
68 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
70 // Aliases of the R* registers used to hold 64-bit int values (doubles).
71 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
72 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
73 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
74 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
75 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
76 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
77 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
78 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
79 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
80 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
81 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
82 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
83 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
84 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
85 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
86 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
87 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
90 // Predicate registers.
91 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
92 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
93 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
94 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
96 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
97 // tions modify this bit, and multiple such instructions are allowed in the
98 // same packet. We need to ignore output dependencies on this bit, but not
100 def USR_OVF : Rc<?, "usr.ovf">;
102 // Control registers.
103 def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>;
104 def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>;
106 def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>;
107 def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>;
109 def M0 : Rc<6, "m0">, DwarfRegNum<[71]>;
110 def M1 : Rc<7, "m1">, DwarfRegNum<[72]>;
112 def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct?
113 def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct?
118 // FIXME: the register order should be defined in terms of the preferred
119 // allocation order...
121 def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,
122 (add (sequence "R%u", 0, 9),
123 (sequence "R%u", 12, 28),
124 R10, R11, R29, R30, R31)> {
127 def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64,
128 (add (sequence "D%u", 0, 4),
129 (sequence "D%u", 6, 13), D5, D14, D15)>;
132 def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))>
137 def CRRegs : RegisterClass<"Hexagon", [i32], 32,
138 (add (sequence "LC%u", 0, 1),
139 (sequence "SA%u", 0, 1),
140 (sequence "M%u", 0, 1), PC, GP)> {
145 list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
149 LC0, LC1, SA0, SA1, USR_OVF];
152 def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
154 return isPositiveHalfWord(N);