1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
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3 // The LLVM Compiler Infrastructure
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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8 //===----------------------------------------------------------------------===//
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10 #include "MCTargetDesc/HexagonBaseInfo.h"
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11 #include "MCTargetDesc/HexagonMCTargetDesc.h"
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13 #include "llvm/MC/MCContext.h"
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14 #include "llvm/MC/MCDisassembler.h"
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15 #include "llvm/MC/MCExpr.h"
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16 #include "llvm/MC/MCFixedLenDisassembler.h"
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17 #include "llvm/MC/MCInst.h"
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18 #include "llvm/MC/MCInstrDesc.h"
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19 #include "llvm/MC/MCSubtargetInfo.h"
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20 #include "llvm/Support/Debug.h"
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21 #include "llvm/Support/ErrorHandling.h"
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22 #include "llvm/Support/LEB128.h"
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23 #include "llvm/Support/MemoryObject.h"
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24 #include "llvm/Support/raw_ostream.h"
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25 #include "llvm/Support/TargetRegistry.h"
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26 #include "llvm/Support/Endian.h"
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31 using namespace llvm;
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33 #define DEBUG_TYPE "hexagon-disassembler"
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35 // Pull DecodeStatus and its enum values into the global namespace.
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36 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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39 /// \brief Hexagon disassembler for all Hexagon platforms.
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40 class HexagonDisassembler : public MCDisassembler {
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42 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
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43 : MCDisassembler(STI, Ctx) {}
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45 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
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46 MemoryObject const ®ion, uint64_t address,
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47 raw_ostream &vStream, raw_ostream &cStream) const override;
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51 static const uint16_t IntRegDecoderTable[] = {
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52 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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53 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
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54 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
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55 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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56 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
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57 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
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58 Hexagon::R30, Hexagon::R31};
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60 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
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61 Hexagon::P2, Hexagon::P3};
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63 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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64 uint64_t /*Address*/,
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65 void const *Decoder) {
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67 return MCDisassembler::Fail;
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69 unsigned Register = IntRegDecoderTable[RegNo];
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70 Inst.addOperand(MCOperand::CreateReg(Register));
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71 return MCDisassembler::Success;
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74 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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75 uint64_t /*Address*/,
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76 void const *Decoder) {
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78 return MCDisassembler::Fail;
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80 unsigned Register = PredRegDecoderTable[RegNo];
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81 Inst.addOperand(MCOperand::CreateReg(Register));
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82 return MCDisassembler::Success;
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85 #include "HexagonGenDisassemblerTables.inc"
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87 static MCDisassembler *createHexagonDisassembler(Target const &T,
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88 MCSubtargetInfo const &STI,
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90 return new HexagonDisassembler(STI, Ctx);
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93 extern "C" void LLVMInitializeHexagonDisassembler() {
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94 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
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95 createHexagonDisassembler);
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98 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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99 MemoryObject const &Region,
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102 raw_ostream &cs) const {
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103 std::array<uint8_t, 4> Bytes;
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105 if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) {
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106 return MCDisassembler::Fail;
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109 llvm::support::endian::read<uint32_t, llvm::support::little,
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110 llvm::support::unaligned>(Bytes.data());
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112 // Remove parse bits.
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113 insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
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114 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
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