lib/Target/CellSPU/SPUTargetMachine.cpp

   1 //===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Top-level implementation for the Cell SPU target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "SPU.h"
  15 #include "SPUTargetMachine.h"
  16 #include "llvm/PassManager.h"
  17 #include "llvm/CodeGen/RegAllocRegistry.h"
  18 #include "llvm/CodeGen/SchedulerRegistry.h"
  19 #include "llvm/Target/TargetRegistry.h"
  20 #include "llvm/Support/DynamicLibrary.h"
  21
  22 using namespace llvm;
  23
  24 extern "C" void LLVMInitializeCellSPUTarget() {
  25   // Register the target.
  26   RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget);
  27 }
  28
  29 const std::pair<unsigned, int> *
  30 SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
  31   NumEntries = 1;
  32   return &LR[0];
  33 }
  34
  35 SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
  36                                    StringRef CPU, StringRef FS,
  37                                    Reloc::Model RM, CodeModel::Model CM)
  38   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
  39     Subtarget(TT, CPU, FS),
  40     DataLayout(Subtarget.getTargetDataString()),
  41     InstrInfo(*this),
  42     FrameLowering(Subtarget),
  43     TLInfo(*this),
  44     TSInfo(*this),
  45     InstrItins(Subtarget.getInstrItineraryData()) {
  46 }
  47
  48 //===----------------------------------------------------------------------===//
  49 // Pass Pipeline Configuration
  50 //===----------------------------------------------------------------------===//
  51
  52 bool SPUTargetMachine::addInstSelector(PassManagerBase &PM,
  53                                        CodeGenOpt::Level OptLevel) {
  54   // Install an instruction selector.
  55   PM.add(createSPUISelDag(*this));
  56   return false;
  57 }
  58
  59 // passes to run just before printing the assembly
  60 bool SPUTargetMachine::
  61 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
  62   // load the TCE instruction scheduler, if available via
  63   // loaded plugins
  64   typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
  65   BuilderFunc schedulerCreator =
  66     (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
  67           "createTCESchedulerPass");
  68   if (schedulerCreator != NULL)
  69       PM.add(schedulerCreator("cellspu"));
  70
  71   //align instructions with nops/lnops for dual issue
  72   PM.add(createSPUNopFillerPass(*this));
  73   return true;
  74 }