1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
41 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
43 isI64IntS10Immediate(ConstantSDNode *CN)
45 return isS10Constant(CN->getValue());
48 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
50 isI32IntS10Immediate(ConstantSDNode *CN)
52 return isS10Constant((int) CN->getValue());
56 //! SDNode predicate for sign-extended, 10-bit immediate values
58 isI32IntS10Immediate(SDNode *N)
60 return (N->getOpcode() == ISD::Constant
61 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
65 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
67 isI32IntU10Immediate(ConstantSDNode *CN)
69 return isU10Constant((int) CN->getValue());
72 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
74 isI16IntS10Immediate(ConstantSDNode *CN)
76 return isS10Constant((short) CN->getValue());
79 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
81 isI16IntS10Immediate(SDNode *N)
83 return (N->getOpcode() == ISD::Constant
84 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
87 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
89 isI16IntU10Immediate(ConstantSDNode *CN)
91 return isU10Constant((short) CN->getValue());
94 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
96 isI16IntU10Immediate(SDNode *N)
98 return (N->getOpcode() == ISD::Constant
99 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
102 //! ConstantSDNode predicate for signed 16-bit values
104 \arg CN The constant SelectionDAG node holding the value
105 \arg Imm The returned 16-bit value, if returning true
107 This predicate tests the value in \a CN to see whether it can be
108 represented as a 16-bit, sign-extended quantity. Returns true if
112 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
114 MVT::ValueType vt = CN->getValueType(0);
115 Imm = (short) CN->getValue();
116 if (vt >= MVT::i1 && vt <= MVT::i16) {
118 } else if (vt == MVT::i32) {
119 int32_t i_val = (int32_t) CN->getValue();
120 short s_val = (short) i_val;
121 return i_val == s_val;
123 int64_t i_val = (int64_t) CN->getValue();
124 short s_val = (short) i_val;
125 return i_val == s_val;
131 //! SDNode predicate for signed 16-bit values.
133 isIntS16Immediate(SDNode *N, short &Imm)
135 return (N->getOpcode() == ISD::Constant
136 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
139 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
141 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
143 MVT::ValueType vt = FPN->getValueType(0);
144 if (vt == MVT::f32) {
145 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
146 int sval = (int) ((val << 16) >> 16);
154 //===------------------------------------------------------------------===//
155 //! MVT::ValueType to "useful stuff" mapping structure:
157 struct valtype_map_s {
159 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
160 int prefslot_byte; /// Byte offset of the "preferred" slot
161 unsigned brcc_eq_ins; /// br_cc equal instruction
162 unsigned brcc_neq_ins; /// br_cc not equal instruction
165 const valtype_map_s valtype_map[] = {
166 { MVT::i1, 0, 3, 0, 0 },
167 { MVT::i8, 0, 3, 0, 0 },
168 { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
169 { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
170 { MVT::i64, SPU::ORIr64, 0, 0, 0 },
171 { MVT::f32, 0, 0, 0, 0 },
172 { MVT::f64, 0, 0, 0, 0 }
175 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
177 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
179 const valtype_map_s *retval = 0;
180 for (size_t i = 0; i < n_valtype_map; ++i) {
181 if (valtype_map[i].VT == VT) {
182 retval = valtype_map + i;
190 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
191 << MVT::getValueTypeString(VT)
201 //===--------------------------------------------------------------------===//
202 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
203 /// instructions for SelectionDAG operations.
205 class SPUDAGToDAGISel :
206 public SelectionDAGISel
208 SPUTargetMachine &TM;
209 SPUTargetLowering &SPUtli;
210 unsigned GlobalBaseReg;
213 SPUDAGToDAGISel(SPUTargetMachine &tm) :
214 SelectionDAGISel(*tm.getTargetLowering()),
216 SPUtli(*tm.getTargetLowering())
219 virtual bool runOnFunction(Function &Fn) {
220 // Make sure we re-emit a set of the global base reg if necessary
222 SelectionDAGISel::runOnFunction(Fn);
226 /// getI32Imm - Return a target constant with the specified value, of type
228 inline SDOperand getI32Imm(uint32_t Imm) {
229 return CurDAG->getTargetConstant(Imm, MVT::i32);
232 /// getI64Imm - Return a target constant with the specified value, of type
234 inline SDOperand getI64Imm(uint64_t Imm) {
235 return CurDAG->getTargetConstant(Imm, MVT::i64);
238 /// getSmallIPtrImm - Return a target constant of pointer type.
239 inline SDOperand getSmallIPtrImm(unsigned Imm) {
240 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
243 /// Select - Convert the specified operand from a target-independent to a
244 /// target-specific node if it hasn't already been changed.
245 SDNode *Select(SDOperand Op);
247 /// Return true if the address N is a RI7 format address [r+imm]
248 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
251 //! Returns true if the address N is an A-form (local store) address
252 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
255 //! D-form address predicate
256 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
259 //! Address predicate if N can be expressed as an indexed [r+r] operation.
260 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
263 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
264 /// inline asm expressions.
265 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
267 std::vector<SDOperand> &OutOps,
270 switch (ConstraintCode) {
271 default: return true;
273 if (!SelectDFormAddr(Op, Op, Op0, Op1)
274 && !SelectAFormAddr(Op, Op, Op0, Op1))
275 SelectXFormAddr(Op, Op, Op0, Op1);
277 case 'o': // offsetable
278 if (!SelectDFormAddr(Op, Op, Op0, Op1)
279 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
281 AddToISelQueue(Op0); // r+0.
282 Op1 = getSmallIPtrImm(0);
285 case 'v': // not offsetable
287 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
289 SelectAddrIdxOnly(Op, Op, Op0, Op1);
294 OutOps.push_back(Op0);
295 OutOps.push_back(Op1);
299 /// InstructionSelectBasicBlock - This callback is invoked by
300 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
301 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
303 virtual const char *getPassName() const {
304 return "Cell SPU DAG->DAG Pattern Instruction Selection";
307 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
308 /// this target when scheduling the DAG.
309 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
310 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
311 assert(II && "No InstrInfo?");
312 return new SPUHazardRecognizer(*II);
315 // Include the pieces autogenerated from the target description.
316 #include "SPUGenDAGISel.inc"
319 /// InstructionSelectBasicBlock - This callback is invoked by
320 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
322 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
326 // Select target instructions for the DAG.
327 DAG.setRoot(SelectRoot(DAG.getRoot()));
328 DAG.RemoveDeadNodes();
330 // Emit machine code to BB.
331 ScheduleAndEmitDAG(DAG);
335 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
337 unsigned Opc = N.getOpcode();
338 unsigned VT = N.getValueType();
339 MVT::ValueType PtrVT = SPUtli.getPointerTy();
340 ConstantSDNode *CN = 0;
343 if (Opc == ISD::ADD) {
344 SDOperand Op0 = N.getOperand(0);
345 SDOperand Op1 = N.getOperand(1);
346 if (Op1.getOpcode() == ISD::Constant ||
347 Op1.getOpcode() == ISD::TargetConstant) {
348 CN = cast<ConstantSDNode>(Op1);
349 Imm = int(CN->getValue());
351 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
356 } else if (Opc == ISD::GlobalAddress
357 || Opc == ISD::TargetGlobalAddress
358 || Opc == ISD::Register) {
359 // Plain old local store address:
360 Disp = CurDAG->getTargetConstant(0, VT);
363 } else if (Opc == SPUISD::DFormAddr) {
364 // D-Form address: This is pretty straightforward, naturally...
365 CN = cast<ConstantSDNode>(N.getOperand(1));
366 assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
367 Imm = unsigned(CN->getValue());
369 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
370 Base = N.getOperand(0);
379 \arg Op The ISD instructio operand
380 \arg N The address to be tested
381 \arg Base The base address
382 \arg Index The base address index
385 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
387 // These match the addr256k operand type:
388 MVT::ValueType PtrVT = SPUtli.getPointerTy();
389 MVT::ValueType OffsVT = MVT::i16;
391 switch (N.getOpcode()) {
393 case ISD::TargetConstant: {
394 // Loading from a constant address.
395 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
396 int Imm = (int)CN->getValue();
397 if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
398 Base = CurDAG->getTargetConstant(Imm, PtrVT);
399 // Note that this operand will be ignored by the assembly printer...
400 Index = CurDAG->getTargetConstant(0, OffsVT);
404 case ISD::ConstantPool:
405 case ISD::TargetConstantPool: {
406 // The constant pool address is N. Base is a dummy that will be ignored by
407 // the assembly printer.
409 Index = CurDAG->getTargetConstant(0, OffsVT);
413 case ISD::GlobalAddress:
414 case ISD::TargetGlobalAddress: {
415 // The global address is N. Base is a dummy that is ignored by the
418 Index = CurDAG->getTargetConstant(0, OffsVT);
427 \arg Op The ISD instruction (ignored)
428 \arg N The address to be tested
429 \arg Base Base address register/pointer
430 \arg Index Base address index
432 Examine the input address by a base register plus a signed 10-bit
433 displacement, [r+I10] (D-form address).
435 \return true if \a N is a D-form address with \a Base and \a Index set
436 to non-empty SDOperand instances.
439 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
441 unsigned Opc = N.getOpcode();
442 unsigned PtrTy = SPUtli.getPointerTy();
444 if (Opc == ISD::Register) {
446 Index = CurDAG->getTargetConstant(0, PtrTy);
448 } else if (Opc == ISD::FrameIndex) {
449 // Stack frame index must be less than 512 (divided by 16):
450 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
451 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
452 << FI->getIndex() << "\n");
453 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
454 Base = CurDAG->getTargetConstant(0, PtrTy);
455 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
458 } else if (Opc == ISD::ADD) {
459 // Generated by getelementptr
460 const SDOperand Op0 = N.getOperand(0); // Frame index/base
461 const SDOperand Op1 = N.getOperand(1); // Offset within base
462 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
468 int32_t offset = (int32_t) CN->getSignExtended();
469 unsigned Opc0 = Op0.getOpcode();
471 if ((offset & 0xf) != 0) {
472 cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n";
477 if (Opc0 == ISD::FrameIndex) {
478 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
479 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
480 << " frame index = " << FI->getIndex() << "\n");
482 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
483 Base = CurDAG->getTargetConstant(offset, PtrTy);
484 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
487 } else if (offset > SPUFrameInfo::minFrameOffset()
488 && offset < SPUFrameInfo::maxFrameOffset()) {
489 Base = CurDAG->getTargetConstant(offset, PtrTy);
490 if (Opc0 == ISD::GlobalAddress) {
491 // Convert global address to target global address
492 GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
493 Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
496 // Otherwise, just take operand 0
501 } else if (Opc == SPUISD::DFormAddr) {
502 // D-Form address: This is pretty straightforward, naturally...
503 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
504 assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
505 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
506 Index = N.getOperand(0);
514 \arg Op The ISD instruction operand
515 \arg N The address operand
516 \arg Base The base pointer operand
517 \arg Index The offset/index operand
519 If the address \a N can be expressed as a [r + s10imm] address, returns false.
520 Otherwise, creates two operands, Base and Index that will become the [r+r]
524 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
526 if (SelectAFormAddr(Op, N, Base, Index)
527 || SelectDFormAddr(Op, N, Base, Index))
530 unsigned Opc = N.getOpcode();
532 if (Opc == ISD::ADD) {
533 SDOperand N1 = N.getOperand(0);
534 SDOperand N2 = N.getOperand(1);
535 unsigned N1Opc = N1.getOpcode();
536 unsigned N2Opc = N2.getOpcode();
538 if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo)
539 || (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) {
540 Base = N.getOperand(0);
541 Index = N.getOperand(1);
544 cerr << "SelectXFormAddr: Unhandled ADD operands:\n";
552 } else if (N.getNumOperands() == 2) {
553 SDOperand N1 = N.getOperand(0);
554 SDOperand N2 = N.getOperand(1);
555 unsigned N1Opc = N1.getOpcode();
556 unsigned N2Opc = N2.getOpcode();
558 if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
559 && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
560 Base = N.getOperand(0);
561 Index = N.getOperand(1);
565 cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
572 cerr << "SelectXFormAddr: Unhandled operand type:\n";
582 //! Convert the operand from a target-independent to a target-specific node
586 SPUDAGToDAGISel::Select(SDOperand Op) {
588 unsigned Opc = N->getOpcode();
590 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
591 return NULL; // Already selected.
592 } else if (Opc == ISD::FrameIndex) {
593 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
594 int FI = cast<FrameIndexSDNode>(N)->getIndex();
595 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
597 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
598 return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
599 CurDAG->getTargetConstant(0, MVT::i32));
600 } else if (Opc == SPUISD::LDRESULT) {
601 // Custom select instructions for LDRESULT
602 unsigned VT = N->getValueType(0);
603 SDOperand Arg = N->getOperand(0);
604 SDOperand Chain = N->getOperand(1);
608 if (!MVT::isFloatingPoint(VT)) {
609 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
610 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
612 if (vtm->ldresult_ins == 0) {
613 cerr << "LDRESULT for unsupported type: "
614 << MVT::getValueTypeString(VT)
618 Opc = vtm->ldresult_ins;
620 AddToISelQueue(Zero);
621 Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
624 CurDAG->SelectNodeTo(N, (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64),
625 MVT::Other, Arg, Arg, Chain);
628 Chain = SDOperand(Result, 1);
629 AddToISelQueue(Chain);
634 return SelectCode(Op);
637 /// createPPCISelDag - This pass converts a legalized DAG into a
638 /// SPU-specific DAG, ready for instruction scheduling.
640 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
641 return new SPUDAGToDAGISel(TM);