1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, bool isKill, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 // << FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg, false, false, isKill)
72 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 else if (RC == Alpha::F8RCRegisterClass)
74 BuildMI(MBB, MI, TII.get(Alpha::STT))
75 .addReg(SrcReg, false, false, isKill)
76 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
77 else if (RC == Alpha::GPRCRegisterClass)
78 BuildMI(MBB, MI, TII.get(Alpha::STQ))
79 .addReg(SrcReg, false, false, isKill)
80 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
85 void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
87 SmallVectorImpl<MachineOperand> &Addr,
88 const TargetRegisterClass *RC,
89 SmallVectorImpl<MachineInstr*> &NewMIs) const {
91 if (RC == Alpha::F4RCRegisterClass)
93 else if (RC == Alpha::F8RCRegisterClass)
95 else if (RC == Alpha::GPRCRegisterClass)
99 MachineInstrBuilder MIB =
100 BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
101 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
102 MachineOperand &MO = Addr[i];
104 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
106 MIB.addImm(MO.getImm());
108 NewMIs.push_back(MIB);
112 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MI,
114 unsigned DestReg, int FrameIdx,
115 const TargetRegisterClass *RC) const {
116 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
117 // << FrameIdx << "\n";
118 if (RC == Alpha::F4RCRegisterClass)
119 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
120 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
121 else if (RC == Alpha::F8RCRegisterClass)
122 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
123 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
124 else if (RC == Alpha::GPRCRegisterClass)
125 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
126 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
131 void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
132 SmallVectorImpl<MachineOperand> &Addr,
133 const TargetRegisterClass *RC,
134 SmallVectorImpl<MachineInstr*> &NewMIs) const {
136 if (RC == Alpha::F4RCRegisterClass)
138 else if (RC == Alpha::F8RCRegisterClass)
140 else if (RC == Alpha::GPRCRegisterClass)
144 MachineInstrBuilder MIB =
145 BuildMI(TII.get(Opc), DestReg);
146 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
147 MachineOperand &MO = Addr[i];
149 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
151 MIB.addImm(MO.getImm());
153 NewMIs.push_back(MIB);
156 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
157 SmallVectorImpl<unsigned> &Ops,
158 int FrameIndex) const {
159 if (Ops.size() != 1) return NULL;
161 // Make sure this is a reg-reg copy.
162 unsigned Opc = MI->getOpcode();
164 MachineInstr *NewMI = NULL;
171 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
172 if (Ops[0] == 0) { // move -> store
173 unsigned InReg = MI->getOperand(1).getReg();
174 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
175 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
176 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
178 } else { // load -> move
179 unsigned OutReg = MI->getOperand(0).getReg();
180 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
181 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
182 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
189 NewMI->copyKillDeadInfo(MI);
194 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator MI,
196 unsigned DestReg, unsigned SrcReg,
197 const TargetRegisterClass *DestRC,
198 const TargetRegisterClass *SrcRC) const {
199 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
200 if (DestRC != SrcRC) {
201 cerr << "Not yet supported!";
205 if (DestRC == Alpha::GPRCRegisterClass) {
206 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
207 } else if (DestRC == Alpha::F4RCRegisterClass) {
208 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
209 } else if (DestRC == Alpha::F8RCRegisterClass) {
210 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
212 cerr << "Attempt to copy register that is not GPR or FPR";
217 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator I,
220 const MachineInstr *Orig) const {
221 MachineInstr *MI = Orig->clone();
222 MI->getOperand(0).setReg(DestReg);
226 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
228 static const unsigned CalleeSavedRegs[] = {
229 Alpha::R9, Alpha::R10,
230 Alpha::R11, Alpha::R12,
231 Alpha::R13, Alpha::R14,
232 Alpha::F2, Alpha::F3,
233 Alpha::F4, Alpha::F5,
234 Alpha::F6, Alpha::F7,
235 Alpha::F8, Alpha::F9, 0
237 return CalleeSavedRegs;
240 const TargetRegisterClass* const*
241 AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
242 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
243 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
244 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
245 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
246 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
247 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
248 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
249 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
251 return CalleeSavedRegClasses;
254 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
255 BitVector Reserved(getNumRegs());
256 Reserved.set(Alpha::R15);
257 Reserved.set(Alpha::R30);
258 Reserved.set(Alpha::R31);
262 //===----------------------------------------------------------------------===//
263 // Stack Frame Processing methods
264 //===----------------------------------------------------------------------===//
266 // hasFP - Return true if the specified function should have a dedicated frame
267 // pointer register. This is true if the function has variable sized allocas or
268 // if frame pointer elimination is disabled.
270 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
271 MachineFrameInfo *MFI = MF.getFrameInfo();
272 return MFI->hasVarSizedObjects();
275 void AlphaRegisterInfo::
276 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator I) const {
279 // If we have a frame pointer, turn the adjcallstackup instruction into a
280 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
282 MachineInstr *Old = I;
283 uint64_t Amount = Old->getOperand(0).getImmedValue();
285 // We need to keep the stack aligned properly. To do this, we round the
286 // amount of space needed for the outgoing arguments up to the next
287 // alignment boundary.
288 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
289 Amount = (Amount+Align-1)/Align*Align;
292 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
293 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
294 .addImm(-Amount).addReg(Alpha::R30);
296 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
297 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
298 .addImm(Amount).addReg(Alpha::R30);
301 // Replace the pseudo instruction with a new instruction...
309 //Alpha has a slightly funny stack:
312 //fixed locals (and spills, callee saved, etc)
317 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
318 int SPAdj, RegScavenger *RS) const {
319 assert(SPAdj == 0 && "Unexpected");
322 MachineInstr &MI = *II;
323 MachineBasicBlock &MBB = *MI.getParent();
324 MachineFunction &MF = *MBB.getParent();
327 while (!MI.getOperand(i).isFrameIndex()) {
329 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
332 int FrameIndex = MI.getOperand(i).getFrameIndex();
334 // Add the base register of R30 (SP) or R15 (FP).
335 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
337 // Now add the frame object offset to the offset from the virtual frame index.
338 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
340 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
342 Offset += MF.getFrameInfo()->getStackSize();
344 DOUT << "Corrected Offset " << Offset
345 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
347 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
348 DOUT << "Unconditionally using R28 for evil purposes Offset: "
350 //so in this case, we need to use a temporary register, and move the
351 //original inst off the SP/FP
353 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
354 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
356 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
357 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
360 MI.getOperand(i).ChangeToImmediate(Offset);
365 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
366 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
367 MachineBasicBlock::iterator MBBI = MBB.begin();
368 MachineFrameInfo *MFI = MF.getFrameInfo();
371 static int curgpdist = 0;
374 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
375 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
376 .addReg(Alpha::R27).addImm(++curgpdist);
377 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
378 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
379 .addReg(Alpha::R29).addImm(curgpdist);
381 //evil const_cast until MO stuff setup to handle const
382 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
383 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
385 // Get the number of bytes to allocate from the FrameInfo
386 long NumBytes = MFI->getStackSize();
389 NumBytes += 8; //reserve space for the old FP
391 // Do we need to allocate space on the stack?
392 if (NumBytes == 0) return;
394 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
395 NumBytes = (NumBytes+Align-1)/Align*Align;
397 // Update frame info to pretend that this is part of the stack...
398 MFI->setStackSize(NumBytes);
400 // adjust stack pointer: r30 -= numbytes
401 NumBytes = -NumBytes;
402 if (NumBytes >= IMM_LOW) {
403 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
405 } else if (getUpper16(NumBytes) >= IMM_LOW) {
406 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
408 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
411 cerr << "Too big a stack frame at " << NumBytes << "\n";
415 //now if we need to, save the old FP and set the new
418 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
419 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
420 //this must be the last instr in the prolog
421 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
422 .addReg(Alpha::R30).addReg(Alpha::R30);
427 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
428 MachineBasicBlock &MBB) const {
429 const MachineFrameInfo *MFI = MF.getFrameInfo();
430 MachineBasicBlock::iterator MBBI = prior(MBB.end());
431 assert(MBBI->getOpcode() == Alpha::RETDAG ||
432 MBBI->getOpcode() == Alpha::RETDAGp
433 && "Can only insert epilog into returning blocks");
437 // Get the number of bytes allocated from the FrameInfo...
438 long NumBytes = MFI->getStackSize();
440 //now if we need to, restore the old FP
443 //copy the FP into the SP (discards allocas)
444 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
447 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
452 if (NumBytes <= IMM_HIGH) {
453 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
455 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
456 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
457 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
458 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
459 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
461 cerr << "Too big a stack frame at " << NumBytes << "\n";
467 unsigned AlphaRegisterInfo::getRARegister() const {
468 assert(0 && "What is the return address register");
472 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
473 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
476 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
477 assert(0 && "What is the exception register");
481 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
482 assert(0 && "What is the exception handler register");
486 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
487 assert(0 && "What is the dwarf register number");
491 #include "AlphaGenRegisterInfo.inc"
493 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
495 std::string s(RegisterDescriptors[reg].Name);