1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
28 //===----------------------------------------------------------------------===//
29 // ARM64-specific DAG Nodes.
32 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
33 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
39 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
45 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
46 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
53 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
54 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
56 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
57 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
58 SDTCisVT<2, OtherVT>]>;
61 def SDT_ARM64CSel : SDTypeProfile<1, 4,
66 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
69 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
70 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
71 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
74 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
75 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
76 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 SDTCisInt<2>, SDTCisInt<3>]>;
78 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
79 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
81 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
83 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
84 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
85 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
86 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
92 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
94 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
96 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
98 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
99 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
100 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 SDTCisSameAs<1, 4>]>;
105 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
106 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
107 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
108 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
109 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
110 [SDNPHasChain, SDNPOutGlue]>;
111 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
112 SDCallSeqEnd<[ SDTCisVT<0, i32>,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def ARM64call : SDNode<"ARM64ISD::CALL",
116 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
121 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
123 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
125 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
127 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
131 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
132 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
133 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
134 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
135 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
138 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
139 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
141 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
142 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut,
144 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
145 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
147 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
149 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
151 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
152 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
154 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
155 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
156 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
157 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
158 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
160 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
161 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
162 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
163 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
164 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
165 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
167 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
168 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
169 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
170 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
171 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
172 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
173 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
175 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
176 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
177 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
178 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
180 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
181 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
182 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
183 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
184 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
185 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
186 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
187 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
189 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
190 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
191 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
193 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
194 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
195 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
196 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
197 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
199 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
200 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
201 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
203 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
204 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
205 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
206 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
207 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
208 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
209 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
211 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
212 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
213 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
214 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
215 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
217 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
218 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
220 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
222 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
225 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
226 [SDNPHasChain, SDNPSideEffect]>;
228 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
229 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
231 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
232 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
235 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
242 // ARM64 Instruction Predicate Definitions.
244 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
245 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
246 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
247 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
248 def ForCodeSize : Predicate<"ForCodeSize">;
249 def NotForCodeSize : Predicate<"!ForCodeSize">;
251 include "ARM64InstrFormats.td"
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
256 // Miscellaneous instructions.
257 //===----------------------------------------------------------------------===//
259 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
260 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
261 [(ARM64callseq_start timm:$amt)]>;
262 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
263 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
264 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
266 let isReMaterializable = 1, isCodeGenOnly = 1 in {
267 // FIXME: The following pseudo instructions are only needed because remat
268 // cannot handle multiple instructions. When that changes, they can be
269 // removed, along with the ARM64Wrapper node.
271 let AddedComplexity = 10 in
272 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
273 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
276 // The MOVaddr instruction should match only when the add is not folded
277 // into a load or store address.
279 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
280 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
281 tglobaladdr:$low))]>,
282 Sched<[WriteAdrAdr]>;
284 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
285 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
287 Sched<[WriteAdrAdr]>;
289 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
290 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
292 Sched<[WriteAdrAdr]>;
294 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
295 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
296 tblockaddress:$low))]>,
297 Sched<[WriteAdrAdr]>;
299 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
300 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
301 tglobaltlsaddr:$low))]>,
302 Sched<[WriteAdrAdr]>;
304 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
305 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
306 texternalsym:$low))]>,
307 Sched<[WriteAdrAdr]>;
309 } // isReMaterializable, isCodeGenOnly
311 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
312 (LOADgot tglobaltlsaddr:$addr)>;
314 def : Pat<(ARM64LOADgot texternalsym:$addr),
315 (LOADgot texternalsym:$addr)>;
317 def : Pat<(ARM64LOADgot tconstpool:$addr),
318 (LOADgot tconstpool:$addr)>;
320 //===----------------------------------------------------------------------===//
321 // System instructions.
322 //===----------------------------------------------------------------------===//
324 def HINT : HintI<"hint">;
325 def : InstAlias<"nop", (HINT 0b000)>;
326 def : InstAlias<"yield",(HINT 0b001)>;
327 def : InstAlias<"wfe", (HINT 0b010)>;
328 def : InstAlias<"wfi", (HINT 0b011)>;
329 def : InstAlias<"sev", (HINT 0b100)>;
330 def : InstAlias<"sevl", (HINT 0b101)>;
332 // As far as LLVM is concerned this writes to the system's exclusive monitors.
333 let mayLoad = 1, mayStore = 1 in
334 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
336 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
337 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
338 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
339 def : InstAlias<"clrex", (CLREX 0xf)>;
340 def : InstAlias<"isb", (ISB 0xf)>;
344 def MSRpstate: MSRpstateI;
346 // The thread pointer (on Linux, at least, where this has been implemented) is
348 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
350 // Generic system instructions
351 def SYSxt : SystemXtI<0, "sys">;
352 def SYSLxt : SystemLXtI<1, "sysl">;
354 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
355 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
356 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
358 //===----------------------------------------------------------------------===//
359 // Move immediate instructions.
360 //===----------------------------------------------------------------------===//
362 defm MOVK : InsertImmediate<0b11, "movk">;
363 defm MOVN : MoveImmediate<0b00, "movn">;
365 let PostEncoderMethod = "fixMOVZ" in
366 defm MOVZ : MoveImmediate<0b10, "movz">;
368 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
369 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
370 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
371 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
372 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
373 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
375 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
376 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
377 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
378 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
380 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
381 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
382 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
383 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
385 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
386 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
387 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
388 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
390 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
391 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
393 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
394 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
396 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
397 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
399 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
400 isAsCheapAsAMove = 1 in {
401 // FIXME: The following pseudo instructions are only needed because remat
402 // cannot handle multiple instructions. When that changes, we can select
403 // directly to the real instructions and get rid of these pseudos.
406 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
407 [(set GPR32:$dst, imm:$src)]>,
410 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
411 [(set GPR64:$dst, imm:$src)]>,
413 } // isReMaterializable, isCodeGenOnly
415 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
416 // eventual expansion code fewer bits to worry about getting right. Marshalling
417 // the types is a little tricky though:
418 def i64imm_32bit : ImmLeaf<i64, [{
419 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
422 def trunc_imm : SDNodeXForm<imm, [{
423 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
426 def : Pat<(i64 i64imm_32bit:$src),
427 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
429 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
431 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
432 tglobaladdr:$g1, tglobaladdr:$g0),
433 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
434 tglobaladdr:$g2, 32),
435 tglobaladdr:$g1, 16),
436 tglobaladdr:$g0, 0)>;
438 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
439 tblockaddress:$g1, tblockaddress:$g0),
440 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
441 tblockaddress:$g2, 32),
442 tblockaddress:$g1, 16),
443 tblockaddress:$g0, 0)>;
445 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
446 tconstpool:$g1, tconstpool:$g0),
447 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
452 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
453 tjumptable:$g1, tjumptable:$g0),
454 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
460 //===----------------------------------------------------------------------===//
461 // Arithmetic instructions.
462 //===----------------------------------------------------------------------===//
464 // Add/subtract with carry.
465 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
466 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
468 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
469 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
470 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
471 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
474 defm ADD : AddSub<0, "add", add>;
475 defm SUB : AddSub<1, "sub">;
477 defm ADDS : AddSubS<0, "adds", ARM64add_flag, "cmn">;
478 defm SUBS : AddSubS<1, "subs", ARM64sub_flag, "cmp">;
480 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
481 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
482 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
483 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
484 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
485 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
486 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
487 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
488 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
489 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
490 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
491 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
492 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
493 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
494 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
495 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
496 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
498 // Because of the immediate format for add/sub-imm instructions, the
499 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
500 // These patterns capture that transformation.
501 let AddedComplexity = 1 in {
502 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
503 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
504 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
505 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
506 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
507 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
508 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
509 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
512 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
513 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
514 def : InstAlias<"neg $dst, $src, $shift",
515 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
516 def : InstAlias<"neg $dst, $src, $shift",
517 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
519 // Because of the immediate format for add/sub-imm instructions, the
520 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
521 // These patterns capture that transformation.
522 let AddedComplexity = 1 in {
523 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
524 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
525 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
526 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
527 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
528 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
529 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
530 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
533 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
534 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
535 def : InstAlias<"negs $dst, $src, $shift",
536 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
537 def : InstAlias<"negs $dst, $src, $shift",
538 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
540 // Unsigned/Signed divide
541 defm UDIV : Div<0, "udiv", udiv>;
542 defm SDIV : Div<1, "sdiv", sdiv>;
543 let isCodeGenOnly = 1 in {
544 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
545 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
549 defm ASRV : Shift<0b10, "asr", sra>;
550 defm LSLV : Shift<0b00, "lsl", shl>;
551 defm LSRV : Shift<0b01, "lsr", srl>;
552 defm RORV : Shift<0b11, "ror", rotr>;
554 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
555 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
556 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
557 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
558 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
559 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
560 def : ShiftAlias<"rorv", RORVWr, GPR32>;
561 def : ShiftAlias<"rorv", RORVXr, GPR64>;
564 let AddedComplexity = 7 in {
565 defm MADD : MulAccum<0, "madd", add>;
566 defm MSUB : MulAccum<1, "msub", sub>;
568 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
569 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
570 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
571 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
573 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
574 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
575 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
576 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
577 } // AddedComplexity = 7
579 let AddedComplexity = 5 in {
580 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
581 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
582 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
583 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
585 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
586 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
587 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
588 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
590 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
591 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
592 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
593 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
594 } // AddedComplexity = 5
596 def : MulAccumWAlias<"mul", MADDWrrr>;
597 def : MulAccumXAlias<"mul", MADDXrrr>;
598 def : MulAccumWAlias<"mneg", MSUBWrrr>;
599 def : MulAccumXAlias<"mneg", MSUBXrrr>;
600 def : WideMulAccumAlias<"smull", SMADDLrrr>;
601 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
602 def : WideMulAccumAlias<"umull", UMADDLrrr>;
603 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
606 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
607 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
610 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
611 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
612 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
613 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
615 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
616 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
617 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
618 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
621 //===----------------------------------------------------------------------===//
622 // Logical instructions.
623 //===----------------------------------------------------------------------===//
626 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
627 defm AND : LogicalImm<0b00, "and", and>;
628 defm EOR : LogicalImm<0b10, "eor", xor>;
629 defm ORR : LogicalImm<0b01, "orr", or>;
631 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
632 logical_imm32:$imm)>;
633 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
634 logical_imm64:$imm)>;
638 defm ANDS : LogicalRegS<0b11, 0, "ands", ARM64and_flag>;
639 defm BICS : LogicalRegS<0b11, 1, "bics",
640 BinOpFrag<(ARM64and_flag node:$LHS, (not node:$RHS))>>;
641 defm AND : LogicalReg<0b00, 0, "and", and>;
642 defm BIC : LogicalReg<0b00, 1, "bic",
643 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
644 defm EON : LogicalReg<0b10, 1, "eon",
645 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
646 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
647 defm ORN : LogicalReg<0b01, 1, "orn",
648 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
649 defm ORR : LogicalReg<0b01, 0, "orr", or>;
651 def : InstAlias<"tst $src1, $src2",
652 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
653 def : InstAlias<"tst $src1, $src2",
654 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
656 def : InstAlias<"tst $src1, $src2",
657 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
658 def : InstAlias<"tst $src1, $src2",
659 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
661 def : InstAlias<"tst $src1, $src2, $sh",
662 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
663 def : InstAlias<"tst $src1, $src2, $sh",
664 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
666 def : InstAlias<"mvn $Wd, $Wm",
667 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
668 def : InstAlias<"mvn $Xd, $Xm",
669 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
671 def : InstAlias<"mvn $Wd, $Wm, $sh",
672 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
673 def : InstAlias<"mvn $Xd, $Xm, $sh",
674 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
676 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
677 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
680 //===----------------------------------------------------------------------===//
681 // One operand data processing instructions.
682 //===----------------------------------------------------------------------===//
684 defm CLS : OneOperandData<0b101, "cls">;
685 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
686 defm RBIT : OneOperandData<0b000, "rbit">;
687 def REV16Wr : OneWRegData<0b001, "rev16",
688 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
689 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
691 def : Pat<(cttz GPR32:$Rn),
692 (CLZWr (RBITWr GPR32:$Rn))>;
693 def : Pat<(cttz GPR64:$Rn),
694 (CLZXr (RBITXr GPR64:$Rn))>;
695 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
698 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
702 // Unlike the other one operand instructions, the instructions with the "rev"
703 // mnemonic do *not* just different in the size bit, but actually use different
704 // opcode bits for the different sizes.
705 def REVWr : OneWRegData<0b010, "rev", bswap>;
706 def REVXr : OneXRegData<0b011, "rev", bswap>;
707 def REV32Xr : OneXRegData<0b010, "rev32",
708 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
710 // The bswap commutes with the rotr so we want a pattern for both possible
712 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
713 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
715 //===----------------------------------------------------------------------===//
716 // Bitfield immediate extraction instruction.
717 //===----------------------------------------------------------------------===//
718 let neverHasSideEffects = 1 in
719 defm EXTR : ExtractImm<"extr">;
720 def : InstAlias<"ror $dst, $src, $shift",
721 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
722 def : InstAlias<"ror $dst, $src, $shift",
723 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
725 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
726 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
727 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
728 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
730 //===----------------------------------------------------------------------===//
731 // Other bitfield immediate instructions.
732 //===----------------------------------------------------------------------===//
733 let neverHasSideEffects = 1 in {
734 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
735 defm SBFM : BitfieldImm<0b00, "sbfm">;
736 defm UBFM : BitfieldImm<0b10, "ubfm">;
739 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
740 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
741 return CurDAG->getTargetConstant(enc, MVT::i64);
744 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
745 uint64_t enc = 31 - N->getZExtValue();
746 return CurDAG->getTargetConstant(enc, MVT::i64);
749 // min(7, 31 - shift_amt)
750 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
751 uint64_t enc = 31 - N->getZExtValue();
752 enc = enc > 7 ? 7 : enc;
753 return CurDAG->getTargetConstant(enc, MVT::i64);
756 // min(15, 31 - shift_amt)
757 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
758 uint64_t enc = 31 - N->getZExtValue();
759 enc = enc > 15 ? 15 : enc;
760 return CurDAG->getTargetConstant(enc, MVT::i64);
763 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
764 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
765 return CurDAG->getTargetConstant(enc, MVT::i64);
768 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
769 uint64_t enc = 63 - N->getZExtValue();
770 return CurDAG->getTargetConstant(enc, MVT::i64);
773 // min(7, 63 - shift_amt)
774 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
775 uint64_t enc = 63 - N->getZExtValue();
776 enc = enc > 7 ? 7 : enc;
777 return CurDAG->getTargetConstant(enc, MVT::i64);
780 // min(15, 63 - shift_amt)
781 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
782 uint64_t enc = 63 - N->getZExtValue();
783 enc = enc > 15 ? 15 : enc;
784 return CurDAG->getTargetConstant(enc, MVT::i64);
787 // min(31, 63 - shift_amt)
788 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
789 uint64_t enc = 63 - N->getZExtValue();
790 enc = enc > 31 ? 31 : enc;
791 return CurDAG->getTargetConstant(enc, MVT::i64);
794 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
795 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
796 (i64 (i32shift_b imm0_31:$imm)))>;
797 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
798 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
799 (i64 (i64shift_b imm0_63:$imm)))>;
801 let AddedComplexity = 10 in {
802 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
803 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
804 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
805 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
808 def : InstAlias<"asr $dst, $src, $shift",
809 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
810 def : InstAlias<"asr $dst, $src, $shift",
811 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
812 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
813 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
814 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
815 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
816 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
818 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
819 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
820 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
821 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
823 def : InstAlias<"lsr $dst, $src, $shift",
824 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
825 def : InstAlias<"lsr $dst, $src, $shift",
826 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
827 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
828 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
829 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
830 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
831 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
833 //===----------------------------------------------------------------------===//
834 // Conditionally set flags instructions.
835 //===----------------------------------------------------------------------===//
836 defm CCMN : CondSetFlagsImm<0, "ccmn">;
837 defm CCMP : CondSetFlagsImm<1, "ccmp">;
839 defm CCMN : CondSetFlagsReg<0, "ccmn">;
840 defm CCMP : CondSetFlagsReg<1, "ccmp">;
842 //===----------------------------------------------------------------------===//
843 // Conditional select instructions.
844 //===----------------------------------------------------------------------===//
845 defm CSEL : CondSelect<0, 0b00, "csel">;
847 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
848 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
849 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
850 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
852 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
853 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
854 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
855 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
856 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
857 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
858 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
859 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
860 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
861 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
862 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
863 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
865 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
866 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
867 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
868 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
869 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
870 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
871 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
872 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
874 // The inverse of the condition code from the alias instruction is what is used
875 // in the aliased instruction. The parser all ready inverts the condition code
876 // for these aliases.
877 // FIXME: Is this the correct way to handle these aliases?
878 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
879 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
881 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
882 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
884 def : InstAlias<"cinc $dst, $src, $cc",
885 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
886 def : InstAlias<"cinc $dst, $src, $cc",
887 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
889 def : InstAlias<"cinv $dst, $src, $cc",
890 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
891 def : InstAlias<"cinv $dst, $src, $cc",
892 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
894 def : InstAlias<"cneg $dst, $src, $cc",
895 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
896 def : InstAlias<"cneg $dst, $src, $cc",
897 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
899 //===----------------------------------------------------------------------===//
900 // PC-relative instructions.
901 //===----------------------------------------------------------------------===//
902 let isReMaterializable = 1 in {
903 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
904 def ADR : ADRI<0, "adr", adrlabel, []>;
905 } // neverHasSideEffects = 1
907 def ADRP : ADRI<1, "adrp", adrplabel,
908 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
909 } // isReMaterializable = 1
911 // page address of a constant pool entry, block address
912 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
913 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
915 //===----------------------------------------------------------------------===//
916 // Unconditional branch (register) instructions.
917 //===----------------------------------------------------------------------===//
919 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
920 def RET : BranchReg<0b0010, "ret", []>;
921 def DRPS : SpecialReturn<0b0101, "drps">;
922 def ERET : SpecialReturn<0b0100, "eret">;
923 } // isReturn = 1, isTerminator = 1, isBarrier = 1
925 // Default to the LR register.
926 def : InstAlias<"ret", (RET LR)>;
928 let isCall = 1, Defs = [LR], Uses = [SP] in {
929 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
932 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
933 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
934 } // isBranch, isTerminator, isBarrier, isIndirectBranch
936 // Create a separate pseudo-instruction for codegen to use so that we don't
937 // flag lr as used in every function. It'll be restored before the RET by the
938 // epilogue if it's legitimately used.
939 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
940 let isTerminator = 1;
945 // This is a directive-like pseudo-instruction. The purpose is to insert an
946 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
947 // (which in the usual case is a BLR).
948 let hasSideEffects = 1 in
949 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
950 let AsmString = ".tlsdesccall $sym";
953 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
954 // gets expanded to two MCInsts during lowering.
955 let isCall = 1, Defs = [LR] in
957 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
958 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
960 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
961 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
962 //===----------------------------------------------------------------------===//
963 // Conditional branch (immediate) instruction.
964 //===----------------------------------------------------------------------===//
965 def Bcc : BranchCond;
967 //===----------------------------------------------------------------------===//
968 // Compare-and-branch instructions.
969 //===----------------------------------------------------------------------===//
970 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
971 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
973 //===----------------------------------------------------------------------===//
974 // Test-bit-and-branch instructions.
975 //===----------------------------------------------------------------------===//
976 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
977 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
979 //===----------------------------------------------------------------------===//
980 // Unconditional branch (immediate) instructions.
981 //===----------------------------------------------------------------------===//
982 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
983 def B : BranchImm<0, "b", [(br bb:$addr)]>;
984 } // isBranch, isTerminator, isBarrier
986 let isCall = 1, Defs = [LR], Uses = [SP] in {
987 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
989 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
991 //===----------------------------------------------------------------------===//
992 // Exception generation instructions.
993 //===----------------------------------------------------------------------===//
994 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
995 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
996 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
997 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
998 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
999 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1000 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1001 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1003 // DCPSn defaults to an immediate operand of zero if unspecified.
1004 def : InstAlias<"dcps1", (DCPS1 0)>;
1005 def : InstAlias<"dcps2", (DCPS2 0)>;
1006 def : InstAlias<"dcps3", (DCPS3 0)>;
1008 //===----------------------------------------------------------------------===//
1009 // Load instructions.
1010 //===----------------------------------------------------------------------===//
1012 // Pair (indexed, offset)
1013 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
1014 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
1015 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
1016 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
1017 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1019 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1021 // Pair (pre-indexed)
1022 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1023 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1024 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1025 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1026 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1028 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1030 // Pair (post-indexed)
1031 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1032 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1033 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1034 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1035 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1037 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1040 // Pair (no allocate)
1041 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1042 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1043 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1044 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1045 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1048 // (register offset)
1051 let AddedComplexity = 10 in {
1053 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1054 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1055 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1056 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1057 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1058 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1059 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1060 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1063 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1064 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1065 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1066 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1067 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1068 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1069 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1070 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1071 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1075 // For regular load, we do not have any alignment requirement.
1076 // Thus, it is safe to directly map the vector loads with interesting
1077 // addressing modes.
1078 // FIXME: We could do the same for bitconvert to floating point vectors.
1079 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1080 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1081 (LDRBro ro_indexed8:$addr), bsub)>;
1082 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1083 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1084 (LDRBro ro_indexed8:$addr), bsub)>;
1085 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1086 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1087 (LDRHro ro_indexed16:$addr), hsub)>;
1088 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1089 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1090 (LDRHro ro_indexed16:$addr), hsub)>;
1091 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1092 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1093 (LDRSro ro_indexed32:$addr), ssub)>;
1094 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1095 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1096 (LDRSro ro_indexed32:$addr), ssub)>;
1097 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1098 (LDRDro ro_indexed64:$addr)>;
1099 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1100 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1101 (LDRDro ro_indexed64:$addr), dsub)>;
1103 // Match all load 64 bits width whose type is compatible with FPR64
1104 let Predicates = [IsLE] in {
1105 // We must do vector loads with LD1 in big-endian.
1106 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1107 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1108 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1109 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1111 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1112 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1114 // Match all load 128 bits width whose type is compatible with FPR128
1115 let Predicates = [IsLE] in {
1116 // We must do vector loads with LD1 in big-endian.
1117 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1118 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1119 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1120 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1121 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1122 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1124 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1126 // Load sign-extended half-word
1127 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1128 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1129 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1130 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1132 // Load sign-extended byte
1133 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1134 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1135 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1136 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1138 // Load sign-extended word
1139 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1140 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1143 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1144 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1147 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1148 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1149 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1150 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1151 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1152 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1154 // zextloadi1 -> zextloadi8
1155 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1156 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1157 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1159 // extload -> zextload
1160 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1161 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1162 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1163 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1164 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1165 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1166 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1167 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1168 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1169 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1170 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1172 } // AddedComplexity = 10
1175 // (unsigned immediate)
1177 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1178 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1179 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1180 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1181 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1182 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1183 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1184 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1185 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1186 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1187 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1188 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1189 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1190 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1192 // For regular load, we do not have any alignment requirement.
1193 // Thus, it is safe to directly map the vector loads with interesting
1194 // addressing modes.
1195 // FIXME: We could do the same for bitconvert to floating point vectors.
1196 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1197 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1198 (LDRBui am_indexed8:$addr), bsub)>;
1199 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1200 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1201 (LDRBui am_indexed8:$addr), bsub)>;
1202 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1203 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1204 (LDRHui am_indexed16:$addr), hsub)>;
1205 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1206 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1207 (LDRHui am_indexed16:$addr), hsub)>;
1208 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1209 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1210 (LDRSui am_indexed32:$addr), ssub)>;
1211 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1212 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1213 (LDRSui am_indexed32:$addr), ssub)>;
1214 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1215 (LDRDui am_indexed64:$addr)>;
1216 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1217 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1218 (LDRDui am_indexed64:$addr), dsub)>;
1220 // Match all load 64 bits width whose type is compatible with FPR64
1221 let Predicates = [IsLE] in {
1222 // We must use LD1 to perform vector loads in big-endian.
1223 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1224 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1225 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1226 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1228 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1229 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1231 // Match all load 128 bits width whose type is compatible with FPR128
1232 let Predicates = [IsLE] in {
1233 // We must use LD1 to perform vector loads in big-endian.
1234 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1235 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1236 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1237 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1238 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1239 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1241 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1243 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1244 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1245 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1246 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1248 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1249 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1250 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1251 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1253 // zextloadi1 -> zextloadi8
1254 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1255 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1256 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1258 // extload -> zextload
1259 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1260 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1261 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1262 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1263 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1264 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1265 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1266 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1267 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1268 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1269 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1271 // load sign-extended half-word
1272 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1273 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1274 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1275 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1277 // load sign-extended byte
1278 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1279 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1280 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1281 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1283 // load sign-extended word
1284 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1285 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1287 // load zero-extended word
1288 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1289 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1292 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1293 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1297 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1298 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1299 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1300 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1301 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1303 // load sign-extended word
1304 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1307 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1308 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1311 // (unscaled immediate)
1312 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1313 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1314 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1315 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1316 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1317 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1318 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1319 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1320 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1321 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1322 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1323 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1324 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1325 [(set (f128 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1328 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1329 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1331 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1332 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1334 // Match all load 64 bits width whose type is compatible with FPR64
1335 let Predicates = [IsLE] in {
1336 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1337 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1338 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1339 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1341 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1342 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1344 // Match all load 128 bits width whose type is compatible with FPR128
1345 let Predicates = [IsLE] in {
1346 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1347 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1348 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1349 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1350 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1351 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1352 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1356 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1357 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1358 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1359 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1360 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1361 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1362 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1363 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1364 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1365 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1366 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1368 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1369 (LDURHHi am_unscaled16:$addr)>;
1370 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1371 (LDURBBi am_unscaled8:$addr)>;
1372 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1373 (LDURBBi am_unscaled8:$addr)>;
1374 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1375 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1376 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1377 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1378 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1379 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1380 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1381 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1385 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1387 // Define new assembler match classes as we want to only match these when
1388 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1389 // associate a DiagnosticType either, as we want the diagnostic for the
1390 // canonical form (the scaled operand) to take precedence.
1391 def MemoryUnscaledFB8Operand : AsmOperandClass {
1392 let Name = "MemoryUnscaledFB8";
1393 let RenderMethod = "addMemoryUnscaledOperands";
1395 def MemoryUnscaledFB16Operand : AsmOperandClass {
1396 let Name = "MemoryUnscaledFB16";
1397 let RenderMethod = "addMemoryUnscaledOperands";
1399 def MemoryUnscaledFB32Operand : AsmOperandClass {
1400 let Name = "MemoryUnscaledFB32";
1401 let RenderMethod = "addMemoryUnscaledOperands";
1403 def MemoryUnscaledFB64Operand : AsmOperandClass {
1404 let Name = "MemoryUnscaledFB64";
1405 let RenderMethod = "addMemoryUnscaledOperands";
1407 def MemoryUnscaledFB128Operand : AsmOperandClass {
1408 let Name = "MemoryUnscaledFB128";
1409 let RenderMethod = "addMemoryUnscaledOperands";
1411 def am_unscaled_fb8 : Operand<i64> {
1412 let ParserMatchClass = MemoryUnscaledFB8Operand;
1413 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1415 def am_unscaled_fb16 : Operand<i64> {
1416 let ParserMatchClass = MemoryUnscaledFB16Operand;
1417 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1419 def am_unscaled_fb32 : Operand<i64> {
1420 let ParserMatchClass = MemoryUnscaledFB32Operand;
1421 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1423 def am_unscaled_fb64 : Operand<i64> {
1424 let ParserMatchClass = MemoryUnscaledFB64Operand;
1425 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1427 def am_unscaled_fb128 : Operand<i64> {
1428 let ParserMatchClass = MemoryUnscaledFB128Operand;
1429 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1431 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1432 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1433 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1434 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1435 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1436 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1437 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1440 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1441 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1442 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1443 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1445 // load sign-extended half-word
1447 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1448 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1450 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1451 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1453 // load sign-extended byte
1455 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1456 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1458 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1459 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1461 // load sign-extended word
1463 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1464 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1466 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1467 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1468 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1469 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1470 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1471 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1472 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1473 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1476 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1477 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1480 // (unscaled immediate, unprivileged)
1481 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1482 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1484 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1485 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1487 // load sign-extended half-word
1488 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1489 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1491 // load sign-extended byte
1492 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1493 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1495 // load sign-extended word
1496 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1499 // (immediate pre-indexed)
1500 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1501 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1502 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1503 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1504 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1505 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1506 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1508 // load sign-extended half-word
1509 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1510 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1512 // load sign-extended byte
1513 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1514 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1516 // load zero-extended byte
1517 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1518 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1520 // load sign-extended word
1521 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1523 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1524 def LDRQpre_isel : LoadPreIdxPseudo<FPR128>;
1525 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1526 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1527 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1528 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1529 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1530 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1532 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1533 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1534 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1535 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1536 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1539 // (immediate post-indexed)
1540 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1541 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1542 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1543 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1544 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1545 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1546 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1548 // load sign-extended half-word
1549 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1550 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1552 // load sign-extended byte
1553 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1554 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1556 // load zero-extended byte
1557 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1558 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1560 // load sign-extended word
1561 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1563 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1564 def LDRQpost_isel : LoadPostIdxPseudo<FPR128>;
1565 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1566 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1567 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1568 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1569 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1570 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1572 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1573 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1574 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1575 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1576 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1578 //===----------------------------------------------------------------------===//
1579 // Store instructions.
1580 //===----------------------------------------------------------------------===//
1582 // Pair (indexed, offset)
1583 // FIXME: Use dedicated range-checked addressing mode operand here.
1584 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1585 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1586 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1587 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1588 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1590 // Pair (pre-indexed)
1591 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1592 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1593 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1594 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1595 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1597 // Pair (pre-indexed)
1598 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1599 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1600 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1601 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1602 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1604 // Pair (no allocate)
1605 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1606 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1607 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1608 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1609 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1612 // (Register offset)
1614 let AddedComplexity = 10 in {
1617 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1618 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1619 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1620 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1621 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1622 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1623 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1624 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1627 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1628 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1629 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1630 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1631 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1632 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1636 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1637 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1638 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1639 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1640 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1641 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1642 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1643 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1644 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1648 // Match all store 64 bits width whose type is compatible with FPR64
1649 let Predicates = [IsLE] in {
1650 // We must use ST1 to store vectors in big-endian.
1651 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1652 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1653 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1654 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1655 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1656 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1657 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1658 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1660 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1661 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1662 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1663 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1665 // Match all store 128 bits width whose type is compatible with FPR128
1666 let Predicates = [IsLE] in {
1667 // We must use ST1 to store vectors in big-endian.
1668 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1669 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1670 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1671 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1672 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1673 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1674 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1675 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1676 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1677 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1678 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1679 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1681 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1682 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1685 // (unsigned immediate)
1686 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1687 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1688 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1689 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1690 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1691 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1692 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1693 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1694 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1695 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1696 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1697 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1698 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1702 // Match all store 64 bits width whose type is compatible with FPR64
1703 let Predicates = [IsLE] in {
1704 // We must use ST1 to store vectors in big-endian.
1705 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1706 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1707 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1708 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1709 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1710 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1711 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1712 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1714 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1715 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1716 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1717 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1719 // Match all store 128 bits width whose type is compatible with FPR128
1720 let Predicates = [IsLE] in {
1721 // We must use ST1 to store vectors in big-endian.
1722 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1723 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1724 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1725 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1726 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1727 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1728 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1729 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1730 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1731 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1732 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1733 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1735 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1736 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1738 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1739 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1740 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1741 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1744 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1745 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1746 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1747 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1748 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1749 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1751 } // AddedComplexity = 10
1754 // (unscaled immediate)
1755 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1756 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1757 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1758 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1759 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1760 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1761 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1762 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1763 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1764 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1765 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1766 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1767 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1768 [(store (f128 FPR128:$Rt), am_unscaled128:$addr)]>;
1769 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1770 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1771 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1772 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1774 // Match all store 64 bits width whose type is compatible with FPR64
1775 let Predicates = [IsLE] in {
1776 // We must use ST1 to store vectors in big-endian.
1777 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1778 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1779 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1780 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1781 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1782 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1783 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1784 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1786 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1787 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1788 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1789 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1791 // Match all store 128 bits width whose type is compatible with FPR128
1792 let Predicates = [IsLE] in {
1793 // We must use ST1 to store vectors in big-endian.
1794 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1795 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1796 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1797 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1798 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1799 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1800 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1801 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1802 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1803 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1804 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1805 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1806 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1807 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1810 // unscaled i64 truncating stores
1811 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1812 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1813 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1814 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1815 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1816 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1819 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1820 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1821 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1822 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1823 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1824 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1825 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1826 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1828 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1829 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1832 // (unscaled immediate, unprivileged)
1833 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1834 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1836 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1837 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1840 // (immediate pre-indexed)
1841 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1842 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1843 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1844 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1845 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1846 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1847 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1849 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1850 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1852 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1853 defm STRQpre : StorePreIdxPseudo<FPR128, f128, pre_store>;
1854 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1855 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1856 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1857 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1858 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1859 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1861 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1862 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1864 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1865 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1867 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1868 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1871 def : Pat<(pre_store (v8i8 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1872 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1873 def : Pat<(pre_store (v4i16 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1874 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1875 def : Pat<(pre_store (v2i32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1876 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1877 def : Pat<(pre_store (v2f32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1878 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1879 def : Pat<(pre_store (v1i64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1880 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1881 def : Pat<(pre_store (v1f64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1882 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1884 def : Pat<(pre_store (v16i8 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1885 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1886 def : Pat<(pre_store (v8i16 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1887 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1888 def : Pat<(pre_store (v4i32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1889 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1890 def : Pat<(pre_store (v4f32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1891 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1892 def : Pat<(pre_store (v2i64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1893 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1894 def : Pat<(pre_store (v2f64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1895 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1898 // (immediate post-indexed)
1899 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1900 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1901 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1902 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1903 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1904 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1905 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1907 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1908 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1910 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1911 defm STRQpost : StorePostIdxPseudo<FPR128, f128, post_store, STRQpost>;
1912 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1913 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1914 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1915 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1916 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1917 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1919 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1920 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1922 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1923 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1925 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1926 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1929 def : Pat<(post_store (v8i8 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1930 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1931 def : Pat<(post_store (v4i16 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1932 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1933 def : Pat<(post_store (v2i32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1934 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1935 def : Pat<(post_store (v2f32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1936 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1937 def : Pat<(post_store (v1i64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1938 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1939 def : Pat<(post_store (v1f64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1940 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1942 def : Pat<(post_store (v16i8 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1943 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1944 def : Pat<(post_store (v8i16 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1945 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1946 def : Pat<(post_store (v4i32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1947 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1948 def : Pat<(post_store (v4f32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1949 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1950 def : Pat<(post_store (v2i64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1951 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1952 def : Pat<(post_store (v2f64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1953 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1955 //===----------------------------------------------------------------------===//
1956 // Load/store exclusive instructions.
1957 //===----------------------------------------------------------------------===//
1959 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1960 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1961 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1962 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1964 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1965 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1966 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1967 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1969 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1970 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1971 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1972 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1974 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1975 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1976 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1977 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1979 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1980 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1981 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1982 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1984 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1985 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1986 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1987 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1989 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1990 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1992 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1993 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1995 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1996 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1998 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1999 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2001 //===----------------------------------------------------------------------===//
2002 // Scaled floating point to integer conversion instructions.
2003 //===----------------------------------------------------------------------===//
2005 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
2006 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
2007 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
2008 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
2009 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
2010 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
2011 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
2012 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
2013 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2014 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2015 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2016 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2017 let isCodeGenOnly = 1 in {
2018 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2019 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2020 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2021 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2024 //===----------------------------------------------------------------------===//
2025 // Scaled integer to floating point conversion instructions.
2026 //===----------------------------------------------------------------------===//
2028 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2029 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2031 //===----------------------------------------------------------------------===//
2032 // Unscaled integer to floating point conversion instruction.
2033 //===----------------------------------------------------------------------===//
2035 defm FMOV : UnscaledConversion<"fmov">;
2037 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2038 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2040 //===----------------------------------------------------------------------===//
2041 // Floating point conversion instruction.
2042 //===----------------------------------------------------------------------===//
2044 defm FCVT : FPConversion<"fcvt">;
2046 def : Pat<(f32_to_f16 FPR32:$Rn),
2047 (i32 (COPY_TO_REGCLASS
2048 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
2051 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
2052 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
2054 //===----------------------------------------------------------------------===//
2055 // Floating point single operand instructions.
2056 //===----------------------------------------------------------------------===//
2058 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2059 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2060 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2061 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2062 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2063 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2064 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
2065 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2067 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
2068 (FRINTNDr FPR64:$Rn)>;
2070 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2071 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2072 // <rdar://problem/13715968>
2073 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2074 let hasSideEffects = 1 in {
2075 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2078 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2080 let SchedRW = [WriteFDiv] in {
2081 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2084 //===----------------------------------------------------------------------===//
2085 // Floating point two operand instructions.
2086 //===----------------------------------------------------------------------===//
2088 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2089 let SchedRW = [WriteFDiv] in {
2090 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2092 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2093 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2094 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2095 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2096 let SchedRW = [WriteFMul] in {
2097 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2098 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2100 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2102 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2103 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2104 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2105 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2106 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2107 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2108 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2109 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2111 //===----------------------------------------------------------------------===//
2112 // Floating point three operand instructions.
2113 //===----------------------------------------------------------------------===//
2115 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2116 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2117 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2118 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2119 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2120 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2121 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2123 // The following def pats catch the case where the LHS of an FMA is negated.
2124 // The TriOpFrag above catches the case where the middle operand is negated.
2126 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2127 // the NEON variant.
2128 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2129 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2131 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2132 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2134 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2136 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2137 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2139 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2140 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2142 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2143 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2145 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2146 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2148 //===----------------------------------------------------------------------===//
2149 // Floating point comparison instructions.
2150 //===----------------------------------------------------------------------===//
2152 defm FCMPE : FPComparison<1, "fcmpe">;
2153 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2155 //===----------------------------------------------------------------------===//
2156 // Floating point conditional comparison instructions.
2157 //===----------------------------------------------------------------------===//
2159 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2160 defm FCCMP : FPCondComparison<0, "fccmp">;
2162 //===----------------------------------------------------------------------===//
2163 // Floating point conditional select instruction.
2164 //===----------------------------------------------------------------------===//
2166 defm FCSEL : FPCondSelect<"fcsel">;
2168 // CSEL instructions providing f128 types need to be handled by a
2169 // pseudo-instruction since the eventual code will need to introduce basic
2170 // blocks and control flow.
2171 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2172 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2173 [(set (f128 FPR128:$Rd),
2174 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2175 (i32 imm:$cond), NZCV))]> {
2177 let usesCustomInserter = 1;
2181 //===----------------------------------------------------------------------===//
2182 // Floating point immediate move.
2183 //===----------------------------------------------------------------------===//
2185 let isReMaterializable = 1 in {
2186 defm FMOV : FPMoveImmediate<"fmov">;
2189 //===----------------------------------------------------------------------===//
2190 // Advanced SIMD two vector instructions.
2191 //===----------------------------------------------------------------------===//
2193 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2194 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2195 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2196 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2197 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2198 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2199 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2200 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2201 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2202 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2204 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2205 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2206 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2207 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2208 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2209 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2210 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2211 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2212 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2213 (FCVTLv4i16 V64:$Rn)>;
2214 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2216 (FCVTLv8i16 V128:$Rn)>;
2217 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2218 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2220 (FCVTLv4i32 V128:$Rn)>;
2222 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2223 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2224 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2225 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2226 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2227 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2228 (FCVTNv4i16 V128:$Rn)>;
2229 def : Pat<(concat_vectors V64:$Rd,
2230 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2231 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2232 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2233 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2234 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2235 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2236 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2237 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2238 int_arm64_neon_fcvtxn>;
2239 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2240 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2241 let isCodeGenOnly = 1 in {
2242 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2243 int_arm64_neon_fcvtzs>;
2244 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2245 int_arm64_neon_fcvtzu>;
2247 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2248 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2249 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2250 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2251 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2252 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2253 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2254 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2255 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2256 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2257 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2258 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2259 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2260 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2261 // Aliases for MVN -> NOT.
2262 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2263 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2264 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2265 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2267 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2268 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2269 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2270 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2271 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2272 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2273 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2275 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2276 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2277 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2278 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2279 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2280 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2281 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2282 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2284 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2285 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2286 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2287 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2288 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2290 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2291 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2292 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2293 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2294 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2295 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2296 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2297 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2298 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2299 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2300 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2301 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2302 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2303 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2304 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2305 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2306 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2307 int_arm64_neon_uaddlp>;
2308 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2309 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2310 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2311 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2312 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2313 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2315 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2316 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2318 // Patterns for vector long shift (by element width). These need to match all
2319 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2321 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2322 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2323 (SHLLv8i8 V64:$Rn)>;
2324 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2325 (SHLLv16i8 V128:$Rn)>;
2326 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2327 (SHLLv4i16 V64:$Rn)>;
2328 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2329 (SHLLv8i16 V128:$Rn)>;
2330 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2331 (SHLLv2i32 V64:$Rn)>;
2332 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2333 (SHLLv4i32 V128:$Rn)>;
2336 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2337 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2338 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2340 //===----------------------------------------------------------------------===//
2341 // Advanced SIMD three vector instructions.
2342 //===----------------------------------------------------------------------===//
2344 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2345 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2346 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2347 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2348 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2349 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2350 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2351 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2352 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2353 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2354 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2355 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2356 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2357 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2358 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2359 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2360 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2361 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2362 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2363 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2364 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2365 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2366 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2367 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2368 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2370 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2371 // instruction expects the addend first, while the fma intrinsic puts it last.
2372 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2373 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2374 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2375 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2377 // The following def pats catch the case where the LHS of an FMA is negated.
2378 // The TriOpFrag above catches the case where the middle operand is negated.
2379 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2380 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2382 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2383 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2385 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2386 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2388 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2389 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2390 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2391 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2392 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2393 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2394 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2395 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2396 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2397 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2398 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2399 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2400 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2401 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2402 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2403 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2404 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2405 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2406 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2407 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2408 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2409 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2410 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2411 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2412 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2413 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2414 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2415 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2416 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2417 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2418 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2419 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2420 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2421 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2422 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2423 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2424 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2425 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2426 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2427 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2428 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2429 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2430 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2431 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2432 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2433 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2435 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2436 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2437 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2438 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2439 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2440 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2441 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2442 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2443 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2444 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2445 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2447 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2448 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2449 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2450 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2451 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2452 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2453 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2454 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2456 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2457 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2458 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2459 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2460 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2461 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2462 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2463 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2465 // FIXME: the .16b and .8b variantes should be emitted by the
2466 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2467 // in aliases yet though.
2468 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2469 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2470 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2471 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2472 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2473 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2474 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2475 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2477 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2478 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2479 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2480 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2481 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2482 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2483 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2484 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2486 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2487 "|cmls.8b\t$dst, $src1, $src2}",
2488 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2489 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2490 "|cmls.16b\t$dst, $src1, $src2}",
2491 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2492 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2493 "|cmls.4h\t$dst, $src1, $src2}",
2494 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2495 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2496 "|cmls.8h\t$dst, $src1, $src2}",
2497 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2498 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2499 "|cmls.2s\t$dst, $src1, $src2}",
2500 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2501 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2502 "|cmls.4s\t$dst, $src1, $src2}",
2503 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2504 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2505 "|cmls.2d\t$dst, $src1, $src2}",
2506 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2508 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2509 "|cmlo.8b\t$dst, $src1, $src2}",
2510 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2511 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2512 "|cmlo.16b\t$dst, $src1, $src2}",
2513 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2514 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2515 "|cmlo.4h\t$dst, $src1, $src2}",
2516 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2517 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2518 "|cmlo.8h\t$dst, $src1, $src2}",
2519 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2520 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2521 "|cmlo.2s\t$dst, $src1, $src2}",
2522 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2523 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2524 "|cmlo.4s\t$dst, $src1, $src2}",
2525 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2526 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2527 "|cmlo.2d\t$dst, $src1, $src2}",
2528 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2530 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2531 "|cmle.8b\t$dst, $src1, $src2}",
2532 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2533 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2534 "|cmle.16b\t$dst, $src1, $src2}",
2535 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2536 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2537 "|cmle.4h\t$dst, $src1, $src2}",
2538 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2539 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2540 "|cmle.8h\t$dst, $src1, $src2}",
2541 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2542 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2543 "|cmle.2s\t$dst, $src1, $src2}",
2544 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2545 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2546 "|cmle.4s\t$dst, $src1, $src2}",
2547 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2548 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2549 "|cmle.2d\t$dst, $src1, $src2}",
2550 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2552 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2553 "|cmlt.8b\t$dst, $src1, $src2}",
2554 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2555 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2556 "|cmlt.16b\t$dst, $src1, $src2}",
2557 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2558 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2559 "|cmlt.4h\t$dst, $src1, $src2}",
2560 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2561 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2562 "|cmlt.8h\t$dst, $src1, $src2}",
2563 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2564 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2565 "|cmlt.2s\t$dst, $src1, $src2}",
2566 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2567 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2568 "|cmlt.4s\t$dst, $src1, $src2}",
2569 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2570 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2571 "|cmlt.2d\t$dst, $src1, $src2}",
2572 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2574 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2575 "|fcmle.2s\t$dst, $src1, $src2}",
2576 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2577 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2578 "|fcmle.4s\t$dst, $src1, $src2}",
2579 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2580 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2581 "|fcmle.2d\t$dst, $src1, $src2}",
2582 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2584 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2585 "|fcmlt.2s\t$dst, $src1, $src2}",
2586 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2587 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2588 "|fcmlt.4s\t$dst, $src1, $src2}",
2589 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2590 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2591 "|fcmlt.2d\t$dst, $src1, $src2}",
2592 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2594 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2595 "|facle.2s\t$dst, $src1, $src2}",
2596 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2597 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2598 "|facle.4s\t$dst, $src1, $src2}",
2599 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2600 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2601 "|facle.2d\t$dst, $src1, $src2}",
2602 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2604 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2605 "|faclt.2s\t$dst, $src1, $src2}",
2606 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2607 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2608 "|faclt.4s\t$dst, $src1, $src2}",
2609 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2610 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2611 "|faclt.2d\t$dst, $src1, $src2}",
2612 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2614 //===----------------------------------------------------------------------===//
2615 // Advanced SIMD three scalar instructions.
2616 //===----------------------------------------------------------------------===//
2618 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2619 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2620 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2621 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2622 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2623 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2624 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2625 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2626 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2627 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2628 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2629 int_arm64_neon_facge>;
2630 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2631 int_arm64_neon_facgt>;
2632 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2633 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2634 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2635 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2636 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2637 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2638 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2639 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2640 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2641 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2642 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2643 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2644 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2645 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2646 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2647 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2648 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2649 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2650 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2651 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2652 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2654 def : InstAlias<"cmls $dst, $src1, $src2",
2655 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2656 def : InstAlias<"cmle $dst, $src1, $src2",
2657 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2658 def : InstAlias<"cmlo $dst, $src1, $src2",
2659 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2660 def : InstAlias<"cmlt $dst, $src1, $src2",
2661 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2662 def : InstAlias<"fcmle $dst, $src1, $src2",
2663 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2664 def : InstAlias<"fcmle $dst, $src1, $src2",
2665 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2666 def : InstAlias<"fcmlt $dst, $src1, $src2",
2667 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2668 def : InstAlias<"fcmlt $dst, $src1, $src2",
2669 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2670 def : InstAlias<"facle $dst, $src1, $src2",
2671 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2672 def : InstAlias<"facle $dst, $src1, $src2",
2673 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2674 def : InstAlias<"faclt $dst, $src1, $src2",
2675 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2676 def : InstAlias<"faclt $dst, $src1, $src2",
2677 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2679 //===----------------------------------------------------------------------===//
2680 // Advanced SIMD three scalar instructions (mixed operands).
2681 //===----------------------------------------------------------------------===//
2682 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2683 int_arm64_neon_sqdmulls_scalar>;
2684 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2685 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2687 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2688 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2689 (i32 FPR32:$Rm))))),
2690 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2691 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2692 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2693 (i32 FPR32:$Rm))))),
2694 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2696 //===----------------------------------------------------------------------===//
2697 // Advanced SIMD two scalar instructions.
2698 //===----------------------------------------------------------------------===//
2700 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2701 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2702 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2703 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2704 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2705 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2706 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2707 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2708 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2709 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2710 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2711 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2712 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2713 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2714 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2715 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2716 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2717 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2718 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2719 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2720 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2721 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2722 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2723 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2724 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2725 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2726 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2727 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2728 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2729 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2730 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2731 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2732 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2733 int_arm64_neon_suqadd>;
2734 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2735 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2736 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2737 int_arm64_neon_usqadd>;
2739 def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2741 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2742 (FCVTASv1i64 FPR64:$Rn)>;
2743 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2744 (FCVTAUv1i64 FPR64:$Rn)>;
2745 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2746 (FCVTMSv1i64 FPR64:$Rn)>;
2747 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2748 (FCVTMUv1i64 FPR64:$Rn)>;
2749 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2750 (FCVTNSv1i64 FPR64:$Rn)>;
2751 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2752 (FCVTNUv1i64 FPR64:$Rn)>;
2753 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2754 (FCVTPSv1i64 FPR64:$Rn)>;
2755 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2756 (FCVTPUv1i64 FPR64:$Rn)>;
2758 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2759 (FRECPEv1i32 FPR32:$Rn)>;
2760 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2761 (FRECPEv1i64 FPR64:$Rn)>;
2762 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2763 (FRECPEv1i64 FPR64:$Rn)>;
2765 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2766 (FRECPXv1i32 FPR32:$Rn)>;
2767 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2768 (FRECPXv1i64 FPR64:$Rn)>;
2770 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2771 (FRSQRTEv1i32 FPR32:$Rn)>;
2772 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2773 (FRSQRTEv1i64 FPR64:$Rn)>;
2774 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2775 (FRSQRTEv1i64 FPR64:$Rn)>;
2777 // If an integer is about to be converted to a floating point value,
2778 // just load it on the floating point unit.
2779 // Here are the patterns for 8 and 16-bits to float.
2781 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2782 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2783 (LDRBro ro_indexed8:$addr), bsub))>;
2784 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2785 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2786 (LDRBui am_indexed8:$addr), bsub))>;
2787 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2788 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2789 (LDURBi am_unscaled8:$addr), bsub))>;
2790 // 16-bits -> float.
2791 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2792 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2793 (LDRHro ro_indexed16:$addr), hsub))>;
2794 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2795 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2796 (LDRHui am_indexed16:$addr), hsub))>;
2797 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2798 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2799 (LDURHi am_unscaled16:$addr), hsub))>;
2800 // 32-bits are handled in target specific dag combine:
2801 // performIntToFpCombine.
2802 // 64-bits integer to 32-bits floating point, not possible with
2803 // UCVTF on floating point registers (both source and destination
2804 // must have the same size).
2806 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2807 // 8-bits -> double.
2808 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2809 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2810 (LDRBro ro_indexed8:$addr), bsub))>;
2811 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2812 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2813 (LDRBui am_indexed8:$addr), bsub))>;
2814 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2815 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2816 (LDURBi am_unscaled8:$addr), bsub))>;
2817 // 16-bits -> double.
2818 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2819 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2820 (LDRHro ro_indexed16:$addr), hsub))>;
2821 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2822 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2823 (LDRHui am_indexed16:$addr), hsub))>;
2824 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2825 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2826 (LDURHi am_unscaled16:$addr), hsub))>;
2827 // 32-bits -> double.
2828 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2829 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2830 (LDRSro ro_indexed32:$addr), ssub))>;
2831 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2832 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2833 (LDRSui am_indexed32:$addr), ssub))>;
2834 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2835 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2836 (LDURSi am_unscaled32:$addr), ssub))>;
2837 // 64-bits -> double are handled in target specific dag combine:
2838 // performIntToFpCombine.
2840 //===----------------------------------------------------------------------===//
2841 // Advanced SIMD three different-sized vector instructions.
2842 //===----------------------------------------------------------------------===//
2844 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2845 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2846 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2847 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2848 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2849 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2850 int_arm64_neon_sabd>;
2851 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2852 int_arm64_neon_sabd>;
2853 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2854 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2855 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2856 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2857 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2858 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2859 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2860 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2861 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2862 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2863 int_arm64_neon_sqadd>;
2864 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2865 int_arm64_neon_sqsub>;
2866 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2867 int_arm64_neon_sqdmull>;
2868 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2869 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2870 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2871 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2872 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2873 int_arm64_neon_uabd>;
2874 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2875 int_arm64_neon_uabd>;
2876 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2877 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2878 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2879 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2880 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2881 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2882 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2883 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2884 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2885 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2886 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2887 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2888 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2890 // Patterns for 64-bit pmull
2891 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2892 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2893 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2894 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2895 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2897 // CodeGen patterns for addhn and subhn instructions, which can actually be
2898 // written in LLVM IR without too much difficulty.
2901 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2902 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2903 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2905 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2906 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2908 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2909 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2910 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2912 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2913 V128:$Rn, V128:$Rm)>;
2914 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2915 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2917 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2918 V128:$Rn, V128:$Rm)>;
2919 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2920 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2922 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2923 V128:$Rn, V128:$Rm)>;
2926 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2927 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2928 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2930 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2931 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2933 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2934 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2935 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2937 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2938 V128:$Rn, V128:$Rm)>;
2939 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2940 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2942 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2943 V128:$Rn, V128:$Rm)>;
2944 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2945 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2947 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2948 V128:$Rn, V128:$Rm)>;
2950 //----------------------------------------------------------------------------
2951 // AdvSIMD bitwise extract from vector instruction.
2952 //----------------------------------------------------------------------------
2954 defm EXT : SIMDBitwiseExtract<"ext">;
2956 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2957 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2958 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2959 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2960 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2961 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2962 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2963 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2964 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2965 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2966 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2967 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2968 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2969 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2970 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2971 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2973 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2975 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2976 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2977 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2978 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2979 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2980 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2981 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2982 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2983 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2984 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2985 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2986 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2989 //----------------------------------------------------------------------------
2990 // AdvSIMD zip vector
2991 //----------------------------------------------------------------------------
2993 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2994 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2995 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2996 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2997 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2998 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
3000 //----------------------------------------------------------------------------
3001 // AdvSIMD TBL/TBX instructions
3002 //----------------------------------------------------------------------------
3004 defm TBL : SIMDTableLookup< 0, "tbl">;
3005 defm TBX : SIMDTableLookupTied<1, "tbx">;
3007 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3008 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3009 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3010 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3012 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
3013 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3014 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3015 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
3016 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3017 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3020 //----------------------------------------------------------------------------
3021 // AdvSIMD scalar CPY instruction
3022 //----------------------------------------------------------------------------
3024 defm CPY : SIMDScalarCPY<"cpy">;
3026 //----------------------------------------------------------------------------
3027 // AdvSIMD scalar pairwise instructions
3028 //----------------------------------------------------------------------------
3030 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3031 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3032 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3033 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3034 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3035 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3036 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
3037 (ADDPv2i64p V128:$Rn)>;
3038 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
3039 (ADDPv2i64p V128:$Rn)>;
3040 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
3041 (FADDPv2i32p V64:$Rn)>;
3042 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
3043 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3044 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
3045 (FADDPv2i64p V128:$Rn)>;
3046 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
3047 (FMAXNMPv2i32p V64:$Rn)>;
3048 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
3049 (FMAXNMPv2i64p V128:$Rn)>;
3050 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
3051 (FMAXPv2i32p V64:$Rn)>;
3052 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
3053 (FMAXPv2i64p V128:$Rn)>;
3054 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
3055 (FMINNMPv2i32p V64:$Rn)>;
3056 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
3057 (FMINNMPv2i64p V128:$Rn)>;
3058 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3059 (FMINPv2i32p V64:$Rn)>;
3060 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
3061 (FMINPv2i64p V128:$Rn)>;
3063 //----------------------------------------------------------------------------
3064 // AdvSIMD INS/DUP instructions
3065 //----------------------------------------------------------------------------
3067 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3068 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3069 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3070 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3071 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3072 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3073 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3075 def DUPv2i64lane : SIMDDup64FromElement;
3076 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3077 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3078 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3079 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3080 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3081 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3083 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3084 (v2f32 (DUPv2i32lane
3085 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3087 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3088 (v4f32 (DUPv4i32lane
3089 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3091 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3092 (v2f64 (DUPv2i64lane
3093 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3096 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3097 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3098 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3099 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3100 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3101 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3103 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3104 // instruction even if the types don't match: we just have to remap the lane
3105 // carefully. N.b. this trick only applies to truncations.
3106 def VecIndex_x2 : SDNodeXForm<imm, [{
3107 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3109 def VecIndex_x4 : SDNodeXForm<imm, [{
3110 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3112 def VecIndex_x8 : SDNodeXForm<imm, [{
3113 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3116 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3117 ValueType Src128VT, ValueType ScalVT,
3118 Instruction DUP, SDNodeXForm IdxXFORM> {
3119 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3121 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3123 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3125 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3128 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3129 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3130 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3132 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3133 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3134 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3136 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3137 SDNodeXForm IdxXFORM> {
3138 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3140 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3142 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3144 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3147 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3148 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3149 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3151 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3152 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3153 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3155 // SMOV and UMOV definitions, with some extra patterns for convenience
3159 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3160 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3161 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3162 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3163 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3164 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3165 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3166 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3167 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3168 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3169 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3170 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3172 // Extracting i8 or i16 elements will have the zero-extend transformed to
3173 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3174 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3175 // bits of the destination register.
3176 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3178 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3179 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3181 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3185 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3186 (SUBREG_TO_REG (i32 0),
3187 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3188 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3189 (SUBREG_TO_REG (i32 0),
3190 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3192 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3193 (SUBREG_TO_REG (i32 0),
3194 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3195 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3196 (SUBREG_TO_REG (i32 0),
3197 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3199 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3200 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3201 (i32 FPR32:$Rn), ssub))>;
3202 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3203 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3204 (i32 FPR32:$Rn), ssub))>;
3205 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3206 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3207 (i64 FPR64:$Rn), dsub))>;
3209 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3210 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3211 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3212 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3213 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3214 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3216 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3217 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3220 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3222 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3225 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3226 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3228 V128:$Rn, VectorIndexS:$imm,
3229 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3231 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3232 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3234 V128:$Rn, VectorIndexD:$imm,
3235 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3238 // Copy an element at a constant index in one vector into a constant indexed
3239 // element of another.
3240 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3241 // index type and INS extension
3242 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3243 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3244 VectorIndexB:$idx2)),
3246 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3248 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3249 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3250 VectorIndexH:$idx2)),
3252 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3254 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3255 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3256 VectorIndexS:$idx2)),
3258 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3260 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3261 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3262 VectorIndexD:$idx2)),
3264 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3267 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3268 ValueType VTScal, Instruction INS> {
3269 def : Pat<(VT128 (vector_insert V128:$src,
3270 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3272 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3274 def : Pat<(VT128 (vector_insert V128:$src,
3275 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3277 (INS V128:$src, imm:$Immd,
3278 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3280 def : Pat<(VT64 (vector_insert V64:$src,
3281 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3283 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3284 imm:$Immd, V128:$Rn, imm:$Immn),
3287 def : Pat<(VT64 (vector_insert V64:$src,
3288 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3291 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3292 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3296 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3297 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3298 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3299 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3300 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3301 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3304 // Floating point vector extractions are codegen'd as either a sequence of
3305 // subregister extractions, possibly fed by an INS if the lane number is
3306 // anything other than zero.
3307 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3308 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3309 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3310 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3311 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3312 (f64 (EXTRACT_SUBREG
3313 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3314 V128:$Rn, VectorIndexD:$idx),
3316 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3317 (f32 (EXTRACT_SUBREG
3318 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3319 V128:$Rn, VectorIndexS:$idx),
3322 // All concat_vectors operations are canonicalised to act on i64 vectors for
3323 // ARM64. In the general case we need an instruction, which had just as well be
3325 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3326 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3327 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3328 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3330 def : ConcatPat<v2i64, v1i64>;
3331 def : ConcatPat<v2f64, v1f64>;
3332 def : ConcatPat<v4i32, v2i32>;
3333 def : ConcatPat<v4f32, v2f32>;
3334 def : ConcatPat<v8i16, v4i16>;
3335 def : ConcatPat<v16i8, v8i8>;
3337 // If the high lanes are undef, though, we can just ignore them:
3338 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3339 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3340 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3342 def : ConcatUndefPat<v2i64, v1i64>;
3343 def : ConcatUndefPat<v2f64, v1f64>;
3344 def : ConcatUndefPat<v4i32, v2i32>;
3345 def : ConcatUndefPat<v4f32, v2f32>;
3346 def : ConcatUndefPat<v8i16, v4i16>;
3347 def : ConcatUndefPat<v16i8, v8i8>;
3349 //----------------------------------------------------------------------------
3350 // AdvSIMD across lanes instructions
3351 //----------------------------------------------------------------------------
3353 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3354 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3355 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3356 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3357 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3358 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3359 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3360 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3361 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3362 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3363 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3365 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3366 // If there is a sign extension after this intrinsic, consume it as smov already
3368 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3370 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3371 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3373 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3375 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3376 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3378 // If there is a sign extension after this intrinsic, consume it as smov already
3380 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3382 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3383 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3385 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3387 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3388 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3390 // If there is a sign extension after this intrinsic, consume it as smov already
3392 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3394 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3395 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3397 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3399 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3400 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3402 // If there is a sign extension after this intrinsic, consume it as smov already
3404 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3406 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3407 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3409 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3411 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3412 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3415 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3416 (i32 (EXTRACT_SUBREG
3417 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3418 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3422 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3423 // If there is a masking operation keeping only what has been actually
3424 // generated, consume it.
3425 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3426 (i32 (EXTRACT_SUBREG
3427 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3428 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3430 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3431 (i32 (EXTRACT_SUBREG
3432 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3433 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3435 // If there is a masking operation keeping only what has been actually
3436 // generated, consume it.
3437 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3438 (i32 (EXTRACT_SUBREG
3439 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3440 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3442 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3443 (i32 (EXTRACT_SUBREG
3444 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3445 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3448 // If there is a masking operation keeping only what has been actually
3449 // generated, consume it.
3450 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3451 (i32 (EXTRACT_SUBREG
3452 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3453 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3455 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3456 (i32 (EXTRACT_SUBREG
3457 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3458 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3460 // If there is a masking operation keeping only what has been actually
3461 // generated, consume it.
3462 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3463 (i32 (EXTRACT_SUBREG
3464 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3465 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3467 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3468 (i32 (EXTRACT_SUBREG
3469 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3470 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3473 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3474 (i32 (EXTRACT_SUBREG
3475 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3476 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3481 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3482 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3484 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3485 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3487 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3489 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3490 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3493 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3494 (i32 (EXTRACT_SUBREG
3495 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3496 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3498 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3499 (i32 (EXTRACT_SUBREG
3500 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3501 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3504 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3505 (i64 (EXTRACT_SUBREG
3506 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3507 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3511 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3513 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3514 (i32 (EXTRACT_SUBREG
3515 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3516 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3518 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3519 (i32 (EXTRACT_SUBREG
3520 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3521 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3524 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3525 (i32 (EXTRACT_SUBREG
3526 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3527 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3529 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3530 (i32 (EXTRACT_SUBREG
3531 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3532 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3535 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3536 (i64 (EXTRACT_SUBREG
3537 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3538 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3542 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3543 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3544 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3545 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3547 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3548 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3549 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3550 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3552 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3553 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3554 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3556 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3557 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3558 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3560 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3561 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3562 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3564 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3565 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3566 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3568 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3569 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3571 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3572 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3573 (i64 (EXTRACT_SUBREG
3574 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3575 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3577 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3578 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3579 (i64 (EXTRACT_SUBREG
3580 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3581 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3584 //------------------------------------------------------------------------------
3585 // AdvSIMD modified immediate instructions
3586 //------------------------------------------------------------------------------
3589 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3591 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3595 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3597 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3598 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3600 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3601 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3603 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3607 // EDIT byte mask: scalar
3608 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3609 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3610 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3611 // The movi_edit node has the immediate value already encoded, so we use
3612 // a plain imm0_255 here.
3613 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3614 (MOVID imm0_255:$shift)>;
3616 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3617 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3618 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3619 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3621 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3622 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3623 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3624 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3626 // EDIT byte mask: 2d
3628 // The movi_edit node has the immediate value already encoded, so we use
3629 // a plain imm0_255 in the pattern
3630 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3631 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3634 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3637 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3638 // Complexity is added to break a tie with a plain MOVI.
3639 let AddedComplexity = 1 in {
3640 def : Pat<(f32 fpimm0),
3641 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3643 def : Pat<(f64 fpimm0),
3644 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3648 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3649 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3650 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3651 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3653 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3654 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3655 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3656 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3658 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3659 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3661 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3662 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3663 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3664 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3665 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3666 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3667 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3668 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3669 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3670 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3672 // EDIT per word: 2s & 4s with MSL shifter
3673 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3674 [(set (v2i32 V64:$Rd),
3675 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3676 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3677 [(set (v4i32 V128:$Rd),
3678 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3680 // Per byte: 8b & 16b
3681 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3683 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3684 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3686 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3690 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3691 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3692 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3693 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3694 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3695 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3696 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3697 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3698 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3699 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3701 // EDIT per word: 2s & 4s with MSL shifter
3702 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3703 [(set (v2i32 V64:$Rd),
3704 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3705 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3706 [(set (v4i32 V128:$Rd),
3707 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3709 //----------------------------------------------------------------------------
3710 // AdvSIMD indexed element
3711 //----------------------------------------------------------------------------
3713 let neverHasSideEffects = 1 in {
3714 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3715 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3718 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3719 // instruction expects the addend first, while the intrinsic expects it last.
3721 // On the other hand, there are quite a few valid combinatorial options due to
3722 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3723 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3724 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3725 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3726 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3728 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3729 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3730 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3731 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3732 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3733 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3734 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3735 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3737 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3738 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3740 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3741 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3742 VectorIndexS:$idx))),
3743 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3744 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3745 (v2f32 (ARM64duplane32
3746 (v4f32 (insert_subvector undef,
3747 (v2f32 (fneg V64:$Rm)),
3749 VectorIndexS:$idx)))),
3750 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3751 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3752 VectorIndexS:$idx)>;
3753 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3754 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3755 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3756 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3758 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3760 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3761 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3762 VectorIndexS:$idx))),
3763 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3764 VectorIndexS:$idx)>;
3765 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3766 (v4f32 (ARM64duplane32
3767 (v4f32 (insert_subvector undef,
3768 (v2f32 (fneg V64:$Rm)),
3770 VectorIndexS:$idx)))),
3771 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3772 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3773 VectorIndexS:$idx)>;
3774 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3775 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3776 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3777 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3779 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3780 // (DUPLANE from 64-bit would be trivial).
3781 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3782 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3783 VectorIndexD:$idx))),
3785 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3786 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3787 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3788 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3789 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3791 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3792 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3793 (vector_extract (v4f32 (fneg V128:$Rm)),
3794 VectorIndexS:$idx))),
3795 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3796 V128:$Rm, VectorIndexS:$idx)>;
3797 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3798 (vector_extract (v2f32 (fneg V64:$Rm)),
3799 VectorIndexS:$idx))),
3800 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3801 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3803 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3804 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3805 (vector_extract (v2f64 (fneg V128:$Rm)),
3806 VectorIndexS:$idx))),
3807 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3808 V128:$Rm, VectorIndexS:$idx)>;
3811 defm : FMLSIndexedAfterNegPatterns<
3812 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3813 defm : FMLSIndexedAfterNegPatterns<
3814 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3816 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3817 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3819 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3820 (FMULv2i32_indexed V64:$Rn,
3821 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3823 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3824 (FMULv4i32_indexed V128:$Rn,
3825 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3827 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3828 (FMULv2i64_indexed V128:$Rn,
3829 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3832 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3833 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3834 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3835 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3836 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3837 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3838 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3839 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3840 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3841 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3842 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3843 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3844 int_arm64_neon_smull>;
3845 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3846 int_arm64_neon_sqadd>;
3847 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3848 int_arm64_neon_sqsub>;
3849 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3850 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3851 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3852 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3853 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3854 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3855 int_arm64_neon_umull>;
3857 // A scalar sqdmull with the second operand being a vector lane can be
3858 // handled directly with the indexed instruction encoding.
3859 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3860 (vector_extract (v4i32 V128:$Vm),
3861 VectorIndexS:$idx)),
3862 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3864 //----------------------------------------------------------------------------
3865 // AdvSIMD scalar shift instructions
3866 //----------------------------------------------------------------------------
3867 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3868 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3869 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3870 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3871 // Codegen patterns for the above. We don't put these directly on the
3872 // instructions because TableGen's type inference can't handle the truth.
3873 // Having the same base pattern for fp <--> int totally freaks it out.
3874 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3875 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3876 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3877 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3878 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3879 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3880 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3881 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3882 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3884 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3885 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3887 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3888 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3889 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3890 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3891 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3892 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3893 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3894 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3895 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3896 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3898 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3899 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3901 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3903 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3904 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3905 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3906 int_arm64_neon_sqrshrn>;
3907 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3908 int_arm64_neon_sqrshrun>;
3909 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3910 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3911 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3912 int_arm64_neon_sqshrn>;
3913 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3914 int_arm64_neon_sqshrun>;
3915 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3916 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3917 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3918 TriOpFrag<(add node:$LHS,
3919 (ARM64srshri node:$MHS, node:$RHS))>>;
3920 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3921 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3922 TriOpFrag<(add node:$LHS,
3923 (ARM64vashr node:$MHS, node:$RHS))>>;
3924 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3925 int_arm64_neon_uqrshrn>;
3926 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3927 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3928 int_arm64_neon_uqshrn>;
3929 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3930 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3931 TriOpFrag<(add node:$LHS,
3932 (ARM64urshri node:$MHS, node:$RHS))>>;
3933 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3934 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3935 TriOpFrag<(add node:$LHS,
3936 (ARM64vlshr node:$MHS, node:$RHS))>>;
3938 //----------------------------------------------------------------------------
3939 // AdvSIMD vector shift instructions
3940 //----------------------------------------------------------------------------
3941 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3942 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3943 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3944 int_arm64_neon_vcvtfxs2fp>;
3945 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3946 int_arm64_neon_rshrn>;
3947 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3948 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3949 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3950 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3951 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3952 (i32 vecshiftL64:$imm))),
3953 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3954 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3955 int_arm64_neon_sqrshrn>;
3956 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3957 int_arm64_neon_sqrshrun>;
3958 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3959 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3960 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3961 int_arm64_neon_sqshrn>;
3962 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3963 int_arm64_neon_sqshrun>;
3964 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3965 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3966 (i32 vecshiftR64:$imm))),
3967 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3968 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3969 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3970 TriOpFrag<(add node:$LHS,
3971 (ARM64srshri node:$MHS, node:$RHS))> >;
3972 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3973 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3975 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3976 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3977 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3978 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3979 int_arm64_neon_vcvtfxu2fp>;
3980 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3981 int_arm64_neon_uqrshrn>;
3982 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3983 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3984 int_arm64_neon_uqshrn>;
3985 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3986 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3987 TriOpFrag<(add node:$LHS,
3988 (ARM64urshri node:$MHS, node:$RHS))> >;
3989 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3990 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3991 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3992 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3993 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3995 // SHRN patterns for when a logical right shift was used instead of arithmetic
3996 // (the immediate guarantees no sign bits actually end up in the result so it
3998 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3999 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4000 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4001 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4002 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4003 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4005 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4006 (trunc (ARM64vlshr (v8i16 V128:$Rn),
4007 vecshiftR16Narrow:$imm)))),
4008 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4009 V128:$Rn, vecshiftR16Narrow:$imm)>;
4010 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4011 (trunc (ARM64vlshr (v4i32 V128:$Rn),
4012 vecshiftR32Narrow:$imm)))),
4013 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4014 V128:$Rn, vecshiftR32Narrow:$imm)>;
4015 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4016 (trunc (ARM64vlshr (v2i64 V128:$Rn),
4017 vecshiftR64Narrow:$imm)))),
4018 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4019 V128:$Rn, vecshiftR32Narrow:$imm)>;
4021 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4022 // Anyexts are implemented as zexts.
4023 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4024 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4025 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4026 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4027 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4028 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4029 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4030 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4031 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4032 // Also match an extend from the upper half of a 128 bit source register.
4033 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4034 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4035 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4036 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4037 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4038 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4039 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4040 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4041 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4042 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4043 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4044 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4045 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4046 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4047 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4048 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4049 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4050 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4052 // Vector shift sxtl aliases
4053 def : InstAlias<"sxtl.8h $dst, $src1",
4054 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4055 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4056 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4057 def : InstAlias<"sxtl.4s $dst, $src1",
4058 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4059 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4060 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4061 def : InstAlias<"sxtl.2d $dst, $src1",
4062 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4063 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4064 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4066 // Vector shift sxtl2 aliases
4067 def : InstAlias<"sxtl2.8h $dst, $src1",
4068 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4069 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4070 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4071 def : InstAlias<"sxtl2.4s $dst, $src1",
4072 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4073 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4074 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4075 def : InstAlias<"sxtl2.2d $dst, $src1",
4076 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4077 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4078 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4080 // Vector shift uxtl aliases
4081 def : InstAlias<"uxtl.8h $dst, $src1",
4082 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4083 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4084 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4085 def : InstAlias<"uxtl.4s $dst, $src1",
4086 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4087 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4088 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4089 def : InstAlias<"uxtl.2d $dst, $src1",
4090 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4091 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4092 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4094 // Vector shift uxtl2 aliases
4095 def : InstAlias<"uxtl2.8h $dst, $src1",
4096 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4097 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4098 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4099 def : InstAlias<"uxtl2.4s $dst, $src1",
4100 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4101 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4102 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4103 def : InstAlias<"uxtl2.2d $dst, $src1",
4104 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4105 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4106 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4108 // If an integer is about to be converted to a floating point value,
4109 // just load it on the floating point unit.
4110 // These patterns are more complex because floating point loads do not
4111 // support sign extension.
4112 // The sign extension has to be explicitly added and is only supported for
4113 // one step: byte-to-half, half-to-word, word-to-doubleword.
4114 // SCVTF GPR -> FPR is 9 cycles.
4115 // SCVTF FPR -> FPR is 4 cyclces.
4116 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4117 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4118 // and still being faster.
4119 // However, this is not good for code size.
4120 // 8-bits -> float. 2 sizes step-up.
4121 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
4122 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4127 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4128 (LDRBro ro_indexed8:$addr),
4133 ssub)))>, Requires<[NotForCodeSize]>;
4134 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
4135 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4140 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4141 (LDRBui am_indexed8:$addr),
4146 ssub)))>, Requires<[NotForCodeSize]>;
4147 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
4148 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4153 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4154 (LDURBi am_unscaled8:$addr),
4159 ssub)))>, Requires<[NotForCodeSize]>;
4160 // 16-bits -> float. 1 size step-up.
4161 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4162 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4164 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4165 (LDRHro ro_indexed16:$addr),
4168 ssub)))>, Requires<[NotForCodeSize]>;
4169 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4170 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4172 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4173 (LDRHui am_indexed16:$addr),
4176 ssub)))>, Requires<[NotForCodeSize]>;
4177 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4178 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4180 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4181 (LDURHi am_unscaled16:$addr),
4184 ssub)))>, Requires<[NotForCodeSize]>;
4185 // 32-bits to 32-bits are handled in target specific dag combine:
4186 // performIntToFpCombine.
4187 // 64-bits integer to 32-bits floating point, not possible with
4188 // SCVTF on floating point registers (both source and destination
4189 // must have the same size).
4191 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4192 // 8-bits -> double. 3 size step-up: give up.
4193 // 16-bits -> double. 2 size step.
4194 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4195 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4200 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4201 (LDRHro ro_indexed16:$addr),
4206 dsub)))>, Requires<[NotForCodeSize]>;
4207 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4208 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4213 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4214 (LDRHui am_indexed16:$addr),
4219 dsub)))>, Requires<[NotForCodeSize]>;
4220 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4221 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4226 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4227 (LDURHi am_unscaled16:$addr),
4232 dsub)))>, Requires<[NotForCodeSize]>;
4233 // 32-bits -> double. 1 size step-up.
4234 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4235 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4237 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4238 (LDRSro ro_indexed32:$addr),
4241 dsub)))>, Requires<[NotForCodeSize]>;
4242 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4243 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4245 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4246 (LDRSui am_indexed32:$addr),
4249 dsub)))>, Requires<[NotForCodeSize]>;
4250 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4251 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4253 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4254 (LDURSi am_unscaled32:$addr),
4257 dsub)))>, Requires<[NotForCodeSize]>;
4258 // 64-bits -> double are handled in target specific dag combine:
4259 // performIntToFpCombine.
4262 //----------------------------------------------------------------------------
4263 // AdvSIMD Load-Store Structure
4264 //----------------------------------------------------------------------------
4265 defm LD1 : SIMDLd1Multiple<"ld1">;
4266 defm LD2 : SIMDLd2Multiple<"ld2">;
4267 defm LD3 : SIMDLd3Multiple<"ld3">;
4268 defm LD4 : SIMDLd4Multiple<"ld4">;
4270 defm ST1 : SIMDSt1Multiple<"st1">;
4271 defm ST2 : SIMDSt2Multiple<"st2">;
4272 defm ST3 : SIMDSt3Multiple<"st3">;
4273 defm ST4 : SIMDSt4Multiple<"st4">;
4275 class Ld1Pat<ValueType ty, Instruction INST>
4276 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4278 def : Ld1Pat<v16i8, LD1Onev16b>;
4279 def : Ld1Pat<v8i16, LD1Onev8h>;
4280 def : Ld1Pat<v4i32, LD1Onev4s>;
4281 def : Ld1Pat<v2i64, LD1Onev2d>;
4282 def : Ld1Pat<v8i8, LD1Onev8b>;
4283 def : Ld1Pat<v4i16, LD1Onev4h>;
4284 def : Ld1Pat<v2i32, LD1Onev2s>;
4285 def : Ld1Pat<v1i64, LD1Onev1d>;
4287 class St1Pat<ValueType ty, Instruction INST>
4288 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4289 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4291 def : St1Pat<v16i8, ST1Onev16b>;
4292 def : St1Pat<v8i16, ST1Onev8h>;
4293 def : St1Pat<v4i32, ST1Onev4s>;
4294 def : St1Pat<v2i64, ST1Onev2d>;
4295 def : St1Pat<v8i8, ST1Onev8b>;
4296 def : St1Pat<v4i16, ST1Onev4h>;
4297 def : St1Pat<v2i32, ST1Onev2s>;
4298 def : St1Pat<v1i64, ST1Onev1d>;
4304 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4305 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4306 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4307 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4308 let mayLoad = 1, neverHasSideEffects = 1 in {
4309 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4310 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4311 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4312 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4313 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4314 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4315 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4316 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4317 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4318 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4319 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4320 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4321 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4322 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4323 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4324 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4327 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4328 (LD1Rv8b am_simdnoindex:$vaddr)>;
4329 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4330 (LD1Rv16b am_simdnoindex:$vaddr)>;
4331 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4332 (LD1Rv4h am_simdnoindex:$vaddr)>;
4333 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4334 (LD1Rv8h am_simdnoindex:$vaddr)>;
4335 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4336 (LD1Rv2s am_simdnoindex:$vaddr)>;
4337 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4338 (LD1Rv4s am_simdnoindex:$vaddr)>;
4339 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4340 (LD1Rv2d am_simdnoindex:$vaddr)>;
4341 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4342 (LD1Rv1d am_simdnoindex:$vaddr)>;
4343 // Grab the floating point version too
4344 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4345 (LD1Rv2s am_simdnoindex:$vaddr)>;
4346 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4347 (LD1Rv4s am_simdnoindex:$vaddr)>;
4348 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4349 (LD1Rv2d am_simdnoindex:$vaddr)>;
4350 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4351 (LD1Rv1d am_simdnoindex:$vaddr)>;
4353 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4354 ValueType VTy, ValueType STy, Instruction LD1>
4355 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4356 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4357 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4359 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4360 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4361 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4362 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4363 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4364 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4366 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4367 ValueType VTy, ValueType STy, Instruction LD1>
4368 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4369 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4371 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4372 VecIndex:$idx, am_simdnoindex:$vaddr),
4375 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4376 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4377 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4378 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4381 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4382 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4383 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4384 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4387 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4388 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4389 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4390 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4392 let AddedComplexity = 8 in
4393 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4394 ValueType VTy, ValueType STy, Instruction ST1>
4396 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4397 am_simdnoindex:$vaddr),
4398 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4400 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4401 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4402 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4403 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4404 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4405 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4407 let AddedComplexity = 8 in
4408 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4409 ValueType VTy, ValueType STy, Instruction ST1>
4411 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4412 am_simdnoindex:$vaddr),
4413 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4414 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4416 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4417 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4418 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4419 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4421 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4422 ValueType VTy, ValueType STy, Instruction ST1,
4424 def : Pat<(scalar_store
4425 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4426 am_simdnoindex:$vaddr, offset),
4427 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4428 VecIndex:$idx, am_simdnoindex:$vaddr, XZR)>;
4430 def : Pat<(scalar_store
4431 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4432 am_simdnoindex:$vaddr, GPR64:$Rm),
4433 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4434 VecIndex:$idx, am_simdnoindex:$vaddr, $Rm)>;
4437 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4438 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4440 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4441 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4442 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4443 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4445 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4446 ValueType VTy, ValueType STy, Instruction ST1,
4448 def : Pat<(scalar_store
4449 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4450 am_simdnoindex:$vaddr, offset),
4451 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr, XZR)>;
4453 def : Pat<(scalar_store
4454 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4455 am_simdnoindex:$vaddr, GPR64:$Rm),
4456 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr, $Rm)>;
4459 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4461 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4463 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4464 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4465 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4466 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4468 let mayStore = 1, neverHasSideEffects = 1 in {
4469 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4470 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4471 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4472 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4473 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4474 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4475 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4476 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4477 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4478 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4479 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4480 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4483 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4484 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4485 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4486 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4488 //----------------------------------------------------------------------------
4489 // Crypto extensions
4490 //----------------------------------------------------------------------------
4492 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4493 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4494 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4495 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4497 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4498 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4499 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4500 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4501 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4502 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4503 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4505 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4506 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4507 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4509 //----------------------------------------------------------------------------
4511 //----------------------------------------------------------------------------
4512 // FIXME: Like for X86, these should go in their own separate .td file.
4514 // Any instruction that defines a 32-bit result leaves the high half of the
4515 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4516 // be copying from a truncate. But any other 32-bit operation will zero-extend
4518 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4519 def def32 : PatLeaf<(i32 GPR32:$src), [{
4520 return N->getOpcode() != ISD::TRUNCATE &&
4521 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4522 N->getOpcode() != ISD::CopyFromReg;
4525 // In the case of a 32-bit def that is known to implicitly zero-extend,
4526 // we can use a SUBREG_TO_REG.
4527 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4529 // For an anyext, we don't care what the high bits are, so we can perform an
4530 // INSERT_SUBREF into an IMPLICIT_DEF.
4531 def : Pat<(i64 (anyext GPR32:$src)),
4532 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4534 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4535 // instruction (UBFM) on the enclosing super-reg.
4536 def : Pat<(i64 (zext GPR32:$src)),
4537 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4539 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4540 // containing super-reg.
4541 def : Pat<(i64 (sext GPR32:$src)),
4542 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4543 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4544 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4545 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4546 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4547 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4548 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4549 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4551 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4552 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4553 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4554 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4555 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4556 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4558 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4559 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4560 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4561 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4562 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4563 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4565 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4566 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4567 (i64 (i64shift_a imm0_63:$imm)),
4568 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4570 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4571 // AddedComplexity for the following patterns since we want to match sext + sra
4572 // patterns before we attempt to match a single sra node.
4573 let AddedComplexity = 20 in {
4574 // We support all sext + sra combinations which preserve at least one bit of the
4575 // original value which is to be sign extended. E.g. we support shifts up to
4577 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4578 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4579 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4580 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4582 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4583 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4584 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4585 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4587 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4588 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4589 (i64 imm0_31:$imm), 31)>;
4590 } // AddedComplexity = 20
4592 // To truncate, we can simply extract from a subregister.
4593 def : Pat<(i32 (trunc GPR64sp:$src)),
4594 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4596 // __builtin_trap() uses the BRK instruction on ARM64.
4597 def : Pat<(trap), (BRK 1)>;
4599 // Conversions within AdvSIMD types in the same register size are free.
4600 // But because we need a consistent lane ordering, in big endian many
4601 // conversions require one or more REV instructions.
4603 // Consider a simple memory load followed by a bitconvert then a store.
4605 // v1 = BITCAST v2i32 v0 to v4i16
4608 // In big endian mode every memory access has an implicit byte swap. LDR and
4609 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4610 // is, they treat the vector as a sequence of elements to be byte-swapped.
4611 // The two pairs of instructions are fundamentally incompatible. We've decided
4612 // to use LD1/ST1 only to simplify compiler implementation.
4614 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4615 // the original code sequence:
4617 // v1 = REV v2i32 (implicit)
4618 // v2 = BITCAST v2i32 v1 to v4i16
4619 // v3 = REV v4i16 v2 (implicit)
4622 // But this is now broken - the value stored is different to the value loaded
4623 // due to lane reordering. To fix this, on every BITCAST we must perform two
4626 // v1 = REV v2i32 (implicit)
4628 // v3 = BITCAST v2i32 v2 to v4i16
4630 // v5 = REV v4i16 v4 (implicit)
4633 // This means an extra two instructions, but actually in most cases the two REV
4634 // instructions can be combined into one. For example:
4635 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4637 // There is also no 128-bit REV instruction. This must be synthesized with an
4640 // Most bitconverts require some sort of conversion. The only exceptions are:
4641 // a) Identity conversions - vNfX <-> vNiX
4642 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4645 let Predicates = [IsLE] in {
4646 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4647 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4648 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4649 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4651 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4652 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4653 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4654 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4655 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4656 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4657 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4658 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4659 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4660 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4662 let Predicates = [IsBE] in {
4663 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4664 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4665 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4666 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4667 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4668 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4669 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4670 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4672 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4673 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4674 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4675 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4676 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4677 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4678 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4679 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4681 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4682 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4683 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4684 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4685 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4686 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4687 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4688 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4689 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4691 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4692 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4693 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4694 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4695 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4696 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4697 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4698 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4699 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4700 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4702 let Predicates = [IsLE] in {
4703 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4704 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4705 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4706 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4708 let Predicates = [IsBE] in {
4709 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
4710 (v1i64 (REV64v2i32 FPR64:$src))>;
4711 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
4712 (v1i64 (REV64v4i16 FPR64:$src))>;
4713 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
4714 (v1i64 (REV64v8i8 FPR64:$src))>;
4715 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
4716 (v1i64 (REV64v2i32 FPR64:$src))>;
4718 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4719 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4721 let Predicates = [IsLE] in {
4722 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4723 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4724 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4725 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4726 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4728 let Predicates = [IsBE] in {
4729 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
4730 (v2i32 (REV64v2i32 FPR64:$src))>;
4731 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
4732 (v2i32 (REV32v4i16 FPR64:$src))>;
4733 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
4734 (v2i32 (REV32v8i8 FPR64:$src))>;
4735 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
4736 (v2i32 (REV64v2i32 FPR64:$src))>;
4737 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
4738 (v2i32 (REV64v2i32 FPR64:$src))>;
4740 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4742 let Predicates = [IsLE] in {
4743 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4744 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4745 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4746 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4747 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4748 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4750 let Predicates = [IsBE] in {
4751 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
4752 (v4i16 (REV64v4i16 FPR64:$src))>;
4753 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
4754 (v4i16 (REV32v4i16 FPR64:$src))>;
4755 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
4756 (v4i16 (REV16v8i8 FPR64:$src))>;
4757 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
4758 (v4i16 (REV64v4i16 FPR64:$src))>;
4759 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
4760 (v4i16 (REV32v4i16 FPR64:$src))>;
4761 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
4762 (v4i16 (REV64v4i16 FPR64:$src))>;
4765 let Predicates = [IsLE] in {
4766 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4767 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4768 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4769 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4770 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4771 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4773 let Predicates = [IsBE] in {
4774 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
4775 (v8i8 (REV64v8i8 FPR64:$src))>;
4776 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
4777 (v8i8 (REV32v8i8 FPR64:$src))>;
4778 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
4779 (v8i8 (REV16v8i8 FPR64:$src))>;
4780 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
4781 (v8i8 (REV64v8i8 FPR64:$src))>;
4782 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
4783 (v8i8 (REV32v8i8 FPR64:$src))>;
4784 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
4785 (v8i8 (REV64v8i8 FPR64:$src))>;
4788 let Predicates = [IsLE] in {
4789 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4790 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4791 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4792 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4794 let Predicates = [IsBE] in {
4795 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
4796 (f64 (REV64v2i32 FPR64:$src))>;
4797 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
4798 (f64 (REV64v4i16 FPR64:$src))>;
4799 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
4800 (f64 (REV64v2i32 FPR64:$src))>;
4801 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
4802 (f64 (REV64v8i8 FPR64:$src))>;
4804 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4805 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4807 let Predicates = [IsLE] in {
4808 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4809 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4810 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4811 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4813 let Predicates = [IsBE] in {
4814 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
4815 (v1f64 (REV64v2i32 FPR64:$src))>;
4816 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
4817 (v1f64 (REV64v4i16 FPR64:$src))>;
4818 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
4819 (v1f64 (REV64v8i8 FPR64:$src))>;
4820 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
4821 (v1f64 (REV64v2i32 FPR64:$src))>;
4823 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4824 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4826 let Predicates = [IsLE] in {
4827 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4828 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4829 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4830 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4831 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4833 let Predicates = [IsBE] in {
4834 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
4835 (v2f32 (REV64v2i32 FPR64:$src))>;
4836 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
4837 (v2f32 (REV32v4i16 FPR64:$src))>;
4838 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
4839 (v2f32 (REV32v8i8 FPR64:$src))>;
4840 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
4841 (v2f32 (REV64v2i32 FPR64:$src))>;
4842 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
4843 (v2f32 (REV64v2i32 FPR64:$src))>;
4845 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4847 let Predicates = [IsLE] in {
4848 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4849 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4850 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4851 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4852 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4853 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
4855 let Predicates = [IsBE] in {
4856 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
4857 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
4858 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
4859 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
4860 (REV64v4i32 FPR128:$src), (i32 8)))>;
4861 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
4862 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
4863 (REV64v8i16 FPR128:$src), (i32 8)))>;
4864 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
4865 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
4866 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
4867 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
4868 (REV64v4i32 FPR128:$src), (i32 8)))>;
4869 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
4870 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
4871 (REV64v16i8 FPR128:$src), (i32 8)))>;
4874 let Predicates = [IsLE] in {
4875 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4876 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4877 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4878 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4879 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4881 let Predicates = [IsBE] in {
4882 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
4883 (v2f64 (EXTv16i8 FPR128:$src,
4884 FPR128:$src, (i32 8)))>;
4885 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
4886 (v2f64 (REV64v4i32 FPR128:$src))>;
4887 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
4888 (v2f64 (REV64v8i16 FPR128:$src))>;
4889 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
4890 (v2f64 (REV64v16i8 FPR128:$src))>;
4891 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
4892 (v2f64 (REV64v4i32 FPR128:$src))>;
4894 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4896 let Predicates = [IsLE] in {
4897 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4898 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4899 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4900 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4901 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4903 let Predicates = [IsBE] in {
4904 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
4905 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
4906 (REV64v4i32 FPR128:$src), (i32 8)))>;
4907 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
4908 (v4f32 (REV32v8i16 FPR128:$src))>;
4909 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
4910 (v4f32 (REV32v16i8 FPR128:$src))>;
4911 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
4912 (v4f32 (REV64v4i32 FPR128:$src))>;
4913 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
4914 (v4f32 (REV64v4i32 FPR128:$src))>;
4916 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4918 let Predicates = [IsLE] in {
4919 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4920 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4921 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4922 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4923 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4925 let Predicates = [IsBE] in {
4926 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
4927 (v2i64 (EXTv16i8 FPR128:$src,
4928 FPR128:$src, (i32 8)))>;
4929 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
4930 (v2i64 (REV64v4i32 FPR128:$src))>;
4931 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
4932 (v2i64 (REV64v8i16 FPR128:$src))>;
4933 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
4934 (v2i64 (REV64v16i8 FPR128:$src))>;
4935 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
4936 (v2i64 (REV64v4i32 FPR128:$src))>;
4938 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4940 let Predicates = [IsLE] in {
4941 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4942 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4943 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4944 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4945 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4947 let Predicates = [IsBE] in {
4948 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
4949 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
4950 (REV64v4i32 FPR128:$src),
4952 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
4953 (v4i32 (REV64v4i32 FPR128:$src))>;
4954 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
4955 (v4i32 (REV32v8i16 FPR128:$src))>;
4956 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
4957 (v4i32 (REV32v16i8 FPR128:$src))>;
4958 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
4959 (v4i32 (REV64v4i32 FPR128:$src))>;
4961 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4963 let Predicates = [IsLE] in {
4964 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4965 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4966 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4967 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4968 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4969 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4971 let Predicates = [IsBE] in {
4972 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
4973 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
4974 (REV64v8i16 FPR128:$src),
4976 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
4977 (v8i16 (REV64v8i16 FPR128:$src))>;
4978 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
4979 (v8i16 (REV32v8i16 FPR128:$src))>;
4980 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
4981 (v8i16 (REV16v16i8 FPR128:$src))>;
4982 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
4983 (v8i16 (REV64v8i16 FPR128:$src))>;
4984 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
4985 (v8i16 (REV32v8i16 FPR128:$src))>;
4988 let Predicates = [IsLE] in {
4989 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4990 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4991 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4992 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4993 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4994 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4996 let Predicates = [IsBE] in {
4997 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
4998 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
4999 (REV64v16i8 FPR128:$src),
5001 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5002 (v16i8 (REV64v16i8 FPR128:$src))>;
5003 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5004 (v16i8 (REV32v16i8 FPR128:$src))>;
5005 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5006 (v16i8 (REV16v16i8 FPR128:$src))>;
5007 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5008 (v16i8 (REV64v16i8 FPR128:$src))>;
5009 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5010 (v16i8 (REV32v16i8 FPR128:$src))>;
5013 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5014 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5015 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5016 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5017 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5018 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5019 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5020 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5022 // A 64-bit subvector insert to the first 128-bit vector position
5023 // is a subregister copy that needs no instruction.
5024 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5025 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5026 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5027 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5028 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5029 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5030 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5031 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5032 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5033 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5034 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5035 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5037 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5039 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5040 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5041 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5042 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5043 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5044 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5045 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5046 // so we match on v4f32 here, not v2f32. This will also catch adding
5047 // the low two lanes of a true v4f32 vector.
5048 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5049 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5050 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5052 // Scalar 64-bit shifts in FPR64 registers.
5053 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5054 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5055 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5056 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5057 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5058 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5059 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5060 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5062 // Tail call return handling. These are all compiler pseudo-instructions,
5063 // so no encoding information or anything like that.
5064 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5065 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
5066 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
5069 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
5070 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5071 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5073 include "ARM64InstrAtomics.td"