1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
25 : ARMFrameLowering(sti) {}
27 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
28 const MachineFrameInfo *FFI = MF.getFrameInfo();
29 unsigned CFSize = FFI->getMaxCallFrameSize();
30 // It's not always a good idea to include the call frame as part of the
31 // stack frame. ARM (especially Thumb) has small immediate offset to
32 // address the stack frame. So a large call frame can cause poor codegen
33 // and may even makes it impossible to scavenge a register.
34 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
37 return !MF.getFrameInfo()->hasVarSizedObjects();
41 emitSPUpdate(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator &MBBI,
43 const TargetInstrInfo &TII, DebugLoc dl,
44 const Thumb1RegisterInfo &MRI,
45 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
51 void Thumb1FrameLowering::
52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator I) const {
54 const Thumb1InstrInfo &TII =
55 *static_cast<const Thumb1InstrInfo *>(
56 MF.getTarget().getSubtargetImpl()->getInstrInfo());
57 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
58 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
59 if (!hasReservedCallFrame(MF)) {
60 // If we have alloca, convert as follows:
61 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
62 // ADJCALLSTACKUP -> add, sp, sp, amount
63 MachineInstr *Old = I;
64 DebugLoc dl = Old->getDebugLoc();
65 unsigned Amount = Old->getOperand(0).getImm();
67 // We need to keep the stack aligned properly. To do this, we round the
68 // amount of space needed for the outgoing arguments up to the next
69 // alignment boundary.
70 unsigned Align = getStackAlignment();
71 Amount = (Amount+Align-1)/Align*Align;
73 // Replace the pseudo instruction with a new instruction...
74 unsigned Opc = Old->getOpcode();
75 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
86 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
87 MachineBasicBlock &MBB = MF.front();
88 MachineBasicBlock::iterator MBBI = MBB.begin();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
91 MachineModuleInfo &MMI = MF.getMMI();
92 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
93 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
94 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
95 const Thumb1InstrInfo &TII =
96 *static_cast<const Thumb1InstrInfo *>(
97 MF.getTarget().getSubtargetImpl()->getInstrInfo());
99 unsigned Align = MF.getTarget()
102 ->getStackAlignment();
103 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
104 unsigned NumBytes = MFI->getStackSize();
105 assert(NumBytes >= ArgRegsSaveSize &&
106 "ArgRegsSaveSize is included in NumBytes");
107 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
108 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
109 unsigned FramePtr = RegInfo->getFrameRegister(MF);
110 unsigned BasePtr = RegInfo->getBaseRegister();
113 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
114 NumBytes = (NumBytes + 3) & ~3;
115 MFI->setStackSize(NumBytes);
117 // Determine the sizes of each callee-save spill areas and record which frame
118 // belongs to which callee-save spill areas.
119 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
120 int FramePtrSpillFI = 0;
122 if (ArgRegsSaveSize) {
123 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
124 MachineInstr::FrameSetup);
125 CFAOffset -= ArgRegsSaveSize;
126 unsigned CFIIndex = MMI.addFrameInst(
127 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
128 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
129 .addCFIIndex(CFIIndex);
132 if (!AFI->hasStackFrame()) {
133 if (NumBytes - ArgRegsSaveSize != 0) {
134 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
135 MachineInstr::FrameSetup);
136 CFAOffset -= NumBytes - ArgRegsSaveSize;
137 unsigned CFIIndex = MMI.addFrameInst(
138 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
139 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
140 .addCFIIndex(CFIIndex);
145 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
146 unsigned Reg = CSI[i].getReg();
147 int FI = CSI[i].getFrameIdx();
153 if (STI.isTargetMachO()) {
164 FramePtrSpillFI = FI;
172 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
174 if (MBBI != MBB.end())
175 dl = MBBI->getDebugLoc();
178 // Determine starting offsets of spill areas.
179 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
180 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
181 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
182 bool HasFP = hasFP(MF);
184 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
186 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
187 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
188 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
189 NumBytes = DPRCSOffset;
191 int FramePtrOffsetInBlock = 0;
192 unsigned adjustedGPRCS1Size = GPRCS1Size;
193 if (tryFoldSPUpdateIntoPushPop(STI, MF, std::prev(MBBI), NumBytes)) {
194 FramePtrOffsetInBlock = NumBytes;
195 adjustedGPRCS1Size += NumBytes;
199 if (adjustedGPRCS1Size) {
200 CFAOffset -= adjustedGPRCS1Size;
201 unsigned CFIIndex = MMI.addFrameInst(
202 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
203 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
204 .addCFIIndex(CFIIndex);
206 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
207 E = CSI.end(); I != E; ++I) {
208 unsigned Reg = I->getReg();
209 int FI = I->getFrameIdx();
216 if (STI.isTargetMachO())
228 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
229 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
230 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
231 .addCFIIndex(CFIIndex);
237 // Adjust FP so it point to the stack slot that contains the previous FP.
239 FramePtrOffsetInBlock += MFI->getObjectOffset(FramePtrSpillFI)
240 + GPRCS1Size + ArgRegsSaveSize;
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
242 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
243 .setMIFlags(MachineInstr::FrameSetup));
244 if(FramePtrOffsetInBlock) {
245 CFAOffset += FramePtrOffsetInBlock;
246 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
247 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
248 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
249 .addCFIIndex(CFIIndex);
252 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
253 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255 .addCFIIndex(CFIIndex);
258 // If offset is > 508 then sp cannot be adjusted in a single instruction,
259 // try restoring from fp instead.
260 AFI->setShouldRestoreSPFromFP(true);
264 // Insert it after all the callee-save spills.
265 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
266 MachineInstr::FrameSetup);
268 CFAOffset -= NumBytes;
269 unsigned CFIIndex = MMI.addFrameInst(
270 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
271 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
272 .addCFIIndex(CFIIndex);
276 if (STI.isTargetELF() && HasFP)
277 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
278 AFI->getFramePtrSpillOffset());
280 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
281 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
282 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
284 // Thumb1 does not currently support dynamic stack realignment. Report a
285 // fatal error rather then silently generate bad code.
286 if (RegInfo->needsStackRealignment(MF))
287 report_fatal_error("Dynamic stack realignment not supported for thumb1.");
289 // If we need a base pointer, set it up here. It's whatever the value
290 // of the stack pointer is at this point. Any variable size objects
291 // will be allocated after this, so we can still use the base pointer
292 // to reference locals.
293 if (RegInfo->hasBasePointer(MF))
294 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
297 // If the frame has variable sized objects then the epilogue must restore
298 // the sp from fp. We can assume there's an FP here since hasFP already
299 // checks for hasVarSizedObjects.
300 if (MFI->hasVarSizedObjects())
301 AFI->setShouldRestoreSPFromFP(true);
304 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
305 if (MI->getOpcode() == ARM::tLDRspi &&
306 MI->getOperand(1).isFI() &&
307 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
309 else if (MI->getOpcode() == ARM::tPOP) {
310 // The first two operands are predicates. The last two are
311 // imp-def and imp-use of SP. Check everything in between.
312 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
313 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
320 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
321 MachineBasicBlock &MBB) const {
322 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
323 assert((MBBI->getOpcode() == ARM::tBX_RET ||
324 MBBI->getOpcode() == ARM::tPOP_RET) &&
325 "Can only insert epilog into returning blocks");
326 DebugLoc dl = MBBI->getDebugLoc();
327 MachineFrameInfo *MFI = MF.getFrameInfo();
328 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
329 const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
330 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
331 const Thumb1InstrInfo &TII =
332 *static_cast<const Thumb1InstrInfo *>(
333 MF.getTarget().getSubtargetImpl()->getInstrInfo());
335 unsigned Align = MF.getTarget()
338 ->getStackAlignment();
339 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
340 int NumBytes = (int)MFI->getStackSize();
341 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
342 "ArgRegsSaveSize is included in NumBytes");
343 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
344 unsigned FramePtr = RegInfo->getFrameRegister(MF);
346 if (!AFI->hasStackFrame()) {
347 if (NumBytes - ArgRegsSaveSize != 0)
348 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
350 // Unwind MBBI to point to first LDR / VLDRD.
351 if (MBBI != MBB.begin()) {
354 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
355 if (!isCSRestore(MBBI, CSRegs))
359 // Move SP to start of FP callee save spill area.
360 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
361 AFI->getGPRCalleeSavedArea2Size() +
362 AFI->getDPRCalleeSavedAreaSize() +
365 if (AFI->shouldRestoreSPFromFP()) {
366 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
367 // Reset SP based on frame pointer only if the stack frame extends beyond
368 // frame pointer stack slot, the target is ELF and the function has FP, or
369 // the target uses var sized objects.
371 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
372 "No scratch register to restore SP from FP!");
373 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
375 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
379 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
383 if (MBBI->getOpcode() == ARM::tBX_RET &&
384 &MBB.front() != MBBI &&
385 std::prev(MBBI)->getOpcode() == ARM::tPOP) {
386 MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
387 if (!tryFoldSPUpdateIntoPushPop(STI, MF, PMBBI, NumBytes))
388 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
389 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
390 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
394 if (ArgRegsSaveSize) {
395 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
396 // to LR, and we can't pop the value directly to the PC since
397 // we need to update the SP after popping the value. Therefore, we
398 // pop the old LR into R3 as a temporary.
400 // Get the last instruction, tBX_RET
401 MBBI = MBB.getLastNonDebugInstr();
402 assert (MBBI->getOpcode() == ARM::tBX_RET);
403 // Epilogue for vararg functions: pop LR to R3 and branch off it.
404 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
405 .addReg(ARM::R3, RegState::Define);
407 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
409 MachineInstrBuilder MIB =
410 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
411 .addReg(ARM::R3, RegState::Kill);
413 MIB.copyImplicitOps(&*MBBI);
414 // erase the old tBX_RET instruction
419 bool Thumb1FrameLowering::
420 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
421 MachineBasicBlock::iterator MI,
422 const std::vector<CalleeSavedInfo> &CSI,
423 const TargetRegisterInfo *TRI) const {
428 MachineFunction &MF = *MBB.getParent();
429 const TargetInstrInfo &TII =
430 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
432 if (MI != MBB.end()) DL = MI->getDebugLoc();
434 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
436 for (unsigned i = CSI.size(); i != 0; --i) {
437 unsigned Reg = CSI[i-1].getReg();
440 // Add the callee-saved register as live-in unless it's LR and
441 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
442 // then it's already added to the function and entry block live-in sets.
443 if (Reg == ARM::LR) {
444 MachineFunction &MF = *MBB.getParent();
445 if (MF.getFrameInfo()->isReturnAddressTaken() &&
446 MF.getRegInfo().isLiveIn(Reg))
453 MIB.addReg(Reg, getKillRegState(isKill));
455 MIB.setMIFlags(MachineInstr::FrameSetup);
459 bool Thumb1FrameLowering::
460 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MI,
462 const std::vector<CalleeSavedInfo> &CSI,
463 const TargetRegisterInfo *TRI) const {
467 MachineFunction &MF = *MBB.getParent();
468 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
469 const TargetInstrInfo &TII =
470 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
472 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
473 DebugLoc DL = MI->getDebugLoc();
474 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
477 bool NumRegs = false;
478 for (unsigned i = CSI.size(); i != 0; --i) {
479 unsigned Reg = CSI[i-1].getReg();
480 if (Reg == ARM::LR) {
481 // Special epilogue for vararg functions. See emitEpilogue
485 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
486 MIB.copyImplicitOps(&*MI);
489 MIB.addReg(Reg, getDefRegState(true));
493 // It's illegal to emit pop instruction without operands.
495 MBB.insert(MI, &*MIB);
497 MF.DeleteMachineInstr(MIB);