lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

   1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
  16
  17 #include "llvm/Support/DataTypes.h"
  18 #include <string>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInstrInfo;
  26 class MCInstPrinter;
  27 class MCObjectWriter;
  28 class MCRegisterInfo;
  29 class MCSubtargetInfo;
  30 class MCStreamer;
  31 class MCRelocationInfo;
  32 class MCTargetStreamer;
  33 class StringRef;
  34 class Target;
  35 class raw_ostream;
  36
  37 extern Target TheARMLETarget, TheThumbLETarget;
  38 extern Target TheARMBETarget, TheThumbBETarget;
  39
  40 namespace ARM_MC {
  41   std::string ParseARMTriple(StringRef TT, StringRef CPU);
  42
  43   /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
  44   /// This is exposed so Asm parser, etc. do not need to go through
  45   /// TargetRegistry.
  46   MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
  47                                             StringRef FS);
  48 }
  49
  50 MCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
  51                                 bool isVerboseAsm, bool useDwarfDirectory,
  52                                 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
  53                                 MCAsmBackend *TAB, bool ShowInst);
  54
  55 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
  56
  57 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
  58                                         const MCRegisterInfo &MRI,
  59                                         const MCSubtargetInfo &STI,
  60                                         MCContext &Ctx);
  61
  62 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
  63                                         const MCRegisterInfo &MRI,
  64                                         const MCSubtargetInfo &STI,
  65                                         MCContext &Ctx);
  66
  67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  68                                   StringRef TT, StringRef CPU,
  69                                   bool IsLittleEndian);
  70
  71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  72                                   StringRef TT, StringRef CPU);
  73
  74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  75                                   StringRef TT, StringRef CPU);
  76
  77 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  78                                       StringRef TT, StringRef CPU);
  79
  80 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
  81                                       StringRef TT, StringRef CPU);
  82
  83 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which
  84 /// will generate a PE/COFF object file.
  85 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
  86                                      MCCodeEmitter &Emitter, raw_ostream &OS);
  87
  88 /// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
  89 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
  90                                          uint8_t OSABI,
  91                                          bool IsLittleEndian);
  92
  93 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
  94 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
  95                                           bool Is64Bit,
  96                                           uint32_t CPUType,
  97                                           uint32_t CPUSubtype);
  98
  99 /// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
 100 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
 101
 102 /// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
 103 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
 104 } // End llvm namespace
 105
 106 // Defines symbolic names for ARM registers.  This defines a mapping from
 107 // register name to register number.
 108 //
 109 #define GET_REGINFO_ENUM
 110 #include "ARMGenRegisterInfo.inc"
 111
 112 // Defines symbolic names for the ARM instructions.
 113 //
 114 #define GET_INSTRINFO_ENUM
 115 #include "ARMGenInstrInfo.inc"
 116
 117 #define GET_SUBTARGETINFO_ENUM
 118 #include "ARMGenSubtargetInfo.inc"
 119
 120 #endif