Use std::bitset for SubtargetFeatures
[oota-llvm.git] / lib / Target / ARM / MCTargetDesc / ARMMCTargetDesc.cpp
1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28
29 using namespace llvm;
30
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
33
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
35                                   std::string &Info) {
36   if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39       // Checks for the deprecated CP15ISB encoding:
40       // mcr p15, #0, rX, c7, c5, #4
41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44         Info = "deprecated since v7, use 'isb'";
45         return true;
46       }
47
48       // Checks for the deprecated CP15DSB encoding:
49       // mcr p15, #0, rX, c7, c10, #4
50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51         Info = "deprecated since v7, use 'dsb'";
52         return true;
53       }
54     }
55     // Checks for the deprecated CP15DMB encoding:
56     // mcr p15, #0, rX, c7, c10, #5
57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59       Info = "deprecated since v7, use 'dmb'";
60       return true;
61     }
62   }
63   return false;
64 }
65
66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
67                                  std::string &Info) {
68   if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
69       MI.getOperand(1).getImm() != 8) {
70     Info = "applying IT instruction to more than one subsequent instruction is "
71            "deprecated";
72     return true;
73   }
74
75   return false;
76 }
77
78 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
79                                        std::string &Info) {
80   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
81          "cannot predicate thumb instructions");
82
83   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
84   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
85     assert(MI.getOperand(OI).isReg() && "expected register");
86     if (MI.getOperand(OI).getReg() == ARM::SP ||
87         MI.getOperand(OI).getReg() == ARM::PC) {
88       Info = "use of SP or PC in the list is deprecated";
89       return true;
90     }
91   }
92   return false;
93 }
94
95 static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
96                                       std::string &Info) {
97   assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
98          "cannot predicate thumb instructions");
99
100   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
101   bool ListContainsPC = false, ListContainsLR = false;
102   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
103     assert(MI.getOperand(OI).isReg() && "expected register");
104     switch (MI.getOperand(OI).getReg()) {
105     default:
106       break;
107     case ARM::LR:
108       ListContainsLR = true;
109       break;
110     case ARM::PC:
111       ListContainsPC = true;
112       break;
113     case ARM::SP:
114       Info = "use of SP in the list is deprecated";
115       return true;
116     }
117   }
118
119   if (ListContainsPC && ListContainsLR) {
120     Info = "use of LR and PC simultaneously in the list is deprecated";
121     return true;
122   }
123
124   return false;
125 }
126
127 #define GET_INSTRINFO_MC_DESC
128 #include "ARMGenInstrInfo.inc"
129
130 #define GET_SUBTARGETINFO_MC_DESC
131 #include "ARMGenSubtargetInfo.inc"
132
133
134 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
135   Triple triple(TT);
136
137   bool isThumb = triple.getArch() == Triple::thumb ||
138                  triple.getArch() == Triple::thumbeb;
139
140   bool NoCPU = CPU == "generic" || CPU.empty();
141   std::string ARMArchFeature;
142   switch (triple.getSubArch()) {
143   default:
144     llvm_unreachable("invalid sub-architecture for ARM");
145   case Triple::ARMSubArch_v8:
146     if (NoCPU)
147       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
148       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
149       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
150       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
151                        "+trustzone,+t2xtpk,+crypto,+crc";
152     else
153       // Use CPU to figure out the exact features
154       ARMArchFeature = "+v8";
155     break;
156   case Triple::ARMSubArch_v7m:
157     isThumb = true;
158     if (NoCPU)
159       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
160       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
161     else
162       // Use CPU to figure out the exact features.
163       ARMArchFeature = "+v7";
164     break;
165   case Triple::ARMSubArch_v7em:
166     if (NoCPU)
167       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
168       //       FeatureT2XtPk, FeatureMClass
169       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
170     else
171       // Use CPU to figure out the exact features.
172       ARMArchFeature = "+v7";
173     break;
174   case Triple::ARMSubArch_v7s:
175     if (NoCPU)
176       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
177       //      Swift
178       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
179     else
180       // Use CPU to figure out the exact features.
181       ARMArchFeature = "+v7";
182     break;
183   case Triple::ARMSubArch_v7:
184     // v7 CPUs have lots of different feature sets. If no CPU is specified,
185     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
186     // the "minimum" feature set and use CPU string to figure out the exact
187     // features.
188     if (NoCPU)
189       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
190       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
191     else
192       // Use CPU to figure out the exact features.
193       ARMArchFeature = "+v7";
194     break;
195   case Triple::ARMSubArch_v6t2:
196     ARMArchFeature = "+v6t2";
197     break;
198   case Triple::ARMSubArch_v6m:
199     isThumb = true;
200     if (NoCPU)
201       // v6m: FeatureNoARM, FeatureMClass
202       ARMArchFeature = "+v6m,+noarm,+mclass";
203     else
204       ARMArchFeature = "+v6";
205     break;
206   case Triple::ARMSubArch_v6:
207     ARMArchFeature = "+v6";
208     break;
209   case Triple::ARMSubArch_v5te:
210     ARMArchFeature = "+v5te";
211     break;
212   case Triple::ARMSubArch_v5:
213     ARMArchFeature = "+v5t";
214     break;
215   case Triple::ARMSubArch_v4t:
216     ARMArchFeature = "+v4t";
217     break;
218   case Triple::NoSubArch:
219     break;
220   }
221
222   if (isThumb) {
223     if (ARMArchFeature.empty())
224       ARMArchFeature = "+thumb-mode";
225     else
226       ARMArchFeature += ",+thumb-mode";
227   }
228
229   if (triple.isOSNaCl()) {
230     if (ARMArchFeature.empty())
231       ARMArchFeature = "+nacl-trap";
232     else
233       ARMArchFeature += ",+nacl-trap";
234   }
235
236   return ARMArchFeature;
237 }
238
239 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
240                                                   StringRef FS) {
241   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
242   if (!FS.empty()) {
243     if (!ArchFS.empty())
244       ArchFS = ArchFS + "," + FS.str();
245     else
246       ArchFS = FS;
247   }
248
249   MCSubtargetInfo *X = new MCSubtargetInfo();
250   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
251   return X;
252 }
253
254 static MCInstrInfo *createARMMCInstrInfo() {
255   MCInstrInfo *X = new MCInstrInfo();
256   InitARMMCInstrInfo(X);
257   return X;
258 }
259
260 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
261   MCRegisterInfo *X = new MCRegisterInfo();
262   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
263   return X;
264 }
265
266 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
267   Triple TheTriple(TT);
268
269   MCAsmInfo *MAI;
270   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
271     MAI = new ARMMCAsmInfoDarwin(TT);
272   else if (TheTriple.isWindowsItaniumEnvironment())
273     MAI = new ARMCOFFMCAsmInfoGNU();
274   else if (TheTriple.isWindowsMSVCEnvironment())
275     MAI = new ARMCOFFMCAsmInfoMicrosoft();
276   else
277     MAI = new ARMELFMCAsmInfo(TT);
278
279   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
280   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
281
282   return MAI;
283 }
284
285 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
286                                              CodeModel::Model CM,
287                                              CodeGenOpt::Level OL) {
288   MCCodeGenInfo *X = new MCCodeGenInfo();
289   if (RM == Reloc::Default) {
290     Triple TheTriple(TT);
291     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
292     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
293   }
294   X->InitMCCodeGenInfo(RM, CM, OL);
295   return X;
296 }
297
298 // This is duplicated code. Refactor this.
299 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
300                                     MCContext &Ctx, MCAsmBackend &MAB,
301                                     raw_ostream &OS, MCCodeEmitter *Emitter,
302                                     const MCSubtargetInfo &STI, bool RelaxAll) {
303   Triple TheTriple(TT);
304
305   switch (TheTriple.getObjectFormat()) {
306   default: llvm_unreachable("unsupported object format");
307   case Triple::MachO: {
308     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
309     new ARMTargetStreamer(*S);
310     return S;
311   }
312   case Triple::COFF:
313     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
314     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
315   case Triple::ELF:
316     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
317                                 TheTriple.getArch() == Triple::thumb);
318   }
319 }
320
321 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
322                                              unsigned SyntaxVariant,
323                                              const MCAsmInfo &MAI,
324                                              const MCInstrInfo &MII,
325                                              const MCRegisterInfo &MRI,
326                                              const MCSubtargetInfo &STI) {
327   if (SyntaxVariant == 0)
328     return new ARMInstPrinter(MAI, MII, MRI, STI);
329   return nullptr;
330 }
331
332 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
333                                                    MCContext &Ctx) {
334   Triple TheTriple(TT);
335   if (TheTriple.isOSBinFormatMachO())
336     return createARMMachORelocationInfo(Ctx);
337   // Default to the stock relocation info.
338   return llvm::createMCRelocationInfo(TT, Ctx);
339 }
340
341 namespace {
342
343 class ARMMCInstrAnalysis : public MCInstrAnalysis {
344 public:
345   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
346
347   bool isUnconditionalBranch(const MCInst &Inst) const override {
348     // BCCs with the "always" predicate are unconditional branches.
349     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
350       return true;
351     return MCInstrAnalysis::isUnconditionalBranch(Inst);
352   }
353
354   bool isConditionalBranch(const MCInst &Inst) const override {
355     // BCCs with the "always" predicate are unconditional branches.
356     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
357       return false;
358     return MCInstrAnalysis::isConditionalBranch(Inst);
359   }
360
361   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
362                       uint64_t Size, uint64_t &Target) const override {
363     // We only handle PCRel branches for now.
364     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
365       return false;
366
367     int64_t Imm = Inst.getOperand(0).getImm();
368     // FIXME: This is not right for thumb.
369     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
370     return true;
371   }
372 };
373
374 }
375
376 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
377   return new ARMMCInstrAnalysis(Info);
378 }
379
380 // Force static initialization.
381 extern "C" void LLVMInitializeARMTargetMC() {
382   // Register the MC asm info.
383   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
384   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
385   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
386   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
387
388   // Register the MC codegen info.
389   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
390   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
391   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
392                                         createARMMCCodeGenInfo);
393   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
394                                         createARMMCCodeGenInfo);
395
396   // Register the MC instruction info.
397   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
398   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
399   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
400   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
401
402   // Register the MC register info.
403   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
404   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
405   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
406   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
407
408   // Register the MC subtarget info.
409   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
410                                           ARM_MC::createARMMCSubtargetInfo);
411   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
412                                           ARM_MC::createARMMCSubtargetInfo);
413   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
414                                           ARM_MC::createARMMCSubtargetInfo);
415   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
416                                           ARM_MC::createARMMCSubtargetInfo);
417
418   // Register the MC instruction analyzer.
419   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
420                                           createARMMCInstrAnalysis);
421   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
422                                           createARMMCInstrAnalysis);
423   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
424                                           createARMMCInstrAnalysis);
425   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
426                                           createARMMCInstrAnalysis);
427
428   // Register the MC Code Emitter
429   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
430                                         createARMLEMCCodeEmitter);
431   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
432                                         createARMBEMCCodeEmitter);
433   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
434                                         createARMLEMCCodeEmitter);
435   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
436                                         createARMBEMCCodeEmitter);
437
438   // Register the asm backend.
439   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
440   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
441   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
442                                        createThumbLEAsmBackend);
443   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
444                                        createThumbBEAsmBackend);
445
446   // Register the object streamer.
447   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
448   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
449   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
450   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
451
452   // Register the asm streamer.
453   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
454   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
455   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
456   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
457
458   // Register the null TargetStreamer.
459   TargetRegistry::RegisterNullTargetStreamer(TheARMLETarget,
460                                              createARMNullTargetStreamer);
461   TargetRegistry::RegisterNullTargetStreamer(TheARMBETarget,
462                                              createARMNullTargetStreamer);
463   TargetRegistry::RegisterNullTargetStreamer(TheThumbLETarget,
464                                              createARMNullTargetStreamer);
465   TargetRegistry::RegisterNullTargetStreamer(TheThumbBETarget,
466                                              createARMNullTargetStreamer);
467
468   // Register the MCInstPrinter.
469   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
470   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
471   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
472                                         createARMMCInstPrinter);
473   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
474                                         createARMMCInstPrinter);
475
476   // Register the MC relocation info.
477   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
478                                            createARMMCRelocationInfo);
479   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
480                                            createARMMCRelocationInfo);
481   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
482                                            createARMMCRelocationInfo);
483   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
484                                            createARMMCRelocationInfo);
485 }