1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "asm-printer"
27 #include "ARMGenAsmWriter.inc"
29 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
31 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
32 static unsigned translateShiftImm(unsigned imm) {
33 // lsr #32 and asr #32 exist, but should be encoded as a 0.
34 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
41 /// Prints the shift value with an immediate value.
42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43 unsigned ShImm, bool UseMarkup) {
44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
48 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
49 O << getShiftOpcStr(ShOpc);
51 if (ShOpc != ARM_AM::rrx) {
55 O << "#" << translateShiftImm(ShImm);
61 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI)
63 : MCInstPrinter(MAI, MII, MRI) {}
65 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
66 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
70 StringRef Annot, const MCSubtargetInfo &STI) {
71 unsigned Opcode = MI->getOpcode();
75 // Check for HINT instructions w/ canonical names.
79 switch (MI->getOperand(0).getImm()) {
96 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
99 } // Fallthrough for non-v8
101 // Anything else should just print normally.
102 printInstruction(MI, STI, O);
103 printAnnotation(O, Annot);
106 printPredicateOperand(MI, 1, STI, O);
107 if (Opcode == ARM::t2HINT)
109 printAnnotation(O, Annot);
112 // Check for MOVs and print canonical forms, instead.
114 // FIXME: Thumb variants?
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
118 const MCOperand &MO3 = MI->getOperand(3);
120 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
121 printSBitModifierOperand(MI, 6, STI, O);
122 printPredicateOperand(MI, 4, STI, O);
125 printRegName(O, Dst.getReg());
127 printRegName(O, MO1.getReg());
130 printRegName(O, MO2.getReg());
131 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
132 printAnnotation(O, Annot);
137 // FIXME: Thumb variants?
138 const MCOperand &Dst = MI->getOperand(0);
139 const MCOperand &MO1 = MI->getOperand(1);
140 const MCOperand &MO2 = MI->getOperand(2);
142 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
143 printSBitModifierOperand(MI, 5, STI, O);
144 printPredicateOperand(MI, 3, STI, O);
147 printRegName(O, Dst.getReg());
149 printRegName(O, MO1.getReg());
151 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
152 printAnnotation(O, Annot);
156 O << ", " << markup("<imm:") << "#"
157 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
158 printAnnotation(O, Annot);
164 case ARM::t2STMDB_UPD:
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
166 // Should only print PUSH if there are at least two registers in the list.
168 printPredicateOperand(MI, 2, STI, O);
169 if (Opcode == ARM::t2STMDB_UPD)
172 printRegisterList(MI, 4, STI, O);
173 printAnnotation(O, Annot);
178 case ARM::STR_PRE_IMM:
179 if (MI->getOperand(2).getReg() == ARM::SP &&
180 MI->getOperand(3).getImm() == -4) {
182 printPredicateOperand(MI, 4, STI, O);
184 printRegName(O, MI->getOperand(1).getReg());
186 printAnnotation(O, Annot);
193 case ARM::t2LDMIA_UPD:
194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
195 // Should only print POP if there are at least two registers in the list.
197 printPredicateOperand(MI, 2, STI, O);
198 if (Opcode == ARM::t2LDMIA_UPD)
201 printRegisterList(MI, 4, STI, O);
202 printAnnotation(O, Annot);
207 case ARM::LDR_POST_IMM:
208 if (MI->getOperand(2).getReg() == ARM::SP &&
209 MI->getOperand(4).getImm() == 4) {
211 printPredicateOperand(MI, 5, STI, O);
213 printRegName(O, MI->getOperand(0).getReg());
215 printAnnotation(O, Annot);
221 case ARM::VSTMSDB_UPD:
222 case ARM::VSTMDDB_UPD:
223 if (MI->getOperand(0).getReg() == ARM::SP) {
224 O << '\t' << "vpush";
225 printPredicateOperand(MI, 2, STI, O);
227 printRegisterList(MI, 4, STI, O);
228 printAnnotation(O, Annot);
234 case ARM::VLDMSIA_UPD:
235 case ARM::VLDMDIA_UPD:
236 if (MI->getOperand(0).getReg() == ARM::SP) {
238 printPredicateOperand(MI, 2, STI, O);
240 printRegisterList(MI, 4, STI, O);
241 printAnnotation(O, Annot);
247 bool Writeback = true;
248 unsigned BaseReg = MI->getOperand(0).getReg();
249 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
250 if (MI->getOperand(i).getReg() == BaseReg)
256 printPredicateOperand(MI, 1, STI, O);
258 printRegName(O, BaseReg);
262 printRegisterList(MI, 3, STI, O);
263 printAnnotation(O, Annot);
267 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
268 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
269 // a single GPRPair reg operand is used in the .td file to replace the two
270 // GPRs. However, when decoding them, the two GRPs cannot be automatically
271 // expressed as a GPRPair, so we have to manually merge them.
272 // FIXME: We would really like to be able to tablegen'erate this.
277 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
278 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
279 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
280 if (MRC.contains(Reg)) {
283 NewMI.setOpcode(Opcode);
286 NewMI.addOperand(MI->getOperand(0));
287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
288 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
289 NewMI.addOperand(NewReg);
291 // Copy the rest operands into NewMI.
292 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
293 NewMI.addOperand(MI->getOperand(i));
294 printInstruction(&NewMI, STI, O);
299 // B9.3.3 ERET (Thumb)
300 // For a target that has Virtualization Extensions, ERET is the preferred
301 // disassembly of SUBS PC, LR, #0
302 case ARM::t2SUBS_PC_LR: {
303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304 MI->getOperand(0).getImm() == 0 &&
305 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
307 printPredicateOperand(MI, 1, STI, O);
308 printAnnotation(O, Annot);
315 printInstruction(MI, STI, O);
316 printAnnotation(O, Annot);
319 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
320 const MCSubtargetInfo &STI, raw_ostream &O) {
321 const MCOperand &Op = MI->getOperand(OpNo);
323 unsigned Reg = Op.getReg();
324 printRegName(O, Reg);
325 } else if (Op.isImm()) {
326 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
328 assert(Op.isExpr() && "unknown operand kind in printOperand");
329 const MCExpr *Expr = Op.getExpr();
330 switch (Expr->getKind()) {
333 Expr->print(O, &MAI);
335 case MCExpr::Constant: {
336 // If a symbolic branch target was added as a constant expression then
337 // print that address in hex. And only print 32 unsigned bits for the
339 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
340 int64_t TargetAddress;
341 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
343 Expr->print(O, &MAI);
346 O.write_hex(static_cast<uint32_t>(TargetAddress));
351 // FIXME: Should we always treat this as if it is a constant literal and
352 // prefix it with '#'?
353 Expr->print(O, &MAI);
359 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
360 const MCSubtargetInfo &STI,
362 const MCOperand &MO1 = MI->getOperand(OpNum);
364 MO1.getExpr()->print(O, &MAI);
368 O << markup("<mem:") << "[pc, ";
370 int32_t OffImm = (int32_t)MO1.getImm();
371 bool isSub = OffImm < 0;
373 // Special value for #-0. All others are normal.
374 if (OffImm == INT32_MIN)
377 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
379 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
381 O << "]" << markup(">");
384 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
385 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
387 // REG REG 0,SH_OPC - e.g. R5, ROR R3
388 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
389 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
390 const MCSubtargetInfo &STI,
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
394 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
396 printRegName(O, MO1.getReg());
398 // Print the shift opc.
399 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
400 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
401 if (ShOpc == ARM_AM::rrx)
405 printRegName(O, MO2.getReg());
406 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
409 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
410 const MCSubtargetInfo &STI,
412 const MCOperand &MO1 = MI->getOperand(OpNum);
413 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
415 printRegName(O, MO1.getReg());
417 // Print the shift opc.
418 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
419 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
422 //===--------------------------------------------------------------------===//
423 // Addressing Mode #2
424 //===--------------------------------------------------------------------===//
426 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
427 const MCSubtargetInfo &STI,
429 const MCOperand &MO1 = MI->getOperand(Op);
430 const MCOperand &MO2 = MI->getOperand(Op + 1);
431 const MCOperand &MO3 = MI->getOperand(Op + 2);
433 O << markup("<mem:") << "[";
434 printRegName(O, MO1.getReg());
437 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
438 O << ", " << markup("<imm:") << "#"
439 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
440 << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
442 O << "]" << markup(">");
447 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
448 printRegName(O, MO2.getReg());
450 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
451 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
452 O << "]" << markup(">");
455 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
456 const MCSubtargetInfo &STI,
458 const MCOperand &MO1 = MI->getOperand(Op);
459 const MCOperand &MO2 = MI->getOperand(Op + 1);
460 O << markup("<mem:") << "[";
461 printRegName(O, MO1.getReg());
463 printRegName(O, MO2.getReg());
464 O << "]" << markup(">");
467 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
468 const MCSubtargetInfo &STI,
470 const MCOperand &MO1 = MI->getOperand(Op);
471 const MCOperand &MO2 = MI->getOperand(Op + 1);
472 O << markup("<mem:") << "[";
473 printRegName(O, MO1.getReg());
475 printRegName(O, MO2.getReg());
476 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
479 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
480 const MCSubtargetInfo &STI,
482 const MCOperand &MO1 = MI->getOperand(Op);
484 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
485 printOperand(MI, Op, STI, O);
490 const MCOperand &MO3 = MI->getOperand(Op + 2);
491 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
492 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
495 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
498 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
500 const MCSubtargetInfo &STI,
502 const MCOperand &MO1 = MI->getOperand(OpNum);
503 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
506 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
507 O << markup("<imm:") << '#'
508 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
513 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
514 printRegName(O, MO1.getReg());
516 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
517 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
520 //===--------------------------------------------------------------------===//
521 // Addressing Mode #3
522 //===--------------------------------------------------------------------===//
524 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
526 bool AlwaysPrintImm0) {
527 const MCOperand &MO1 = MI->getOperand(Op);
528 const MCOperand &MO2 = MI->getOperand(Op + 1);
529 const MCOperand &MO3 = MI->getOperand(Op + 2);
531 O << markup("<mem:") << '[';
532 printRegName(O, MO1.getReg());
535 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
536 printRegName(O, MO2.getReg());
537 O << ']' << markup(">");
541 // If the op is sub we have to print the immediate even if it is 0
542 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
543 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
545 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
546 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
549 O << ']' << markup(">");
552 template <bool AlwaysPrintImm0>
553 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
554 const MCSubtargetInfo &STI,
556 const MCOperand &MO1 = MI->getOperand(Op);
557 if (!MO1.isReg()) { // For label symbolic references.
558 printOperand(MI, Op, STI, O);
562 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
563 ARMII::IndexModePost &&
564 "unexpected idxmode");
565 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
568 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
570 const MCSubtargetInfo &STI,
572 const MCOperand &MO1 = MI->getOperand(OpNum);
573 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
576 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
577 printRegName(O, MO1.getReg());
581 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
582 O << markup("<imm:") << '#'
583 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
587 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
588 const MCSubtargetInfo &STI,
590 const MCOperand &MO = MI->getOperand(OpNum);
591 unsigned Imm = MO.getImm();
592 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
596 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
597 const MCSubtargetInfo &STI,
599 const MCOperand &MO1 = MI->getOperand(OpNum);
600 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
602 O << (MO2.getImm() ? "" : "-");
603 printRegName(O, MO1.getReg());
606 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
607 const MCSubtargetInfo &STI,
609 const MCOperand &MO = MI->getOperand(OpNum);
610 unsigned Imm = MO.getImm();
611 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
615 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
616 const MCSubtargetInfo &STI,
618 ARM_AM::AMSubMode Mode =
619 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
620 O << ARM_AM::getAMSubModeStr(Mode);
623 template <bool AlwaysPrintImm0>
624 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
625 const MCSubtargetInfo &STI,
627 const MCOperand &MO1 = MI->getOperand(OpNum);
628 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
630 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
631 printOperand(MI, OpNum, STI, O);
635 O << markup("<mem:") << "[";
636 printRegName(O, MO1.getReg());
638 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
639 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
640 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
641 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
642 << ImmOffs * 4 << markup(">");
644 O << "]" << markup(">");
647 template <bool AlwaysPrintImm0>
648 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
649 const MCSubtargetInfo &STI,
651 const MCOperand &MO1 = MI->getOperand(OpNum);
652 const MCOperand &MO2 = MI->getOperand(OpNum+1);
654 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
655 printOperand(MI, OpNum, STI, O);
659 O << markup("<mem:") << "[";
660 printRegName(O, MO1.getReg());
662 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
663 unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
664 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
668 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5FP16Op(MO2.getImm()))
672 O << "]" << markup(">");
675 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
676 const MCSubtargetInfo &STI,
678 const MCOperand &MO1 = MI->getOperand(OpNum);
679 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
681 O << markup("<mem:") << "[";
682 printRegName(O, MO1.getReg());
684 O << ":" << (MO2.getImm() << 3);
686 O << "]" << markup(">");
689 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
690 const MCSubtargetInfo &STI,
692 const MCOperand &MO1 = MI->getOperand(OpNum);
693 O << markup("<mem:") << "[";
694 printRegName(O, MO1.getReg());
695 O << "]" << markup(">");
698 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
700 const MCSubtargetInfo &STI,
702 const MCOperand &MO = MI->getOperand(OpNum);
703 if (MO.getReg() == 0)
707 printRegName(O, MO.getReg());
711 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
713 const MCSubtargetInfo &STI,
715 const MCOperand &MO = MI->getOperand(OpNum);
716 uint32_t v = ~MO.getImm();
717 int32_t lsb = countTrailingZeros(v);
718 int32_t width = (32 - countLeadingZeros(v)) - lsb;
719 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
720 O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
721 << '#' << width << markup(">");
724 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
725 const MCSubtargetInfo &STI,
727 unsigned val = MI->getOperand(OpNum).getImm();
728 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
731 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
732 const MCSubtargetInfo &STI,
734 unsigned val = MI->getOperand(OpNum).getImm();
735 O << ARM_ISB::InstSyncBOptToString(val);
738 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
739 const MCSubtargetInfo &STI,
741 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
742 bool isASR = (ShiftOp & (1 << 5)) != 0;
743 unsigned Amt = ShiftOp & 0x1f;
745 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
748 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
752 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
753 const MCSubtargetInfo &STI,
755 unsigned Imm = MI->getOperand(OpNum).getImm();
758 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
759 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
762 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
763 const MCSubtargetInfo &STI,
765 unsigned Imm = MI->getOperand(OpNum).getImm();
766 // A shift amount of 32 is encoded as 0.
769 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
770 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
773 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
774 const MCSubtargetInfo &STI,
777 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
780 printRegName(O, MI->getOperand(i).getReg());
785 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
786 const MCSubtargetInfo &STI,
788 unsigned Reg = MI->getOperand(OpNum).getReg();
789 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
791 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
794 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
795 const MCSubtargetInfo &STI,
797 const MCOperand &Op = MI->getOperand(OpNum);
804 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
805 const MCSubtargetInfo &STI, raw_ostream &O) {
806 const MCOperand &Op = MI->getOperand(OpNum);
807 O << ARM_PROC::IModToString(Op.getImm());
810 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
811 const MCSubtargetInfo &STI, raw_ostream &O) {
812 const MCOperand &Op = MI->getOperand(OpNum);
813 unsigned IFlags = Op.getImm();
814 for (int i = 2; i >= 0; --i)
815 if (IFlags & (1 << i))
816 O << ARM_PROC::IFlagsToString(1 << i);
822 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
823 const MCSubtargetInfo &STI,
825 const MCOperand &Op = MI->getOperand(OpNum);
826 unsigned SpecRegRBit = Op.getImm() >> 4;
827 unsigned Mask = Op.getImm() & 0xf;
828 const FeatureBitset &FeatureBits = STI.getFeatureBits();
830 if (FeatureBits[ARM::FeatureMClass]) {
831 unsigned SYSm = Op.getImm();
832 unsigned Opcode = MI->getOpcode();
834 // For writes, handle extended mask bits if the DSP extension is present.
835 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
864 // Handle the basic 8-bit mask.
867 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
868 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
869 // alias for MSR APSR_nzcvq.
888 llvm_unreachable("Unexpected mask value!");
934 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
935 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
936 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
940 llvm_unreachable("Unexpected mask value!");
971 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
972 const MCSubtargetInfo &STI,
974 uint32_t Banked = MI->getOperand(OpNum).getImm();
975 uint32_t R = (Banked & 0x20) >> 5;
976 uint32_t SysM = Banked & 0x1f;
978 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
979 // the ARM ARM v7C, and are all over the shop.
1006 llvm_unreachable("Invalid banked SPSR register");
1010 assert(!R && "should have dealt with SPSR regs");
1011 const char *RegNames[] = {
1012 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
1013 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
1014 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
1015 "sp_abt", "lr_und", "sp_und", "", "", "", "",
1016 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
1017 const char *Name = RegNames[SysM];
1018 assert(Name[0] && "invalid banked register operand");
1023 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
1024 const MCSubtargetInfo &STI,
1026 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1027 // Handle the undefined 15 CC value here for printing so we don't abort().
1028 if ((unsigned)CC == 15)
1030 else if (CC != ARMCC::AL)
1031 O << ARMCondCodeToString(CC);
1034 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1036 const MCSubtargetInfo &STI,
1038 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1039 O << ARMCondCodeToString(CC);
1042 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1043 const MCSubtargetInfo &STI,
1045 if (MI->getOperand(OpNum).getReg()) {
1046 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1047 "Expect ARM CPSR register!");
1052 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1053 const MCSubtargetInfo &STI,
1055 O << MI->getOperand(OpNum).getImm();
1058 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1059 const MCSubtargetInfo &STI,
1061 O << "p" << MI->getOperand(OpNum).getImm();
1064 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1065 const MCSubtargetInfo &STI,
1067 O << "c" << MI->getOperand(OpNum).getImm();
1070 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1071 const MCSubtargetInfo &STI,
1073 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1076 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1077 const MCSubtargetInfo &STI, raw_ostream &O) {
1078 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1081 template <unsigned scale>
1082 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1083 const MCSubtargetInfo &STI,
1085 const MCOperand &MO = MI->getOperand(OpNum);
1088 MO.getExpr()->print(O, &MAI);
1092 int32_t OffImm = (int32_t)MO.getImm() << scale;
1094 O << markup("<imm:");
1095 if (OffImm == INT32_MIN)
1097 else if (OffImm < 0)
1098 O << "#-" << -OffImm;
1104 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1105 const MCSubtargetInfo &STI,
1107 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1111 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1112 const MCSubtargetInfo &STI,
1114 unsigned Imm = MI->getOperand(OpNum).getImm();
1115 O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1119 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1120 const MCSubtargetInfo &STI,
1122 // (3 - the number of trailing zeros) is the number of then / else.
1123 unsigned Mask = MI->getOperand(OpNum).getImm();
1124 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1125 unsigned CondBit0 = Firstcond & 1;
1126 unsigned NumTZ = countTrailingZeros(Mask);
1127 assert(NumTZ <= 3 && "Invalid IT mask!");
1128 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1129 bool T = ((Mask >> Pos) & 1) == CondBit0;
1137 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1138 const MCSubtargetInfo &STI,
1140 const MCOperand &MO1 = MI->getOperand(Op);
1141 const MCOperand &MO2 = MI->getOperand(Op + 1);
1143 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1144 printOperand(MI, Op, STI, O);
1148 O << markup("<mem:") << "[";
1149 printRegName(O, MO1.getReg());
1150 if (unsigned RegNum = MO2.getReg()) {
1152 printRegName(O, RegNum);
1154 O << "]" << markup(">");
1157 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1159 const MCSubtargetInfo &STI,
1162 const MCOperand &MO1 = MI->getOperand(Op);
1163 const MCOperand &MO2 = MI->getOperand(Op + 1);
1165 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1166 printOperand(MI, Op, STI, O);
1170 O << markup("<mem:") << "[";
1171 printRegName(O, MO1.getReg());
1172 if (unsigned ImmOffs = MO2.getImm()) {
1173 O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1176 O << "]" << markup(">");
1179 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1181 const MCSubtargetInfo &STI,
1183 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1186 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1188 const MCSubtargetInfo &STI,
1190 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1193 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1195 const MCSubtargetInfo &STI,
1197 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1200 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1201 const MCSubtargetInfo &STI,
1203 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1206 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1207 // register with shift forms.
1208 // REG 0 0 - e.g. R5
1209 // REG IMM, SH_OPC - e.g. R5, LSL #3
1210 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1211 const MCSubtargetInfo &STI,
1213 const MCOperand &MO1 = MI->getOperand(OpNum);
1214 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1216 unsigned Reg = MO1.getReg();
1217 printRegName(O, Reg);
1219 // Print the shift opc.
1220 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1221 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1222 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1225 template <bool AlwaysPrintImm0>
1226 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1227 const MCSubtargetInfo &STI,
1229 const MCOperand &MO1 = MI->getOperand(OpNum);
1230 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1232 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1233 printOperand(MI, OpNum, STI, O);
1237 O << markup("<mem:") << "[";
1238 printRegName(O, MO1.getReg());
1240 int32_t OffImm = (int32_t)MO2.getImm();
1241 bool isSub = OffImm < 0;
1242 // Special value for #-0. All others are normal.
1243 if (OffImm == INT32_MIN)
1246 O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1247 } else if (AlwaysPrintImm0 || OffImm > 0) {
1248 O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1250 O << "]" << markup(">");
1253 template <bool AlwaysPrintImm0>
1254 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1256 const MCSubtargetInfo &STI,
1258 const MCOperand &MO1 = MI->getOperand(OpNum);
1259 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1261 O << markup("<mem:") << "[";
1262 printRegName(O, MO1.getReg());
1264 int32_t OffImm = (int32_t)MO2.getImm();
1265 bool isSub = OffImm < 0;
1267 if (OffImm == INT32_MIN)
1270 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1271 } else if (AlwaysPrintImm0 || OffImm > 0) {
1272 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1274 O << "]" << markup(">");
1277 template <bool AlwaysPrintImm0>
1278 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1280 const MCSubtargetInfo &STI,
1282 const MCOperand &MO1 = MI->getOperand(OpNum);
1283 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1285 if (!MO1.isReg()) { // For label symbolic references.
1286 printOperand(MI, OpNum, STI, O);
1290 O << markup("<mem:") << "[";
1291 printRegName(O, MO1.getReg());
1293 int32_t OffImm = (int32_t)MO2.getImm();
1294 bool isSub = OffImm < 0;
1296 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1299 if (OffImm == INT32_MIN)
1302 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1303 } else if (AlwaysPrintImm0 || OffImm > 0) {
1304 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1306 O << "]" << markup(">");
1309 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1310 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1312 const MCOperand &MO1 = MI->getOperand(OpNum);
1313 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1315 O << markup("<mem:") << "[";
1316 printRegName(O, MO1.getReg());
1318 O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1321 O << "]" << markup(">");
1324 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1325 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1327 const MCOperand &MO1 = MI->getOperand(OpNum);
1328 int32_t OffImm = (int32_t)MO1.getImm();
1329 O << ", " << markup("<imm:");
1330 if (OffImm == INT32_MIN)
1332 else if (OffImm < 0)
1333 O << "#-" << -OffImm;
1339 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1340 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1342 const MCOperand &MO1 = MI->getOperand(OpNum);
1343 int32_t OffImm = (int32_t)MO1.getImm();
1345 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1347 O << ", " << markup("<imm:");
1348 if (OffImm == INT32_MIN)
1350 else if (OffImm < 0)
1351 O << "#-" << -OffImm;
1357 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1359 const MCSubtargetInfo &STI,
1361 const MCOperand &MO1 = MI->getOperand(OpNum);
1362 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1363 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1365 O << markup("<mem:") << "[";
1366 printRegName(O, MO1.getReg());
1368 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1370 printRegName(O, MO2.getReg());
1372 unsigned ShAmt = MO3.getImm();
1374 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1375 O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1377 O << "]" << markup(">");
1380 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1381 const MCSubtargetInfo &STI,
1383 const MCOperand &MO = MI->getOperand(OpNum);
1384 O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1388 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1389 const MCSubtargetInfo &STI,
1391 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1393 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1394 O << markup("<imm:") << "#0x";
1399 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1400 const MCSubtargetInfo &STI,
1402 unsigned Imm = MI->getOperand(OpNum).getImm();
1403 O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1406 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1407 const MCSubtargetInfo &STI,
1409 unsigned Imm = MI->getOperand(OpNum).getImm();
1412 assert(Imm <= 3 && "illegal ror immediate!");
1413 O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1416 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1417 const MCSubtargetInfo &STI,
1419 MCOperand Op = MI->getOperand(OpNum);
1421 // Support for fixups (MCFixup)
1423 return printOperand(MI, OpNum, STI, O);
1425 unsigned Bits = Op.getImm() & 0xFF;
1426 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1428 bool PrintUnsigned = false;
1429 switch (MI->getOpcode()) {
1431 // Movs to PC should be treated unsigned
1432 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1435 // Movs to special registers should be treated unsigned
1436 PrintUnsigned = true;
1440 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1441 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1442 // #rot has the least possible value
1443 O << "#" << markup("<imm:");
1445 O << static_cast<uint32_t>(Rotated);
1452 // Explicit #bits, #rot implied
1453 O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1454 << Rot << markup(">");
1457 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1458 const MCSubtargetInfo &STI, raw_ostream &O) {
1459 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1463 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1464 const MCSubtargetInfo &STI, raw_ostream &O) {
1465 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1469 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1470 const MCSubtargetInfo &STI,
1472 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1475 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1476 const MCSubtargetInfo &STI,
1479 printRegName(O, MI->getOperand(OpNum).getReg());
1483 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1484 const MCSubtargetInfo &STI,
1486 unsigned Reg = MI->getOperand(OpNum).getReg();
1487 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1488 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1490 printRegName(O, Reg0);
1492 printRegName(O, Reg1);
1496 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1497 const MCSubtargetInfo &STI,
1499 unsigned Reg = MI->getOperand(OpNum).getReg();
1500 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1501 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1503 printRegName(O, Reg0);
1505 printRegName(O, Reg1);
1509 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1510 const MCSubtargetInfo &STI,
1512 // Normally, it's not safe to use register enum values directly with
1513 // addition to get the next register, but for VFP registers, the
1514 // sort order is guaranteed because they're all of the form D<n>.
1516 printRegName(O, MI->getOperand(OpNum).getReg());
1518 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1520 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1524 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1525 const MCSubtargetInfo &STI,
1527 // Normally, it's not safe to use register enum values directly with
1528 // addition to get the next register, but for VFP registers, the
1529 // sort order is guaranteed because they're all of the form D<n>.
1531 printRegName(O, MI->getOperand(OpNum).getReg());
1533 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1535 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1537 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1541 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1543 const MCSubtargetInfo &STI,
1546 printRegName(O, MI->getOperand(OpNum).getReg());
1550 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1552 const MCSubtargetInfo &STI,
1554 unsigned Reg = MI->getOperand(OpNum).getReg();
1555 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1556 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1558 printRegName(O, Reg0);
1560 printRegName(O, Reg1);
1564 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1566 const MCSubtargetInfo &STI,
1568 // Normally, it's not safe to use register enum values directly with
1569 // addition to get the next register, but for VFP registers, the
1570 // sort order is guaranteed because they're all of the form D<n>.
1572 printRegName(O, MI->getOperand(OpNum).getReg());
1574 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1576 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1580 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1582 const MCSubtargetInfo &STI,
1584 // Normally, it's not safe to use register enum values directly with
1585 // addition to get the next register, but for VFP registers, the
1586 // sort order is guaranteed because they're all of the form D<n>.
1588 printRegName(O, MI->getOperand(OpNum).getReg());
1590 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1592 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1594 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1598 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1599 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1601 unsigned Reg = MI->getOperand(OpNum).getReg();
1602 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1603 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1605 printRegName(O, Reg0);
1607 printRegName(O, Reg1);
1611 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1612 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1614 // Normally, it's not safe to use register enum values directly with
1615 // addition to get the next register, but for VFP registers, the
1616 // sort order is guaranteed because they're all of the form D<n>.
1618 printRegName(O, MI->getOperand(OpNum).getReg());
1620 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1622 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1626 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1627 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1629 // Normally, it's not safe to use register enum values directly with
1630 // addition to get the next register, but for VFP registers, the
1631 // sort order is guaranteed because they're all of the form D<n>.
1633 printRegName(O, MI->getOperand(OpNum).getReg());
1635 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1637 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1639 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1643 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1645 const MCSubtargetInfo &STI,
1647 // Normally, it's not safe to use register enum values directly with
1648 // addition to get the next register, but for VFP registers, the
1649 // sort order is guaranteed because they're all of the form D<n>.
1651 printRegName(O, MI->getOperand(OpNum).getReg());
1653 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1655 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1659 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1660 const MCSubtargetInfo &STI,
1662 // Normally, it's not safe to use register enum values directly with
1663 // addition to get the next register, but for VFP registers, the
1664 // sort order is guaranteed because they're all of the form D<n>.
1666 printRegName(O, MI->getOperand(OpNum).getReg());
1668 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1670 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1672 printRegName(O, MI->getOperand(OpNum).getReg() + 6);