1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Twine.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCObjectFileInfo.h"
29 #include "llvm/MC/MCParser/MCAsmLexer.h"
30 #include "llvm/MC/MCParser/MCAsmParser.h"
31 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCSection.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/MC/MCTargetAsmParser.h"
39 #include "llvm/Support/ARMBuildAttributes.h"
40 #include "llvm/Support/ARMEHABI.h"
41 #include "llvm/Support/TargetParser.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
132 const MCInstrInfo &MII;
133 const MCRegisterInfo *MRI;
136 ARMTargetStreamer &getTargetStreamer() {
137 assert(getParser().getStreamer().getTargetStreamer() &&
138 "do not have a target streamer");
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U; }
168 bool lastInITBlock() {
169 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
171 void forwardITPosition() {
172 if (!inITBlock()) return;
173 // Move to the next instruction in the IT block, if there is one. If not,
174 // mark the block as done.
175 unsigned TZ = countTrailingZeros(ITState.Mask);
176 if (++ITState.CurPosition == 5 - TZ)
177 ITState.CurPosition = ~0U; // Done with the IT block after this.
180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181 return getParser().Note(L, Msg, Ranges);
183 bool Warning(SMLoc L, const Twine &Msg,
184 ArrayRef<SMRange> Ranges = None) {
185 return getParser().Warning(L, Msg, Ranges);
187 bool Error(SMLoc L, const Twine &Msg,
188 ArrayRef<SMRange> Ranges = None) {
189 return getParser().Error(L, Msg, Ranges);
192 bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
193 unsigned ListNo, bool IsARPop = false);
194 bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
197 int tryParseRegister();
198 bool tryParseRegisterWithWriteBack(OperandVector &);
199 int tryParseShiftRegister(OperandVector &);
200 bool parseRegisterList(OperandVector &);
201 bool parseMemory(OperandVector &);
202 bool parseOperand(OperandVector &, StringRef Mnemonic);
203 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
205 unsigned &ShiftAmount);
206 bool parseLiteralValues(unsigned Size, SMLoc L);
207 bool parseDirectiveThumb(SMLoc L);
208 bool parseDirectiveARM(SMLoc L);
209 bool parseDirectiveThumbFunc(SMLoc L);
210 bool parseDirectiveCode(SMLoc L);
211 bool parseDirectiveSyntax(SMLoc L);
212 bool parseDirectiveReq(StringRef Name, SMLoc L);
213 bool parseDirectiveUnreq(SMLoc L);
214 bool parseDirectiveArch(SMLoc L);
215 bool parseDirectiveEabiAttr(SMLoc L);
216 bool parseDirectiveCPU(SMLoc L);
217 bool parseDirectiveFPU(SMLoc L);
218 bool parseDirectiveFnStart(SMLoc L);
219 bool parseDirectiveFnEnd(SMLoc L);
220 bool parseDirectiveCantUnwind(SMLoc L);
221 bool parseDirectivePersonality(SMLoc L);
222 bool parseDirectiveHandlerData(SMLoc L);
223 bool parseDirectiveSetFP(SMLoc L);
224 bool parseDirectivePad(SMLoc L);
225 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
226 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
227 bool parseDirectiveLtorg(SMLoc L);
228 bool parseDirectiveEven(SMLoc L);
229 bool parseDirectivePersonalityIndex(SMLoc L);
230 bool parseDirectiveUnwindRaw(SMLoc L);
231 bool parseDirectiveTLSDescSeq(SMLoc L);
232 bool parseDirectiveMovSP(SMLoc L);
233 bool parseDirectiveObjectArch(SMLoc L);
234 bool parseDirectiveArchExtension(SMLoc L);
235 bool parseDirectiveAlign(SMLoc L);
236 bool parseDirectiveThumbSet(SMLoc L);
238 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
239 bool &CarrySetting, unsigned &ProcessorIMod,
241 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
242 bool &CanAcceptCarrySet,
243 bool &CanAcceptPredicationCode);
245 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
246 OperandVector &Operands);
247 bool isThumb() const {
248 // FIXME: Can tablegen auto-generate this?
249 return STI.getFeatureBits()[ARM::ModeThumb];
251 bool isThumbOne() const {
252 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
254 bool isThumbTwo() const {
255 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
257 bool hasThumb() const {
258 return STI.getFeatureBits()[ARM::HasV4TOps];
260 bool hasV6Ops() const {
261 return STI.getFeatureBits()[ARM::HasV6Ops];
263 bool hasV6MOps() const {
264 return STI.getFeatureBits()[ARM::HasV6MOps];
266 bool hasV7Ops() const {
267 return STI.getFeatureBits()[ARM::HasV7Ops];
269 bool hasV8Ops() const {
270 return STI.getFeatureBits()[ARM::HasV8Ops];
272 bool hasARM() const {
273 return !STI.getFeatureBits()[ARM::FeatureNoARM];
275 bool hasThumb2DSP() const {
276 return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
278 bool hasD16() const {
279 return STI.getFeatureBits()[ARM::FeatureD16];
281 bool hasV8_1aOps() const {
282 return STI.getFeatureBits()[ARM::HasV8_1aOps];
286 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
287 setAvailableFeatures(FB);
289 bool isMClass() const {
290 return STI.getFeatureBits()[ARM::FeatureMClass];
293 /// @name Auto-generated Match Functions
296 #define GET_ASSEMBLER_HEADER
297 #include "ARMGenAsmMatcher.inc"
301 OperandMatchResultTy parseITCondCode(OperandVector &);
302 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
303 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
304 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
305 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
306 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
307 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
308 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
309 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
310 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
312 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
313 return parsePKHImm(O, "lsl", 0, 31);
315 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
316 return parsePKHImm(O, "asr", 1, 32);
318 OperandMatchResultTy parseSetEndImm(OperandVector &);
319 OperandMatchResultTy parseShifterImm(OperandVector &);
320 OperandMatchResultTy parseRotImm(OperandVector &);
321 OperandMatchResultTy parseModImm(OperandVector &);
322 OperandMatchResultTy parseBitfield(OperandVector &);
323 OperandMatchResultTy parsePostIdxReg(OperandVector &);
324 OperandMatchResultTy parseAM3Offset(OperandVector &);
325 OperandMatchResultTy parseFPImm(OperandVector &);
326 OperandMatchResultTy parseVectorList(OperandVector &);
327 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
330 // Asm Match Converter Methods
331 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
332 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
334 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
335 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
336 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
337 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
340 enum ARMMatchResultTy {
341 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
342 Match_RequiresNotITBlock,
344 Match_RequiresThumb2,
345 #define GET_OPERAND_DIAGNOSTIC_TYPES
346 #include "ARMGenAsmMatcher.inc"
350 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
351 const MCInstrInfo &MII, const MCTargetOptions &Options)
352 : STI(STI), MII(MII), UC(Parser) {
353 MCAsmParserExtension::Initialize(Parser);
355 // Cache the MCRegisterInfo.
356 MRI = getContext().getRegisterInfo();
358 // Initialize the set of available features.
359 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
361 // Not in an ITBlock to start with.
362 ITState.CurPosition = ~0U;
364 NextSymbolIsThumb = false;
367 // Implementation of the MCTargetAsmParser interface:
368 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
369 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
370 SMLoc NameLoc, OperandVector &Operands) override;
371 bool ParseDirective(AsmToken DirectiveID) override;
373 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
374 unsigned Kind) override;
375 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
377 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
378 OperandVector &Operands, MCStreamer &Out,
380 bool MatchingInlineAsm) override;
381 void onLabelParsed(MCSymbol *Symbol) override;
383 } // end anonymous namespace
387 /// ARMOperand - Instances of this class represent a parsed ARM machine
389 class ARMOperand : public MCParsedAsmOperand {
399 k_InstSyncBarrierOpt,
411 k_VectorListAllLanes,
418 k_BitfieldDescriptor,
422 SMLoc StartLoc, EndLoc, AlignmentLoc;
423 SmallVector<unsigned, 8> Registers;
426 ARMCC::CondCodes Val;
433 struct CoprocOptionOp {
446 ARM_ISB::InstSyncBOpt Val;
450 ARM_PROC::IFlags Val;
470 // A vector register list is a sequential list of 1 to 4 registers.
471 struct VectorListOp {
478 struct VectorIndexOp {
486 /// Combined record for all forms of ARM address expressions.
489 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
491 const MCConstantExpr *OffsetImm; // Offset immediate value
492 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
493 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
494 unsigned ShiftImm; // shift for OffsetReg.
495 unsigned Alignment; // 0 = no alignment specified
496 // n = alignment in bytes (2, 4, 8, 16, or 32)
497 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
500 struct PostIdxRegOp {
503 ARM_AM::ShiftOpc ShiftTy;
507 struct ShifterImmOp {
512 struct RegShiftedRegOp {
513 ARM_AM::ShiftOpc ShiftTy;
519 struct RegShiftedImmOp {
520 ARM_AM::ShiftOpc ShiftTy;
542 struct CoprocOptionOp CoprocOption;
543 struct MBOptOp MBOpt;
544 struct ISBOptOp ISBOpt;
545 struct ITMaskOp ITMask;
546 struct IFlagsOp IFlags;
547 struct MMaskOp MMask;
548 struct BankedRegOp BankedReg;
551 struct VectorListOp VectorList;
552 struct VectorIndexOp VectorIndex;
554 struct MemoryOp Memory;
555 struct PostIdxRegOp PostIdxReg;
556 struct ShifterImmOp ShifterImm;
557 struct RegShiftedRegOp RegShiftedReg;
558 struct RegShiftedImmOp RegShiftedImm;
559 struct RotImmOp RotImm;
560 struct ModImmOp ModImm;
561 struct BitfieldOp Bitfield;
565 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
566 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
568 StartLoc = o.StartLoc;
585 case k_DPRRegisterList:
586 case k_SPRRegisterList:
587 Registers = o.Registers;
590 case k_VectorListAllLanes:
591 case k_VectorListIndexed:
592 VectorList = o.VectorList;
599 CoprocOption = o.CoprocOption;
604 case k_MemBarrierOpt:
607 case k_InstSyncBarrierOpt:
612 case k_PostIndexRegister:
613 PostIdxReg = o.PostIdxReg;
619 BankedReg = o.BankedReg;
624 case k_ShifterImmediate:
625 ShifterImm = o.ShifterImm;
627 case k_ShiftedRegister:
628 RegShiftedReg = o.RegShiftedReg;
630 case k_ShiftedImmediate:
631 RegShiftedImm = o.RegShiftedImm;
633 case k_RotateImmediate:
636 case k_ModifiedImmediate:
639 case k_BitfieldDescriptor:
640 Bitfield = o.Bitfield;
643 VectorIndex = o.VectorIndex;
648 /// getStartLoc - Get the location of the first token of this operand.
649 SMLoc getStartLoc() const override { return StartLoc; }
650 /// getEndLoc - Get the location of the last token of this operand.
651 SMLoc getEndLoc() const override { return EndLoc; }
652 /// getLocRange - Get the range between the first and last token of this
654 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
656 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
657 SMLoc getAlignmentLoc() const {
658 assert(Kind == k_Memory && "Invalid access!");
662 ARMCC::CondCodes getCondCode() const {
663 assert(Kind == k_CondCode && "Invalid access!");
667 unsigned getCoproc() const {
668 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
672 StringRef getToken() const {
673 assert(Kind == k_Token && "Invalid access!");
674 return StringRef(Tok.Data, Tok.Length);
677 unsigned getReg() const override {
678 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
682 const SmallVectorImpl<unsigned> &getRegList() const {
683 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
684 Kind == k_SPRRegisterList) && "Invalid access!");
688 const MCExpr *getImm() const {
689 assert(isImm() && "Invalid access!");
693 unsigned getVectorIndex() const {
694 assert(Kind == k_VectorIndex && "Invalid access!");
695 return VectorIndex.Val;
698 ARM_MB::MemBOpt getMemBarrierOpt() const {
699 assert(Kind == k_MemBarrierOpt && "Invalid access!");
703 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
704 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
708 ARM_PROC::IFlags getProcIFlags() const {
709 assert(Kind == k_ProcIFlags && "Invalid access!");
713 unsigned getMSRMask() const {
714 assert(Kind == k_MSRMask && "Invalid access!");
718 unsigned getBankedReg() const {
719 assert(Kind == k_BankedReg && "Invalid access!");
720 return BankedReg.Val;
723 bool isCoprocNum() const { return Kind == k_CoprocNum; }
724 bool isCoprocReg() const { return Kind == k_CoprocReg; }
725 bool isCoprocOption() const { return Kind == k_CoprocOption; }
726 bool isCondCode() const { return Kind == k_CondCode; }
727 bool isCCOut() const { return Kind == k_CCOut; }
728 bool isITMask() const { return Kind == k_ITCondMask; }
729 bool isITCondCode() const { return Kind == k_CondCode; }
730 bool isImm() const override { return Kind == k_Immediate; }
731 // checks whether this operand is an unsigned offset which fits is a field
732 // of specified width and scaled by a specific number of bits
733 template<unsigned width, unsigned scale>
734 bool isUnsignedOffset() const {
735 if (!isImm()) return false;
736 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
737 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
738 int64_t Val = CE->getValue();
739 int64_t Align = 1LL << scale;
740 int64_t Max = Align * ((1LL << width) - 1);
741 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
745 // checks whether this operand is an signed offset which fits is a field
746 // of specified width and scaled by a specific number of bits
747 template<unsigned width, unsigned scale>
748 bool isSignedOffset() const {
749 if (!isImm()) return false;
750 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
751 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
752 int64_t Val = CE->getValue();
753 int64_t Align = 1LL << scale;
754 int64_t Max = Align * ((1LL << (width-1)) - 1);
755 int64_t Min = -Align * (1LL << (width-1));
756 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
761 // checks whether this operand is a memory operand computed as an offset
762 // applied to PC. the offset may have 8 bits of magnitude and is represented
763 // with two bits of shift. textually it may be either [pc, #imm], #imm or
764 // relocable expression...
765 bool isThumbMemPC() const {
768 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
770 if (!CE) return false;
771 Val = CE->getValue();
774 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
775 if(Memory.BaseRegNum != ARM::PC) return false;
776 Val = Memory.OffsetImm->getValue();
779 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
781 bool isFPImm() const {
782 if (!isImm()) return false;
783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784 if (!CE) return false;
785 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
788 bool isFBits16() const {
789 if (!isImm()) return false;
790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791 if (!CE) return false;
792 int64_t Value = CE->getValue();
793 return Value >= 0 && Value <= 16;
795 bool isFBits32() const {
796 if (!isImm()) return false;
797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798 if (!CE) return false;
799 int64_t Value = CE->getValue();
800 return Value >= 1 && Value <= 32;
802 bool isImm8s4() const {
803 if (!isImm()) return false;
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805 if (!CE) return false;
806 int64_t Value = CE->getValue();
807 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
809 bool isImm0_1020s4() const {
810 if (!isImm()) return false;
811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
812 if (!CE) return false;
813 int64_t Value = CE->getValue();
814 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
816 bool isImm0_508s4() const {
817 if (!isImm()) return false;
818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
819 if (!CE) return false;
820 int64_t Value = CE->getValue();
821 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
823 bool isImm0_508s4Neg() const {
824 if (!isImm()) return false;
825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
826 if (!CE) return false;
827 int64_t Value = -CE->getValue();
828 // explicitly exclude zero. we want that to use the normal 0_508 version.
829 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
831 bool isImm0_239() const {
832 if (!isImm()) return false;
833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834 if (!CE) return false;
835 int64_t Value = CE->getValue();
836 return Value >= 0 && Value < 240;
838 bool isImm0_255() const {
839 if (!isImm()) return false;
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841 if (!CE) return false;
842 int64_t Value = CE->getValue();
843 return Value >= 0 && Value < 256;
845 bool isImm0_4095() const {
846 if (!isImm()) return false;
847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848 if (!CE) return false;
849 int64_t Value = CE->getValue();
850 return Value >= 0 && Value < 4096;
852 bool isImm0_4095Neg() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = -CE->getValue();
857 return Value > 0 && Value < 4096;
859 bool isImm0_1() const {
860 if (!isImm()) return false;
861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862 if (!CE) return false;
863 int64_t Value = CE->getValue();
864 return Value >= 0 && Value < 2;
866 bool isImm0_3() const {
867 if (!isImm()) return false;
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869 if (!CE) return false;
870 int64_t Value = CE->getValue();
871 return Value >= 0 && Value < 4;
873 bool isImm0_7() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
878 return Value >= 0 && Value < 8;
880 bool isImm0_15() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
885 return Value >= 0 && Value < 16;
887 bool isImm0_31() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
892 return Value >= 0 && Value < 32;
894 bool isImm0_63() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
899 return Value >= 0 && Value < 64;
901 bool isImm8() const {
902 if (!isImm()) return false;
903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904 if (!CE) return false;
905 int64_t Value = CE->getValue();
908 bool isImm16() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
915 bool isImm32() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
922 bool isShrImm8() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
927 return Value > 0 && Value <= 8;
929 bool isShrImm16() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
934 return Value > 0 && Value <= 16;
936 bool isShrImm32() const {
937 if (!isImm()) return false;
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939 if (!CE) return false;
940 int64_t Value = CE->getValue();
941 return Value > 0 && Value <= 32;
943 bool isShrImm64() const {
944 if (!isImm()) return false;
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 if (!CE) return false;
947 int64_t Value = CE->getValue();
948 return Value > 0 && Value <= 64;
950 bool isImm1_7() const {
951 if (!isImm()) return false;
952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953 if (!CE) return false;
954 int64_t Value = CE->getValue();
955 return Value > 0 && Value < 8;
957 bool isImm1_15() const {
958 if (!isImm()) return false;
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 if (!CE) return false;
961 int64_t Value = CE->getValue();
962 return Value > 0 && Value < 16;
964 bool isImm1_31() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 if (!CE) return false;
968 int64_t Value = CE->getValue();
969 return Value > 0 && Value < 32;
971 bool isImm1_16() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 if (!CE) return false;
975 int64_t Value = CE->getValue();
976 return Value > 0 && Value < 17;
978 bool isImm1_32() const {
979 if (!isImm()) return false;
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 if (!CE) return false;
982 int64_t Value = CE->getValue();
983 return Value > 0 && Value < 33;
985 bool isImm0_32() const {
986 if (!isImm()) return false;
987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988 if (!CE) return false;
989 int64_t Value = CE->getValue();
990 return Value >= 0 && Value < 33;
992 bool isImm0_65535() const {
993 if (!isImm()) return false;
994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
995 if (!CE) return false;
996 int64_t Value = CE->getValue();
997 return Value >= 0 && Value < 65536;
999 bool isImm256_65535Expr() const {
1000 if (!isImm()) return false;
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002 // If it's not a constant expression, it'll generate a fixup and be
1004 if (!CE) return true;
1005 int64_t Value = CE->getValue();
1006 return Value >= 256 && Value < 65536;
1008 bool isImm0_65535Expr() const {
1009 if (!isImm()) return false;
1010 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1011 // If it's not a constant expression, it'll generate a fixup and be
1013 if (!CE) return true;
1014 int64_t Value = CE->getValue();
1015 return Value >= 0 && Value < 65536;
1017 bool isImm24bit() const {
1018 if (!isImm()) return false;
1019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020 if (!CE) return false;
1021 int64_t Value = CE->getValue();
1022 return Value >= 0 && Value <= 0xffffff;
1024 bool isImmThumbSR() const {
1025 if (!isImm()) return false;
1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027 if (!CE) return false;
1028 int64_t Value = CE->getValue();
1029 return Value > 0 && Value < 33;
1031 bool isPKHLSLImm() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return Value >= 0 && Value < 32;
1038 bool isPKHASRImm() const {
1039 if (!isImm()) return false;
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Value = CE->getValue();
1043 return Value > 0 && Value <= 32;
1045 bool isAdrLabel() const {
1046 // If we have an immediate that's not a constant, treat it as a label
1047 // reference needing a fixup.
1048 if (isImm() && !isa<MCConstantExpr>(getImm()))
1051 // If it is a constant, it must fit into a modified immediate encoding.
1052 if (!isImm()) return false;
1053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1054 if (!CE) return false;
1055 int64_t Value = CE->getValue();
1056 return (ARM_AM::getSOImmVal(Value) != -1 ||
1057 ARM_AM::getSOImmVal(-Value) != -1);
1059 bool isT2SOImm() const {
1060 if (!isImm()) return false;
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Value = CE->getValue();
1064 return ARM_AM::getT2SOImmVal(Value) != -1;
1066 bool isT2SOImmNot() const {
1067 if (!isImm()) return false;
1068 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1069 if (!CE) return false;
1070 int64_t Value = CE->getValue();
1071 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1072 ARM_AM::getT2SOImmVal(~Value) != -1;
1074 bool isT2SOImmNeg() const {
1075 if (!isImm()) return false;
1076 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1077 if (!CE) return false;
1078 int64_t Value = CE->getValue();
1079 // Only use this when not representable as a plain so_imm.
1080 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1081 ARM_AM::getT2SOImmVal(-Value) != -1;
1083 bool isSetEndImm() const {
1084 if (!isImm()) return false;
1085 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1086 if (!CE) return false;
1087 int64_t Value = CE->getValue();
1088 return Value == 1 || Value == 0;
1090 bool isReg() const override { return Kind == k_Register; }
1091 bool isRegList() const { return Kind == k_RegisterList; }
1092 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1093 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1094 bool isToken() const override { return Kind == k_Token; }
1095 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1096 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1097 bool isMem() const override { return Kind == k_Memory; }
1098 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1099 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1100 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1101 bool isRotImm() const { return Kind == k_RotateImmediate; }
1102 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1103 bool isModImmNot() const {
1104 if (!isImm()) return false;
1105 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1106 if (!CE) return false;
1107 int64_t Value = CE->getValue();
1108 return ARM_AM::getSOImmVal(~Value) != -1;
1110 bool isModImmNeg() const {
1111 if (!isImm()) return false;
1112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1113 if (!CE) return false;
1114 int64_t Value = CE->getValue();
1115 return ARM_AM::getSOImmVal(Value) == -1 &&
1116 ARM_AM::getSOImmVal(-Value) != -1;
1118 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1119 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1120 bool isPostIdxReg() const {
1121 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1123 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1126 // No offset of any kind.
1127 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1128 (alignOK || Memory.Alignment == Alignment);
1130 bool isMemPCRelImm12() const {
1131 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1133 // Base register must be PC.
1134 if (Memory.BaseRegNum != ARM::PC)
1136 // Immediate offset in range [-4095, 4095].
1137 if (!Memory.OffsetImm) return true;
1138 int64_t Val = Memory.OffsetImm->getValue();
1139 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1141 bool isAlignedMemory() const {
1142 return isMemNoOffset(true);
1144 bool isAlignedMemoryNone() const {
1145 return isMemNoOffset(false, 0);
1147 bool isDupAlignedMemoryNone() const {
1148 return isMemNoOffset(false, 0);
1150 bool isAlignedMemory16() const {
1151 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1153 return isMemNoOffset(false, 0);
1155 bool isDupAlignedMemory16() const {
1156 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1158 return isMemNoOffset(false, 0);
1160 bool isAlignedMemory32() const {
1161 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1163 return isMemNoOffset(false, 0);
1165 bool isDupAlignedMemory32() const {
1166 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1168 return isMemNoOffset(false, 0);
1170 bool isAlignedMemory64() const {
1171 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1173 return isMemNoOffset(false, 0);
1175 bool isDupAlignedMemory64() const {
1176 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1178 return isMemNoOffset(false, 0);
1180 bool isAlignedMemory64or128() const {
1181 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1183 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1185 return isMemNoOffset(false, 0);
1187 bool isDupAlignedMemory64or128() const {
1188 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1190 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1192 return isMemNoOffset(false, 0);
1194 bool isAlignedMemory64or128or256() const {
1195 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1197 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1199 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1201 return isMemNoOffset(false, 0);
1203 bool isAddrMode2() const {
1204 if (!isMem() || Memory.Alignment != 0) return false;
1205 // Check for register offset.
1206 if (Memory.OffsetRegNum) return true;
1207 // Immediate offset in range [-4095, 4095].
1208 if (!Memory.OffsetImm) return true;
1209 int64_t Val = Memory.OffsetImm->getValue();
1210 return Val > -4096 && Val < 4096;
1212 bool isAM2OffsetImm() const {
1213 if (!isImm()) return false;
1214 // Immediate offset in range [-4095, 4095].
1215 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1216 if (!CE) return false;
1217 int64_t Val = CE->getValue();
1218 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1220 bool isAddrMode3() const {
1221 // If we have an immediate that's not a constant, treat it as a label
1222 // reference needing a fixup. If it is a constant, it's something else
1223 // and we reject it.
1224 if (isImm() && !isa<MCConstantExpr>(getImm()))
1226 if (!isMem() || Memory.Alignment != 0) return false;
1227 // No shifts are legal for AM3.
1228 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1229 // Check for register offset.
1230 if (Memory.OffsetRegNum) return true;
1231 // Immediate offset in range [-255, 255].
1232 if (!Memory.OffsetImm) return true;
1233 int64_t Val = Memory.OffsetImm->getValue();
1234 // The #-0 offset is encoded as INT32_MIN, and we have to check
1236 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1238 bool isAM3Offset() const {
1239 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1241 if (Kind == k_PostIndexRegister)
1242 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1243 // Immediate offset in range [-255, 255].
1244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1245 if (!CE) return false;
1246 int64_t Val = CE->getValue();
1247 // Special case, #-0 is INT32_MIN.
1248 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1250 bool isAddrMode5() const {
1251 // If we have an immediate that's not a constant, treat it as a label
1252 // reference needing a fixup. If it is a constant, it's something else
1253 // and we reject it.
1254 if (isImm() && !isa<MCConstantExpr>(getImm()))
1256 if (!isMem() || Memory.Alignment != 0) return false;
1257 // Check for register offset.
1258 if (Memory.OffsetRegNum) return false;
1259 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1260 if (!Memory.OffsetImm) return true;
1261 int64_t Val = Memory.OffsetImm->getValue();
1262 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1265 bool isMemTBB() const {
1266 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1267 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1271 bool isMemTBH() const {
1272 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1273 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1274 Memory.Alignment != 0 )
1278 bool isMemRegOffset() const {
1279 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1283 bool isT2MemRegOffset() const {
1284 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1285 Memory.Alignment != 0)
1287 // Only lsl #{0, 1, 2, 3} allowed.
1288 if (Memory.ShiftType == ARM_AM::no_shift)
1290 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1294 bool isMemThumbRR() const {
1295 // Thumb reg+reg addressing is simple. Just two registers, a base and
1296 // an offset. No shifts, negations or any other complicating factors.
1297 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1298 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1300 return isARMLowRegister(Memory.BaseRegNum) &&
1301 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1303 bool isMemThumbRIs4() const {
1304 if (!isMem() || Memory.OffsetRegNum != 0 ||
1305 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1307 // Immediate offset, multiple of 4 in range [0, 124].
1308 if (!Memory.OffsetImm) return true;
1309 int64_t Val = Memory.OffsetImm->getValue();
1310 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1312 bool isMemThumbRIs2() const {
1313 if (!isMem() || Memory.OffsetRegNum != 0 ||
1314 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1316 // Immediate offset, multiple of 4 in range [0, 62].
1317 if (!Memory.OffsetImm) return true;
1318 int64_t Val = Memory.OffsetImm->getValue();
1319 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1321 bool isMemThumbRIs1() const {
1322 if (!isMem() || Memory.OffsetRegNum != 0 ||
1323 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1325 // Immediate offset in range [0, 31].
1326 if (!Memory.OffsetImm) return true;
1327 int64_t Val = Memory.OffsetImm->getValue();
1328 return Val >= 0 && Val <= 31;
1330 bool isMemThumbSPI() const {
1331 if (!isMem() || Memory.OffsetRegNum != 0 ||
1332 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1334 // Immediate offset, multiple of 4 in range [0, 1020].
1335 if (!Memory.OffsetImm) return true;
1336 int64_t Val = Memory.OffsetImm->getValue();
1337 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1339 bool isMemImm8s4Offset() const {
1340 // If we have an immediate that's not a constant, treat it as a label
1341 // reference needing a fixup. If it is a constant, it's something else
1342 // and we reject it.
1343 if (isImm() && !isa<MCConstantExpr>(getImm()))
1345 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1347 // Immediate offset a multiple of 4 in range [-1020, 1020].
1348 if (!Memory.OffsetImm) return true;
1349 int64_t Val = Memory.OffsetImm->getValue();
1350 // Special case, #-0 is INT32_MIN.
1351 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1353 bool isMemImm0_1020s4Offset() const {
1354 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1356 // Immediate offset a multiple of 4 in range [0, 1020].
1357 if (!Memory.OffsetImm) return true;
1358 int64_t Val = Memory.OffsetImm->getValue();
1359 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1361 bool isMemImm8Offset() const {
1362 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1364 // Base reg of PC isn't allowed for these encodings.
1365 if (Memory.BaseRegNum == ARM::PC) return false;
1366 // Immediate offset in range [-255, 255].
1367 if (!Memory.OffsetImm) return true;
1368 int64_t Val = Memory.OffsetImm->getValue();
1369 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1371 bool isMemPosImm8Offset() const {
1372 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1374 // Immediate offset in range [0, 255].
1375 if (!Memory.OffsetImm) return true;
1376 int64_t Val = Memory.OffsetImm->getValue();
1377 return Val >= 0 && Val < 256;
1379 bool isMemNegImm8Offset() const {
1380 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1382 // Base reg of PC isn't allowed for these encodings.
1383 if (Memory.BaseRegNum == ARM::PC) return false;
1384 // Immediate offset in range [-255, -1].
1385 if (!Memory.OffsetImm) return false;
1386 int64_t Val = Memory.OffsetImm->getValue();
1387 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1389 bool isMemUImm12Offset() const {
1390 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1392 // Immediate offset in range [0, 4095].
1393 if (!Memory.OffsetImm) return true;
1394 int64_t Val = Memory.OffsetImm->getValue();
1395 return (Val >= 0 && Val < 4096);
1397 bool isMemImm12Offset() const {
1398 // If we have an immediate that's not a constant, treat it as a label
1399 // reference needing a fixup. If it is a constant, it's something else
1400 // and we reject it.
1401 if (isImm() && !isa<MCConstantExpr>(getImm()))
1404 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1406 // Immediate offset in range [-4095, 4095].
1407 if (!Memory.OffsetImm) return true;
1408 int64_t Val = Memory.OffsetImm->getValue();
1409 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1411 bool isPostIdxImm8() const {
1412 if (!isImm()) return false;
1413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1414 if (!CE) return false;
1415 int64_t Val = CE->getValue();
1416 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1418 bool isPostIdxImm8s4() const {
1419 if (!isImm()) return false;
1420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1421 if (!CE) return false;
1422 int64_t Val = CE->getValue();
1423 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1427 bool isMSRMask() const { return Kind == k_MSRMask; }
1428 bool isBankedReg() const { return Kind == k_BankedReg; }
1429 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1432 bool isSingleSpacedVectorList() const {
1433 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1435 bool isDoubleSpacedVectorList() const {
1436 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1438 bool isVecListOneD() const {
1439 if (!isSingleSpacedVectorList()) return false;
1440 return VectorList.Count == 1;
1443 bool isVecListDPair() const {
1444 if (!isSingleSpacedVectorList()) return false;
1445 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1446 .contains(VectorList.RegNum));
1449 bool isVecListThreeD() const {
1450 if (!isSingleSpacedVectorList()) return false;
1451 return VectorList.Count == 3;
1454 bool isVecListFourD() const {
1455 if (!isSingleSpacedVectorList()) return false;
1456 return VectorList.Count == 4;
1459 bool isVecListDPairSpaced() const {
1460 if (Kind != k_VectorList) return false;
1461 if (isSingleSpacedVectorList()) return false;
1462 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1463 .contains(VectorList.RegNum));
1466 bool isVecListThreeQ() const {
1467 if (!isDoubleSpacedVectorList()) return false;
1468 return VectorList.Count == 3;
1471 bool isVecListFourQ() const {
1472 if (!isDoubleSpacedVectorList()) return false;
1473 return VectorList.Count == 4;
1476 bool isSingleSpacedVectorAllLanes() const {
1477 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1479 bool isDoubleSpacedVectorAllLanes() const {
1480 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1482 bool isVecListOneDAllLanes() const {
1483 if (!isSingleSpacedVectorAllLanes()) return false;
1484 return VectorList.Count == 1;
1487 bool isVecListDPairAllLanes() const {
1488 if (!isSingleSpacedVectorAllLanes()) return false;
1489 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1490 .contains(VectorList.RegNum));
1493 bool isVecListDPairSpacedAllLanes() const {
1494 if (!isDoubleSpacedVectorAllLanes()) return false;
1495 return VectorList.Count == 2;
1498 bool isVecListThreeDAllLanes() const {
1499 if (!isSingleSpacedVectorAllLanes()) return false;
1500 return VectorList.Count == 3;
1503 bool isVecListThreeQAllLanes() const {
1504 if (!isDoubleSpacedVectorAllLanes()) return false;
1505 return VectorList.Count == 3;
1508 bool isVecListFourDAllLanes() const {
1509 if (!isSingleSpacedVectorAllLanes()) return false;
1510 return VectorList.Count == 4;
1513 bool isVecListFourQAllLanes() const {
1514 if (!isDoubleSpacedVectorAllLanes()) return false;
1515 return VectorList.Count == 4;
1518 bool isSingleSpacedVectorIndexed() const {
1519 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1521 bool isDoubleSpacedVectorIndexed() const {
1522 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1524 bool isVecListOneDByteIndexed() const {
1525 if (!isSingleSpacedVectorIndexed()) return false;
1526 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1529 bool isVecListOneDHWordIndexed() const {
1530 if (!isSingleSpacedVectorIndexed()) return false;
1531 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1534 bool isVecListOneDWordIndexed() const {
1535 if (!isSingleSpacedVectorIndexed()) return false;
1536 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1539 bool isVecListTwoDByteIndexed() const {
1540 if (!isSingleSpacedVectorIndexed()) return false;
1541 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1544 bool isVecListTwoDHWordIndexed() const {
1545 if (!isSingleSpacedVectorIndexed()) return false;
1546 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1549 bool isVecListTwoQWordIndexed() const {
1550 if (!isDoubleSpacedVectorIndexed()) return false;
1551 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1554 bool isVecListTwoQHWordIndexed() const {
1555 if (!isDoubleSpacedVectorIndexed()) return false;
1556 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1559 bool isVecListTwoDWordIndexed() const {
1560 if (!isSingleSpacedVectorIndexed()) return false;
1561 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1564 bool isVecListThreeDByteIndexed() const {
1565 if (!isSingleSpacedVectorIndexed()) return false;
1566 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1569 bool isVecListThreeDHWordIndexed() const {
1570 if (!isSingleSpacedVectorIndexed()) return false;
1571 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1574 bool isVecListThreeQWordIndexed() const {
1575 if (!isDoubleSpacedVectorIndexed()) return false;
1576 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1579 bool isVecListThreeQHWordIndexed() const {
1580 if (!isDoubleSpacedVectorIndexed()) return false;
1581 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1584 bool isVecListThreeDWordIndexed() const {
1585 if (!isSingleSpacedVectorIndexed()) return false;
1586 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1589 bool isVecListFourDByteIndexed() const {
1590 if (!isSingleSpacedVectorIndexed()) return false;
1591 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1594 bool isVecListFourDHWordIndexed() const {
1595 if (!isSingleSpacedVectorIndexed()) return false;
1596 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1599 bool isVecListFourQWordIndexed() const {
1600 if (!isDoubleSpacedVectorIndexed()) return false;
1601 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1604 bool isVecListFourQHWordIndexed() const {
1605 if (!isDoubleSpacedVectorIndexed()) return false;
1606 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1609 bool isVecListFourDWordIndexed() const {
1610 if (!isSingleSpacedVectorIndexed()) return false;
1611 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1614 bool isVectorIndex8() const {
1615 if (Kind != k_VectorIndex) return false;
1616 return VectorIndex.Val < 8;
1618 bool isVectorIndex16() const {
1619 if (Kind != k_VectorIndex) return false;
1620 return VectorIndex.Val < 4;
1622 bool isVectorIndex32() const {
1623 if (Kind != k_VectorIndex) return false;
1624 return VectorIndex.Val < 2;
1627 bool isNEONi8splat() const {
1628 if (!isImm()) return false;
1629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630 // Must be a constant.
1631 if (!CE) return false;
1632 int64_t Value = CE->getValue();
1633 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1635 return Value >= 0 && Value < 256;
1638 bool isNEONi16splat() const {
1639 if (isNEONByteReplicate(2))
1640 return false; // Leave that for bytes replication and forbid by default.
1643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1644 // Must be a constant.
1645 if (!CE) return false;
1646 unsigned Value = CE->getValue();
1647 return ARM_AM::isNEONi16splat(Value);
1650 bool isNEONi16splatNot() const {
1653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1654 // Must be a constant.
1655 if (!CE) return false;
1656 unsigned Value = CE->getValue();
1657 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1660 bool isNEONi32splat() const {
1661 if (isNEONByteReplicate(4))
1662 return false; // Leave that for bytes replication and forbid by default.
1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1666 // Must be a constant.
1667 if (!CE) return false;
1668 unsigned Value = CE->getValue();
1669 return ARM_AM::isNEONi32splat(Value);
1672 bool isNEONi32splatNot() const {
1675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1676 // Must be a constant.
1677 if (!CE) return false;
1678 unsigned Value = CE->getValue();
1679 return ARM_AM::isNEONi32splat(~Value);
1682 bool isNEONByteReplicate(unsigned NumBytes) const {
1685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1686 // Must be a constant.
1689 int64_t Value = CE->getValue();
1691 return false; // Don't bother with zero.
1693 unsigned char B = Value & 0xff;
1694 for (unsigned i = 1; i < NumBytes; ++i) {
1696 if ((Value & 0xff) != B)
1701 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1702 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1703 bool isNEONi32vmov() const {
1704 if (isNEONByteReplicate(4))
1705 return false; // Let it to be classified as byte-replicate case.
1708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1709 // Must be a constant.
1712 int64_t Value = CE->getValue();
1713 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1714 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1715 // FIXME: This is probably wrong and a copy and paste from previous example
1716 return (Value >= 0 && Value < 256) ||
1717 (Value >= 0x0100 && Value <= 0xff00) ||
1718 (Value >= 0x010000 && Value <= 0xff0000) ||
1719 (Value >= 0x01000000 && Value <= 0xff000000) ||
1720 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1721 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1723 bool isNEONi32vmovNeg() const {
1724 if (!isImm()) return false;
1725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1726 // Must be a constant.
1727 if (!CE) return false;
1728 int64_t Value = ~CE->getValue();
1729 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1730 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1731 // FIXME: This is probably wrong and a copy and paste from previous example
1732 return (Value >= 0 && Value < 256) ||
1733 (Value >= 0x0100 && Value <= 0xff00) ||
1734 (Value >= 0x010000 && Value <= 0xff0000) ||
1735 (Value >= 0x01000000 && Value <= 0xff000000) ||
1736 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1737 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1740 bool isNEONi64splat() const {
1741 if (!isImm()) return false;
1742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1743 // Must be a constant.
1744 if (!CE) return false;
1745 uint64_t Value = CE->getValue();
1746 // i64 value with each byte being either 0 or 0xff.
1747 for (unsigned i = 0; i < 8; ++i)
1748 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1752 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1753 // Add as immediates when possible. Null MCExpr = 0.
1755 Inst.addOperand(MCOperand::createImm(0));
1756 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1757 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1759 Inst.addOperand(MCOperand::createExpr(Expr));
1762 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1763 assert(N == 2 && "Invalid number of operands!");
1764 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1765 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1766 Inst.addOperand(MCOperand::createReg(RegNum));
1769 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1770 assert(N == 1 && "Invalid number of operands!");
1771 Inst.addOperand(MCOperand::createImm(getCoproc()));
1774 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 Inst.addOperand(MCOperand::createImm(getCoproc()));
1779 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1780 assert(N == 1 && "Invalid number of operands!");
1781 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1784 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1785 assert(N == 1 && "Invalid number of operands!");
1786 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1789 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1794 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1795 assert(N == 1 && "Invalid number of operands!");
1796 Inst.addOperand(MCOperand::createReg(getReg()));
1799 void addRegOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 1 && "Invalid number of operands!");
1801 Inst.addOperand(MCOperand::createReg(getReg()));
1804 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 3 && "Invalid number of operands!");
1806 assert(isRegShiftedReg() &&
1807 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1808 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1809 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1810 Inst.addOperand(MCOperand::createImm(
1811 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1814 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1815 assert(N == 2 && "Invalid number of operands!");
1816 assert(isRegShiftedImm() &&
1817 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1818 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1819 // Shift of #32 is encoded as 0 where permitted
1820 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1821 Inst.addOperand(MCOperand::createImm(
1822 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1825 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1826 assert(N == 1 && "Invalid number of operands!");
1827 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1831 void addRegListOperands(MCInst &Inst, unsigned N) const {
1832 assert(N == 1 && "Invalid number of operands!");
1833 const SmallVectorImpl<unsigned> &RegList = getRegList();
1834 for (SmallVectorImpl<unsigned>::const_iterator
1835 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1836 Inst.addOperand(MCOperand::createReg(*I));
1839 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1840 addRegListOperands(Inst, N);
1843 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1844 addRegListOperands(Inst, N);
1847 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1848 assert(N == 1 && "Invalid number of operands!");
1849 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1850 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1853 void addModImmOperands(MCInst &Inst, unsigned N) const {
1854 assert(N == 1 && "Invalid number of operands!");
1856 // Support for fixups (MCFixup)
1858 return addImmOperands(Inst, N);
1860 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1863 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 1 && "Invalid number of operands!");
1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1867 Inst.addOperand(MCOperand::createImm(Enc));
1870 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1871 assert(N == 1 && "Invalid number of operands!");
1872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1873 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1874 Inst.addOperand(MCOperand::createImm(Enc));
1877 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1878 assert(N == 1 && "Invalid number of operands!");
1879 // Munge the lsb/width into a bitfield mask.
1880 unsigned lsb = Bitfield.LSB;
1881 unsigned width = Bitfield.Width;
1882 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1883 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1884 (32 - (lsb + width)));
1885 Inst.addOperand(MCOperand::createImm(Mask));
1888 void addImmOperands(MCInst &Inst, unsigned N) const {
1889 assert(N == 1 && "Invalid number of operands!");
1890 addExpr(Inst, getImm());
1893 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1894 assert(N == 1 && "Invalid number of operands!");
1895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1896 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1899 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1900 assert(N == 1 && "Invalid number of operands!");
1901 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1902 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1905 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1906 assert(N == 1 && "Invalid number of operands!");
1907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1908 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1909 Inst.addOperand(MCOperand::createImm(Val));
1912 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1913 assert(N == 1 && "Invalid number of operands!");
1914 // FIXME: We really want to scale the value here, but the LDRD/STRD
1915 // instruction don't encode operands that way yet.
1916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1917 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1920 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1921 assert(N == 1 && "Invalid number of operands!");
1922 // The immediate is scaled by four in the encoding and is stored
1923 // in the MCInst as such. Lop off the low two bits here.
1924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1925 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1928 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1929 assert(N == 1 && "Invalid number of operands!");
1930 // The immediate is scaled by four in the encoding and is stored
1931 // in the MCInst as such. Lop off the low two bits here.
1932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1933 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1936 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1937 assert(N == 1 && "Invalid number of operands!");
1938 // The immediate is scaled by four in the encoding and is stored
1939 // in the MCInst as such. Lop off the low two bits here.
1940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1941 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1944 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1945 assert(N == 1 && "Invalid number of operands!");
1946 // The constant encodes as the immediate-1, and we store in the instruction
1947 // the bits as encoded, so subtract off one here.
1948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1949 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1952 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1953 assert(N == 1 && "Invalid number of operands!");
1954 // The constant encodes as the immediate-1, and we store in the instruction
1955 // the bits as encoded, so subtract off one here.
1956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1957 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1960 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1961 assert(N == 1 && "Invalid number of operands!");
1962 // The constant encodes as the immediate, except for 32, which encodes as
1964 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1965 unsigned Imm = CE->getValue();
1966 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
1969 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1970 assert(N == 1 && "Invalid number of operands!");
1971 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1972 // the instruction as well.
1973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1974 int Val = CE->getValue();
1975 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
1978 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1979 assert(N == 1 && "Invalid number of operands!");
1980 // The operand is actually a t2_so_imm, but we have its bitwise
1981 // negation in the assembly source, so twiddle it here.
1982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1983 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
1986 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1987 assert(N == 1 && "Invalid number of operands!");
1988 // The operand is actually a t2_so_imm, but we have its
1989 // negation in the assembly source, so twiddle it here.
1990 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1991 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1994 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1995 assert(N == 1 && "Invalid number of operands!");
1996 // The operand is actually an imm0_4095, but we have its
1997 // negation in the assembly source, so twiddle it here.
1998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1999 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
2002 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2003 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2004 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2008 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2009 assert(SR && "Unknown value type!");
2010 Inst.addOperand(MCOperand::createExpr(SR));
2013 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2014 assert(N == 1 && "Invalid number of operands!");
2016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2018 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2022 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2023 assert(SR && "Unknown value type!");
2024 Inst.addOperand(MCOperand::createExpr(SR));
2028 assert(isMem() && "Unknown value type!");
2029 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2030 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2033 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2034 assert(N == 1 && "Invalid number of operands!");
2035 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2038 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2039 assert(N == 1 && "Invalid number of operands!");
2040 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2043 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2044 assert(N == 1 && "Invalid number of operands!");
2045 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2048 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2049 assert(N == 1 && "Invalid number of operands!");
2050 int32_t Imm = Memory.OffsetImm->getValue();
2051 Inst.addOperand(MCOperand::createImm(Imm));
2054 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2055 assert(N == 1 && "Invalid number of operands!");
2056 assert(isImm() && "Not an immediate!");
2058 // If we have an immediate that's not a constant, treat it as a label
2059 // reference needing a fixup.
2060 if (!isa<MCConstantExpr>(getImm())) {
2061 Inst.addOperand(MCOperand::createExpr(getImm()));
2065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2066 int Val = CE->getValue();
2067 Inst.addOperand(MCOperand::createImm(Val));
2070 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2071 assert(N == 2 && "Invalid number of operands!");
2072 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2073 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2076 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2077 addAlignedMemoryOperands(Inst, N);
2080 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2081 addAlignedMemoryOperands(Inst, N);
2084 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2085 addAlignedMemoryOperands(Inst, N);
2088 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2089 addAlignedMemoryOperands(Inst, N);
2092 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2093 addAlignedMemoryOperands(Inst, N);
2096 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2097 addAlignedMemoryOperands(Inst, N);
2100 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2101 addAlignedMemoryOperands(Inst, N);
2104 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2105 addAlignedMemoryOperands(Inst, N);
2108 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2109 addAlignedMemoryOperands(Inst, N);
2112 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2113 addAlignedMemoryOperands(Inst, N);
2116 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2117 addAlignedMemoryOperands(Inst, N);
2120 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2121 assert(N == 3 && "Invalid number of operands!");
2122 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2123 if (!Memory.OffsetRegNum) {
2124 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2125 // Special case for #-0
2126 if (Val == INT32_MIN) Val = 0;
2127 if (Val < 0) Val = -Val;
2128 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2130 // For register offset, we encode the shift type and negation flag
2132 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2133 Memory.ShiftImm, Memory.ShiftType);
2135 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2136 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2137 Inst.addOperand(MCOperand::createImm(Val));
2140 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2141 assert(N == 2 && "Invalid number of operands!");
2142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2143 assert(CE && "non-constant AM2OffsetImm operand!");
2144 int32_t Val = CE->getValue();
2145 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2146 // Special case for #-0
2147 if (Val == INT32_MIN) Val = 0;
2148 if (Val < 0) Val = -Val;
2149 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2150 Inst.addOperand(MCOperand::createReg(0));
2151 Inst.addOperand(MCOperand::createImm(Val));
2154 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2155 assert(N == 3 && "Invalid number of operands!");
2156 // If we have an immediate that's not a constant, treat it as a label
2157 // reference needing a fixup. If it is a constant, it's something else
2158 // and we reject it.
2160 Inst.addOperand(MCOperand::createExpr(getImm()));
2161 Inst.addOperand(MCOperand::createReg(0));
2162 Inst.addOperand(MCOperand::createImm(0));
2166 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2167 if (!Memory.OffsetRegNum) {
2168 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2169 // Special case for #-0
2170 if (Val == INT32_MIN) Val = 0;
2171 if (Val < 0) Val = -Val;
2172 Val = ARM_AM::getAM3Opc(AddSub, Val);
2174 // For register offset, we encode the shift type and negation flag
2176 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2178 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2179 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2180 Inst.addOperand(MCOperand::createImm(Val));
2183 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2184 assert(N == 2 && "Invalid number of operands!");
2185 if (Kind == k_PostIndexRegister) {
2187 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2188 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2189 Inst.addOperand(MCOperand::createImm(Val));
2194 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2195 int32_t Val = CE->getValue();
2196 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2197 // Special case for #-0
2198 if (Val == INT32_MIN) Val = 0;
2199 if (Val < 0) Val = -Val;
2200 Val = ARM_AM::getAM3Opc(AddSub, Val);
2201 Inst.addOperand(MCOperand::createReg(0));
2202 Inst.addOperand(MCOperand::createImm(Val));
2205 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2206 assert(N == 2 && "Invalid number of operands!");
2207 // If we have an immediate that's not a constant, treat it as a label
2208 // reference needing a fixup. If it is a constant, it's something else
2209 // and we reject it.
2211 Inst.addOperand(MCOperand::createExpr(getImm()));
2212 Inst.addOperand(MCOperand::createImm(0));
2216 // The lower two bits are always zero and as such are not encoded.
2217 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2218 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2219 // Special case for #-0
2220 if (Val == INT32_MIN) Val = 0;
2221 if (Val < 0) Val = -Val;
2222 Val = ARM_AM::getAM5Opc(AddSub, Val);
2223 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2224 Inst.addOperand(MCOperand::createImm(Val));
2227 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2228 assert(N == 2 && "Invalid number of operands!");
2229 // If we have an immediate that's not a constant, treat it as a label
2230 // reference needing a fixup. If it is a constant, it's something else
2231 // and we reject it.
2233 Inst.addOperand(MCOperand::createExpr(getImm()));
2234 Inst.addOperand(MCOperand::createImm(0));
2238 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2239 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2240 Inst.addOperand(MCOperand::createImm(Val));
2243 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2244 assert(N == 2 && "Invalid number of operands!");
2245 // The lower two bits are always zero and as such are not encoded.
2246 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2247 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2248 Inst.addOperand(MCOperand::createImm(Val));
2251 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2252 assert(N == 2 && "Invalid number of operands!");
2253 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2254 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2255 Inst.addOperand(MCOperand::createImm(Val));
2258 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2259 addMemImm8OffsetOperands(Inst, N);
2262 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2263 addMemImm8OffsetOperands(Inst, N);
2266 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2267 assert(N == 2 && "Invalid number of operands!");
2268 // If this is an immediate, it's a label reference.
2270 addExpr(Inst, getImm());
2271 Inst.addOperand(MCOperand::createImm(0));
2275 // Otherwise, it's a normal memory reg+offset.
2276 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2277 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2278 Inst.addOperand(MCOperand::createImm(Val));
2281 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2282 assert(N == 2 && "Invalid number of operands!");
2283 // If this is an immediate, it's a label reference.
2285 addExpr(Inst, getImm());
2286 Inst.addOperand(MCOperand::createImm(0));
2290 // Otherwise, it's a normal memory reg+offset.
2291 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2292 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2293 Inst.addOperand(MCOperand::createImm(Val));
2296 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2297 assert(N == 2 && "Invalid number of operands!");
2298 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2299 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2302 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2303 assert(N == 2 && "Invalid number of operands!");
2304 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2305 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2308 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2309 assert(N == 3 && "Invalid number of operands!");
2311 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2312 Memory.ShiftImm, Memory.ShiftType);
2313 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2314 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2315 Inst.addOperand(MCOperand::createImm(Val));
2318 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2319 assert(N == 3 && "Invalid number of operands!");
2320 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2321 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2322 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2325 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2326 assert(N == 2 && "Invalid number of operands!");
2327 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2328 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2331 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2332 assert(N == 2 && "Invalid number of operands!");
2333 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2334 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2335 Inst.addOperand(MCOperand::createImm(Val));
2338 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2339 assert(N == 2 && "Invalid number of operands!");
2340 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2341 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2342 Inst.addOperand(MCOperand::createImm(Val));
2345 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2346 assert(N == 2 && "Invalid number of operands!");
2347 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2348 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2349 Inst.addOperand(MCOperand::createImm(Val));
2352 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2353 assert(N == 2 && "Invalid number of operands!");
2354 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2355 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2356 Inst.addOperand(MCOperand::createImm(Val));
2359 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2360 assert(N == 1 && "Invalid number of operands!");
2361 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2362 assert(CE && "non-constant post-idx-imm8 operand!");
2363 int Imm = CE->getValue();
2364 bool isAdd = Imm >= 0;
2365 if (Imm == INT32_MIN) Imm = 0;
2366 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2367 Inst.addOperand(MCOperand::createImm(Imm));
2370 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2371 assert(N == 1 && "Invalid number of operands!");
2372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2373 assert(CE && "non-constant post-idx-imm8s4 operand!");
2374 int Imm = CE->getValue();
2375 bool isAdd = Imm >= 0;
2376 if (Imm == INT32_MIN) Imm = 0;
2377 // Immediate is scaled by 4.
2378 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2379 Inst.addOperand(MCOperand::createImm(Imm));
2382 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2383 assert(N == 2 && "Invalid number of operands!");
2384 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2385 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2388 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2389 assert(N == 2 && "Invalid number of operands!");
2390 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2391 // The sign, shift type, and shift amount are encoded in a single operand
2392 // using the AM2 encoding helpers.
2393 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2394 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2395 PostIdxReg.ShiftTy);
2396 Inst.addOperand(MCOperand::createImm(Imm));
2399 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2400 assert(N == 1 && "Invalid number of operands!");
2401 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2404 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2405 assert(N == 1 && "Invalid number of operands!");
2406 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2409 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2410 assert(N == 1 && "Invalid number of operands!");
2411 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2414 void addVecListOperands(MCInst &Inst, unsigned N) const {
2415 assert(N == 1 && "Invalid number of operands!");
2416 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2419 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2420 assert(N == 2 && "Invalid number of operands!");
2421 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2422 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2425 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2426 assert(N == 1 && "Invalid number of operands!");
2427 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2430 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2431 assert(N == 1 && "Invalid number of operands!");
2432 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2435 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2436 assert(N == 1 && "Invalid number of operands!");
2437 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2440 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2441 assert(N == 1 && "Invalid number of operands!");
2442 // The immediate encodes the type of constant as well as the value.
2443 // Mask in that this is an i8 splat.
2444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2445 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2448 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2449 assert(N == 1 && "Invalid number of operands!");
2450 // The immediate encodes the type of constant as well as the value.
2451 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2452 unsigned Value = CE->getValue();
2453 Value = ARM_AM::encodeNEONi16splat(Value);
2454 Inst.addOperand(MCOperand::createImm(Value));
2457 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2458 assert(N == 1 && "Invalid number of operands!");
2459 // The immediate encodes the type of constant as well as the value.
2460 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2461 unsigned Value = CE->getValue();
2462 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2463 Inst.addOperand(MCOperand::createImm(Value));
2466 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2467 assert(N == 1 && "Invalid number of operands!");
2468 // The immediate encodes the type of constant as well as the value.
2469 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2470 unsigned Value = CE->getValue();
2471 Value = ARM_AM::encodeNEONi32splat(Value);
2472 Inst.addOperand(MCOperand::createImm(Value));
2475 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2476 assert(N == 1 && "Invalid number of operands!");
2477 // The immediate encodes the type of constant as well as the value.
2478 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2479 unsigned Value = CE->getValue();
2480 Value = ARM_AM::encodeNEONi32splat(~Value);
2481 Inst.addOperand(MCOperand::createImm(Value));
2484 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2485 assert(N == 1 && "Invalid number of operands!");
2486 // The immediate encodes the type of constant as well as the value.
2487 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2488 unsigned Value = CE->getValue();
2489 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2490 Inst.getOpcode() == ARM::VMOVv16i8) &&
2491 "All vmvn instructions that wants to replicate non-zero byte "
2492 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2493 unsigned B = ((~Value) & 0xff);
2494 B |= 0xe00; // cmode = 0b1110
2495 Inst.addOperand(MCOperand::createImm(B));
2497 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2498 assert(N == 1 && "Invalid number of operands!");
2499 // The immediate encodes the type of constant as well as the value.
2500 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2501 unsigned Value = CE->getValue();
2502 if (Value >= 256 && Value <= 0xffff)
2503 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2504 else if (Value > 0xffff && Value <= 0xffffff)
2505 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2506 else if (Value > 0xffffff)
2507 Value = (Value >> 24) | 0x600;
2508 Inst.addOperand(MCOperand::createImm(Value));
2511 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2512 assert(N == 1 && "Invalid number of operands!");
2513 // The immediate encodes the type of constant as well as the value.
2514 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2515 unsigned Value = CE->getValue();
2516 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2517 Inst.getOpcode() == ARM::VMOVv16i8) &&
2518 "All instructions that wants to replicate non-zero byte "
2519 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2520 unsigned B = Value & 0xff;
2521 B |= 0xe00; // cmode = 0b1110
2522 Inst.addOperand(MCOperand::createImm(B));
2524 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2525 assert(N == 1 && "Invalid number of operands!");
2526 // The immediate encodes the type of constant as well as the value.
2527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2528 unsigned Value = ~CE->getValue();
2529 if (Value >= 256 && Value <= 0xffff)
2530 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2531 else if (Value > 0xffff && Value <= 0xffffff)
2532 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2533 else if (Value > 0xffffff)
2534 Value = (Value >> 24) | 0x600;
2535 Inst.addOperand(MCOperand::createImm(Value));
2538 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2539 assert(N == 1 && "Invalid number of operands!");
2540 // The immediate encodes the type of constant as well as the value.
2541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2542 uint64_t Value = CE->getValue();
2544 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2545 Imm |= (Value & 1) << i;
2547 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2550 void print(raw_ostream &OS) const override;
2552 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2553 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2554 Op->ITMask.Mask = Mask;
2560 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2562 auto Op = make_unique<ARMOperand>(k_CondCode);
2569 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2570 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2571 Op->Cop.Val = CopVal;
2577 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2578 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2579 Op->Cop.Val = CopVal;
2585 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2587 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2594 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2595 auto Op = make_unique<ARMOperand>(k_CCOut);
2596 Op->Reg.RegNum = RegNum;
2602 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2603 auto Op = make_unique<ARMOperand>(k_Token);
2604 Op->Tok.Data = Str.data();
2605 Op->Tok.Length = Str.size();
2611 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2613 auto Op = make_unique<ARMOperand>(k_Register);
2614 Op->Reg.RegNum = RegNum;
2620 static std::unique_ptr<ARMOperand>
2621 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2622 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2624 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2625 Op->RegShiftedReg.ShiftTy = ShTy;
2626 Op->RegShiftedReg.SrcReg = SrcReg;
2627 Op->RegShiftedReg.ShiftReg = ShiftReg;
2628 Op->RegShiftedReg.ShiftImm = ShiftImm;
2634 static std::unique_ptr<ARMOperand>
2635 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2636 unsigned ShiftImm, SMLoc S, SMLoc E) {
2637 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2638 Op->RegShiftedImm.ShiftTy = ShTy;
2639 Op->RegShiftedImm.SrcReg = SrcReg;
2640 Op->RegShiftedImm.ShiftImm = ShiftImm;
2646 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2648 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2649 Op->ShifterImm.isASR = isASR;
2650 Op->ShifterImm.Imm = Imm;
2656 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2658 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2659 Op->RotImm.Imm = Imm;
2665 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2667 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2668 Op->ModImm.Bits = Bits;
2669 Op->ModImm.Rot = Rot;
2675 static std::unique_ptr<ARMOperand>
2676 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2677 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2678 Op->Bitfield.LSB = LSB;
2679 Op->Bitfield.Width = Width;
2685 static std::unique_ptr<ARMOperand>
2686 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2687 SMLoc StartLoc, SMLoc EndLoc) {
2688 assert (Regs.size() > 0 && "RegList contains no registers?");
2689 KindTy Kind = k_RegisterList;
2691 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2692 Kind = k_DPRRegisterList;
2693 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2694 contains(Regs.front().second))
2695 Kind = k_SPRRegisterList;
2697 // Sort based on the register encoding values.
2698 array_pod_sort(Regs.begin(), Regs.end());
2700 auto Op = make_unique<ARMOperand>(Kind);
2701 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2702 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2703 Op->Registers.push_back(I->second);
2704 Op->StartLoc = StartLoc;
2705 Op->EndLoc = EndLoc;
2709 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2711 bool isDoubleSpaced,
2713 auto Op = make_unique<ARMOperand>(k_VectorList);
2714 Op->VectorList.RegNum = RegNum;
2715 Op->VectorList.Count = Count;
2716 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2722 static std::unique_ptr<ARMOperand>
2723 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2725 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2726 Op->VectorList.RegNum = RegNum;
2727 Op->VectorList.Count = Count;
2728 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2734 static std::unique_ptr<ARMOperand>
2735 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2736 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2737 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2738 Op->VectorList.RegNum = RegNum;
2739 Op->VectorList.Count = Count;
2740 Op->VectorList.LaneIndex = Index;
2741 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2747 static std::unique_ptr<ARMOperand>
2748 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2749 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2750 Op->VectorIndex.Val = Idx;
2756 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2758 auto Op = make_unique<ARMOperand>(k_Immediate);
2765 static std::unique_ptr<ARMOperand>
2766 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2767 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2768 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2769 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2770 auto Op = make_unique<ARMOperand>(k_Memory);
2771 Op->Memory.BaseRegNum = BaseRegNum;
2772 Op->Memory.OffsetImm = OffsetImm;
2773 Op->Memory.OffsetRegNum = OffsetRegNum;
2774 Op->Memory.ShiftType = ShiftType;
2775 Op->Memory.ShiftImm = ShiftImm;
2776 Op->Memory.Alignment = Alignment;
2777 Op->Memory.isNegative = isNegative;
2780 Op->AlignmentLoc = AlignmentLoc;
2784 static std::unique_ptr<ARMOperand>
2785 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2786 unsigned ShiftImm, SMLoc S, SMLoc E) {
2787 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2788 Op->PostIdxReg.RegNum = RegNum;
2789 Op->PostIdxReg.isAdd = isAdd;
2790 Op->PostIdxReg.ShiftTy = ShiftTy;
2791 Op->PostIdxReg.ShiftImm = ShiftImm;
2797 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2799 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2800 Op->MBOpt.Val = Opt;
2806 static std::unique_ptr<ARMOperand>
2807 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2808 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2809 Op->ISBOpt.Val = Opt;
2815 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2817 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2818 Op->IFlags.Val = IFlags;
2824 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2825 auto Op = make_unique<ARMOperand>(k_MSRMask);
2826 Op->MMask.Val = MMask;
2832 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2833 auto Op = make_unique<ARMOperand>(k_BankedReg);
2834 Op->BankedReg.Val = Reg;
2841 } // end anonymous namespace.
2843 void ARMOperand::print(raw_ostream &OS) const {
2846 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2849 OS << "<ccout " << getReg() << ">";
2851 case k_ITCondMask: {
2852 static const char *const MaskStr[] = {
2853 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2854 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2856 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2857 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2861 OS << "<coprocessor number: " << getCoproc() << ">";
2864 OS << "<coprocessor register: " << getCoproc() << ">";
2866 case k_CoprocOption:
2867 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2870 OS << "<mask: " << getMSRMask() << ">";
2873 OS << "<banked reg: " << getBankedReg() << ">";
2878 case k_MemBarrierOpt:
2879 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2881 case k_InstSyncBarrierOpt:
2882 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2886 << " base:" << Memory.BaseRegNum;
2889 case k_PostIndexRegister:
2890 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2891 << PostIdxReg.RegNum;
2892 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2893 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2894 << PostIdxReg.ShiftImm;
2897 case k_ProcIFlags: {
2898 OS << "<ARM_PROC::";
2899 unsigned IFlags = getProcIFlags();
2900 for (int i=2; i >= 0; --i)
2901 if (IFlags & (1 << i))
2902 OS << ARM_PROC::IFlagsToString(1 << i);
2907 OS << "<register " << getReg() << ">";
2909 case k_ShifterImmediate:
2910 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2911 << " #" << ShifterImm.Imm << ">";
2913 case k_ShiftedRegister:
2914 OS << "<so_reg_reg "
2915 << RegShiftedReg.SrcReg << " "
2916 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2917 << " " << RegShiftedReg.ShiftReg << ">";
2919 case k_ShiftedImmediate:
2920 OS << "<so_reg_imm "
2921 << RegShiftedImm.SrcReg << " "
2922 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2923 << " #" << RegShiftedImm.ShiftImm << ">";
2925 case k_RotateImmediate:
2926 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2928 case k_ModifiedImmediate:
2929 OS << "<mod_imm #" << ModImm.Bits << ", #"
2930 << ModImm.Rot << ")>";
2932 case k_BitfieldDescriptor:
2933 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2934 << ", width: " << Bitfield.Width << ">";
2936 case k_RegisterList:
2937 case k_DPRRegisterList:
2938 case k_SPRRegisterList: {
2939 OS << "<register_list ";
2941 const SmallVectorImpl<unsigned> &RegList = getRegList();
2942 for (SmallVectorImpl<unsigned>::const_iterator
2943 I = RegList.begin(), E = RegList.end(); I != E; ) {
2945 if (++I < E) OS << ", ";
2952 OS << "<vector_list " << VectorList.Count << " * "
2953 << VectorList.RegNum << ">";
2955 case k_VectorListAllLanes:
2956 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2957 << VectorList.RegNum << ">";
2959 case k_VectorListIndexed:
2960 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2961 << VectorList.Count << " * " << VectorList.RegNum << ">";
2964 OS << "'" << getToken() << "'";
2967 OS << "<vectorindex " << getVectorIndex() << ">";
2972 /// @name Auto-generated Match Functions
2975 static unsigned MatchRegisterName(StringRef Name);
2979 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2980 SMLoc &StartLoc, SMLoc &EndLoc) {
2981 const AsmToken &Tok = getParser().getTok();
2982 StartLoc = Tok.getLoc();
2983 EndLoc = Tok.getEndLoc();
2984 RegNo = tryParseRegister();
2986 return (RegNo == (unsigned)-1);
2989 /// Try to parse a register name. The token must be an Identifier when called,
2990 /// and if it is a register name the token is eaten and the register number is
2991 /// returned. Otherwise return -1.
2993 int ARMAsmParser::tryParseRegister() {
2994 MCAsmParser &Parser = getParser();
2995 const AsmToken &Tok = Parser.getTok();
2996 if (Tok.isNot(AsmToken::Identifier)) return -1;
2998 std::string lowerCase = Tok.getString().lower();
2999 unsigned RegNum = MatchRegisterName(lowerCase);
3001 RegNum = StringSwitch<unsigned>(lowerCase)
3002 .Case("r13", ARM::SP)
3003 .Case("r14", ARM::LR)
3004 .Case("r15", ARM::PC)
3005 .Case("ip", ARM::R12)
3006 // Additional register name aliases for 'gas' compatibility.
3007 .Case("a1", ARM::R0)
3008 .Case("a2", ARM::R1)
3009 .Case("a3", ARM::R2)
3010 .Case("a4", ARM::R3)
3011 .Case("v1", ARM::R4)
3012 .Case("v2", ARM::R5)
3013 .Case("v3", ARM::R6)
3014 .Case("v4", ARM::R7)
3015 .Case("v5", ARM::R8)
3016 .Case("v6", ARM::R9)
3017 .Case("v7", ARM::R10)
3018 .Case("v8", ARM::R11)
3019 .Case("sb", ARM::R9)
3020 .Case("sl", ARM::R10)
3021 .Case("fp", ARM::R11)
3025 // Check for aliases registered via .req. Canonicalize to lower case.
3026 // That's more consistent since register names are case insensitive, and
3027 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3028 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3029 // If no match, return failure.
3030 if (Entry == RegisterReqs.end())
3032 Parser.Lex(); // Eat identifier token.
3033 return Entry->getValue();
3036 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3037 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3040 Parser.Lex(); // Eat identifier token.
3045 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3046 // If a recoverable error occurs, return 1. If an irrecoverable error
3047 // occurs, return -1. An irrecoverable error is one where tokens have been
3048 // consumed in the process of trying to parse the shifter (i.e., when it is
3049 // indeed a shifter operand, but malformed).
3050 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3051 MCAsmParser &Parser = getParser();
3052 SMLoc S = Parser.getTok().getLoc();
3053 const AsmToken &Tok = Parser.getTok();
3054 if (Tok.isNot(AsmToken::Identifier))
3057 std::string lowerCase = Tok.getString().lower();
3058 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3059 .Case("asl", ARM_AM::lsl)
3060 .Case("lsl", ARM_AM::lsl)
3061 .Case("lsr", ARM_AM::lsr)
3062 .Case("asr", ARM_AM::asr)
3063 .Case("ror", ARM_AM::ror)
3064 .Case("rrx", ARM_AM::rrx)
3065 .Default(ARM_AM::no_shift);
3067 if (ShiftTy == ARM_AM::no_shift)
3070 Parser.Lex(); // Eat the operator.
3072 // The source register for the shift has already been added to the
3073 // operand list, so we need to pop it off and combine it into the shifted
3074 // register operand instead.
3075 std::unique_ptr<ARMOperand> PrevOp(
3076 (ARMOperand *)Operands.pop_back_val().release());
3077 if (!PrevOp->isReg())
3078 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3079 int SrcReg = PrevOp->getReg();
3084 if (ShiftTy == ARM_AM::rrx) {
3085 // RRX Doesn't have an explicit shift amount. The encoder expects
3086 // the shift register to be the same as the source register. Seems odd,
3090 // Figure out if this is shifted by a constant or a register (for non-RRX).
3091 if (Parser.getTok().is(AsmToken::Hash) ||
3092 Parser.getTok().is(AsmToken::Dollar)) {
3093 Parser.Lex(); // Eat hash.
3094 SMLoc ImmLoc = Parser.getTok().getLoc();
3095 const MCExpr *ShiftExpr = nullptr;
3096 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3097 Error(ImmLoc, "invalid immediate shift value");
3100 // The expression must be evaluatable as an immediate.
3101 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3103 Error(ImmLoc, "invalid immediate shift value");
3106 // Range check the immediate.
3107 // lsl, ror: 0 <= imm <= 31
3108 // lsr, asr: 0 <= imm <= 32
3109 Imm = CE->getValue();
3111 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3112 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3113 Error(ImmLoc, "immediate shift value out of range");
3116 // shift by zero is a nop. Always send it through as lsl.
3117 // ('as' compatibility)
3119 ShiftTy = ARM_AM::lsl;
3120 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3121 SMLoc L = Parser.getTok().getLoc();
3122 EndLoc = Parser.getTok().getEndLoc();
3123 ShiftReg = tryParseRegister();
3124 if (ShiftReg == -1) {
3125 Error(L, "expected immediate or register in shift operand");
3129 Error(Parser.getTok().getLoc(),
3130 "expected immediate or register in shift operand");
3135 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3136 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3140 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3147 /// Try to parse a register name. The token must be an Identifier when called.
3148 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3149 /// if there is a "writeback". 'true' if it's not a register.
3151 /// TODO this is likely to change to allow different register types and or to
3152 /// parse for a specific register type.
3153 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3154 MCAsmParser &Parser = getParser();
3155 const AsmToken &RegTok = Parser.getTok();
3156 int RegNo = tryParseRegister();
3160 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3161 RegTok.getEndLoc()));
3163 const AsmToken &ExclaimTok = Parser.getTok();
3164 if (ExclaimTok.is(AsmToken::Exclaim)) {
3165 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3166 ExclaimTok.getLoc()));
3167 Parser.Lex(); // Eat exclaim token
3171 // Also check for an index operand. This is only legal for vector registers,
3172 // but that'll get caught OK in operand matching, so we don't need to
3173 // explicitly filter everything else out here.
3174 if (Parser.getTok().is(AsmToken::LBrac)) {
3175 SMLoc SIdx = Parser.getTok().getLoc();
3176 Parser.Lex(); // Eat left bracket token.
3178 const MCExpr *ImmVal;
3179 if (getParser().parseExpression(ImmVal))
3181 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3183 return TokError("immediate value expected for vector index");
3185 if (Parser.getTok().isNot(AsmToken::RBrac))
3186 return Error(Parser.getTok().getLoc(), "']' expected");
3188 SMLoc E = Parser.getTok().getEndLoc();
3189 Parser.Lex(); // Eat right bracket token.
3191 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3199 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3200 /// instruction with a symbolic operand name.
3201 /// We accept "crN" syntax for GAS compatibility.
3202 /// <operand-name> ::= <prefix><number>
3203 /// If CoprocOp is 'c', then:
3204 /// <prefix> ::= c | cr
3205 /// If CoprocOp is 'p', then :
3207 /// <number> ::= integer in range [0, 15]
3208 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3209 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3211 if (Name.size() < 2 || Name[0] != CoprocOp)
3213 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3215 switch (Name.size()) {
3236 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3237 // However, old cores (v5/v6) did use them in that way.
3238 case '0': return 10;
3239 case '1': return 11;
3240 case '2': return 12;
3241 case '3': return 13;
3242 case '4': return 14;
3243 case '5': return 15;
3248 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3249 ARMAsmParser::OperandMatchResultTy
3250 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3251 MCAsmParser &Parser = getParser();
3252 SMLoc S = Parser.getTok().getLoc();
3253 const AsmToken &Tok = Parser.getTok();
3254 if (!Tok.is(AsmToken::Identifier))
3255 return MatchOperand_NoMatch;
3256 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3257 .Case("eq", ARMCC::EQ)
3258 .Case("ne", ARMCC::NE)
3259 .Case("hs", ARMCC::HS)
3260 .Case("cs", ARMCC::HS)
3261 .Case("lo", ARMCC::LO)
3262 .Case("cc", ARMCC::LO)
3263 .Case("mi", ARMCC::MI)
3264 .Case("pl", ARMCC::PL)
3265 .Case("vs", ARMCC::VS)
3266 .Case("vc", ARMCC::VC)
3267 .Case("hi", ARMCC::HI)
3268 .Case("ls", ARMCC::LS)
3269 .Case("ge", ARMCC::GE)
3270 .Case("lt", ARMCC::LT)
3271 .Case("gt", ARMCC::GT)
3272 .Case("le", ARMCC::LE)
3273 .Case("al", ARMCC::AL)
3276 return MatchOperand_NoMatch;
3277 Parser.Lex(); // Eat the token.
3279 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3281 return MatchOperand_Success;
3284 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3285 /// token must be an Identifier when called, and if it is a coprocessor
3286 /// number, the token is eaten and the operand is added to the operand list.
3287 ARMAsmParser::OperandMatchResultTy
3288 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3289 MCAsmParser &Parser = getParser();
3290 SMLoc S = Parser.getTok().getLoc();
3291 const AsmToken &Tok = Parser.getTok();
3292 if (Tok.isNot(AsmToken::Identifier))
3293 return MatchOperand_NoMatch;
3295 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3297 return MatchOperand_NoMatch;
3298 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3299 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3300 return MatchOperand_NoMatch;
3302 Parser.Lex(); // Eat identifier token.
3303 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3304 return MatchOperand_Success;
3307 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3308 /// token must be an Identifier when called, and if it is a coprocessor
3309 /// number, the token is eaten and the operand is added to the operand list.
3310 ARMAsmParser::OperandMatchResultTy
3311 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3312 MCAsmParser &Parser = getParser();
3313 SMLoc S = Parser.getTok().getLoc();
3314 const AsmToken &Tok = Parser.getTok();
3315 if (Tok.isNot(AsmToken::Identifier))
3316 return MatchOperand_NoMatch;
3318 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3320 return MatchOperand_NoMatch;
3322 Parser.Lex(); // Eat identifier token.
3323 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3324 return MatchOperand_Success;
3327 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3328 /// coproc_option : '{' imm0_255 '}'
3329 ARMAsmParser::OperandMatchResultTy
3330 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3331 MCAsmParser &Parser = getParser();
3332 SMLoc S = Parser.getTok().getLoc();
3334 // If this isn't a '{', this isn't a coprocessor immediate operand.
3335 if (Parser.getTok().isNot(AsmToken::LCurly))
3336 return MatchOperand_NoMatch;
3337 Parser.Lex(); // Eat the '{'
3340 SMLoc Loc = Parser.getTok().getLoc();
3341 if (getParser().parseExpression(Expr)) {
3342 Error(Loc, "illegal expression");
3343 return MatchOperand_ParseFail;
3345 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3346 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3347 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3348 return MatchOperand_ParseFail;
3350 int Val = CE->getValue();
3352 // Check for and consume the closing '}'
3353 if (Parser.getTok().isNot(AsmToken::RCurly))
3354 return MatchOperand_ParseFail;
3355 SMLoc E = Parser.getTok().getEndLoc();
3356 Parser.Lex(); // Eat the '}'
3358 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3359 return MatchOperand_Success;
3362 // For register list parsing, we need to map from raw GPR register numbering
3363 // to the enumeration values. The enumeration values aren't sorted by
3364 // register number due to our using "sp", "lr" and "pc" as canonical names.
3365 static unsigned getNextRegister(unsigned Reg) {
3366 // If this is a GPR, we need to do it manually, otherwise we can rely
3367 // on the sort ordering of the enumeration since the other reg-classes
3369 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3372 default: llvm_unreachable("Invalid GPR number!");
3373 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3374 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3375 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3376 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3377 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3378 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3379 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3380 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3384 // Return the low-subreg of a given Q register.
3385 static unsigned getDRegFromQReg(unsigned QReg) {
3387 default: llvm_unreachable("expected a Q register!");
3388 case ARM::Q0: return ARM::D0;
3389 case ARM::Q1: return ARM::D2;
3390 case ARM::Q2: return ARM::D4;
3391 case ARM::Q3: return ARM::D6;
3392 case ARM::Q4: return ARM::D8;
3393 case ARM::Q5: return ARM::D10;
3394 case ARM::Q6: return ARM::D12;
3395 case ARM::Q7: return ARM::D14;
3396 case ARM::Q8: return ARM::D16;
3397 case ARM::Q9: return ARM::D18;
3398 case ARM::Q10: return ARM::D20;
3399 case ARM::Q11: return ARM::D22;
3400 case ARM::Q12: return ARM::D24;
3401 case ARM::Q13: return ARM::D26;
3402 case ARM::Q14: return ARM::D28;
3403 case ARM::Q15: return ARM::D30;
3407 /// Parse a register list.
3408 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3409 MCAsmParser &Parser = getParser();
3410 assert(Parser.getTok().is(AsmToken::LCurly) &&
3411 "Token is not a Left Curly Brace");
3412 SMLoc S = Parser.getTok().getLoc();
3413 Parser.Lex(); // Eat '{' token.
3414 SMLoc RegLoc = Parser.getTok().getLoc();
3416 // Check the first register in the list to see what register class
3417 // this is a list of.
3418 int Reg = tryParseRegister();
3420 return Error(RegLoc, "register expected");
3422 // The reglist instructions have at most 16 registers, so reserve
3423 // space for that many.
3425 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3427 // Allow Q regs and just interpret them as the two D sub-registers.
3428 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3429 Reg = getDRegFromQReg(Reg);
3430 EReg = MRI->getEncodingValue(Reg);
3431 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3434 const MCRegisterClass *RC;
3435 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3436 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3437 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3438 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3439 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3440 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3442 return Error(RegLoc, "invalid register in register list");
3444 // Store the register.
3445 EReg = MRI->getEncodingValue(Reg);
3446 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3448 // This starts immediately after the first register token in the list,
3449 // so we can see either a comma or a minus (range separator) as a legal
3451 while (Parser.getTok().is(AsmToken::Comma) ||
3452 Parser.getTok().is(AsmToken::Minus)) {
3453 if (Parser.getTok().is(AsmToken::Minus)) {
3454 Parser.Lex(); // Eat the minus.
3455 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3456 int EndReg = tryParseRegister();
3458 return Error(AfterMinusLoc, "register expected");
3459 // Allow Q regs and just interpret them as the two D sub-registers.
3460 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3461 EndReg = getDRegFromQReg(EndReg) + 1;
3462 // If the register is the same as the start reg, there's nothing
3466 // The register must be in the same register class as the first.
3467 if (!RC->contains(EndReg))
3468 return Error(AfterMinusLoc, "invalid register in register list");
3469 // Ranges must go from low to high.
3470 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3471 return Error(AfterMinusLoc, "bad range in register list");
3473 // Add all the registers in the range to the register list.
3474 while (Reg != EndReg) {
3475 Reg = getNextRegister(Reg);
3476 EReg = MRI->getEncodingValue(Reg);
3477 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3481 Parser.Lex(); // Eat the comma.
3482 RegLoc = Parser.getTok().getLoc();
3484 const AsmToken RegTok = Parser.getTok();
3485 Reg = tryParseRegister();
3487 return Error(RegLoc, "register expected");
3488 // Allow Q regs and just interpret them as the two D sub-registers.
3489 bool isQReg = false;
3490 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3491 Reg = getDRegFromQReg(Reg);
3494 // The register must be in the same register class as the first.
3495 if (!RC->contains(Reg))
3496 return Error(RegLoc, "invalid register in register list");
3497 // List must be monotonically increasing.
3498 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3499 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3500 Warning(RegLoc, "register list not in ascending order");
3502 return Error(RegLoc, "register list not in ascending order");
3504 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3505 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3506 ") in register list");
3509 // VFP register lists must also be contiguous.
3510 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3512 return Error(RegLoc, "non-contiguous register range");
3513 EReg = MRI->getEncodingValue(Reg);
3514 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3516 EReg = MRI->getEncodingValue(++Reg);
3517 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3521 if (Parser.getTok().isNot(AsmToken::RCurly))
3522 return Error(Parser.getTok().getLoc(), "'}' expected");
3523 SMLoc E = Parser.getTok().getEndLoc();
3524 Parser.Lex(); // Eat '}' token.
3526 // Push the register list operand.
3527 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3529 // The ARM system instruction variants for LDM/STM have a '^' token here.
3530 if (Parser.getTok().is(AsmToken::Caret)) {
3531 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3532 Parser.Lex(); // Eat '^' token.
3538 // Helper function to parse the lane index for vector lists.
3539 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3540 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3541 MCAsmParser &Parser = getParser();
3542 Index = 0; // Always return a defined index value.
3543 if (Parser.getTok().is(AsmToken::LBrac)) {
3544 Parser.Lex(); // Eat the '['.
3545 if (Parser.getTok().is(AsmToken::RBrac)) {
3546 // "Dn[]" is the 'all lanes' syntax.
3547 LaneKind = AllLanes;
3548 EndLoc = Parser.getTok().getEndLoc();
3549 Parser.Lex(); // Eat the ']'.
3550 return MatchOperand_Success;
3553 // There's an optional '#' token here. Normally there wouldn't be, but
3554 // inline assemble puts one in, and it's friendly to accept that.
3555 if (Parser.getTok().is(AsmToken::Hash))
3556 Parser.Lex(); // Eat '#' or '$'.
3558 const MCExpr *LaneIndex;
3559 SMLoc Loc = Parser.getTok().getLoc();
3560 if (getParser().parseExpression(LaneIndex)) {
3561 Error(Loc, "illegal expression");
3562 return MatchOperand_ParseFail;
3564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3566 Error(Loc, "lane index must be empty or an integer");
3567 return MatchOperand_ParseFail;
3569 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3570 Error(Parser.getTok().getLoc(), "']' expected");
3571 return MatchOperand_ParseFail;
3573 EndLoc = Parser.getTok().getEndLoc();
3574 Parser.Lex(); // Eat the ']'.
3575 int64_t Val = CE->getValue();
3577 // FIXME: Make this range check context sensitive for .8, .16, .32.
3578 if (Val < 0 || Val > 7) {
3579 Error(Parser.getTok().getLoc(), "lane index out of range");
3580 return MatchOperand_ParseFail;
3583 LaneKind = IndexedLane;
3584 return MatchOperand_Success;
3587 return MatchOperand_Success;
3590 // parse a vector register list
3591 ARMAsmParser::OperandMatchResultTy
3592 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3593 MCAsmParser &Parser = getParser();
3594 VectorLaneTy LaneKind;
3596 SMLoc S = Parser.getTok().getLoc();
3597 // As an extension (to match gas), support a plain D register or Q register
3598 // (without encosing curly braces) as a single or double entry list,
3600 if (Parser.getTok().is(AsmToken::Identifier)) {
3601 SMLoc E = Parser.getTok().getEndLoc();
3602 int Reg = tryParseRegister();
3604 return MatchOperand_NoMatch;
3605 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3606 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3607 if (Res != MatchOperand_Success)
3611 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3614 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3618 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3623 return MatchOperand_Success;
3625 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3626 Reg = getDRegFromQReg(Reg);
3627 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3628 if (Res != MatchOperand_Success)
3632 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3633 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3634 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3637 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3638 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3639 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3643 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3648 return MatchOperand_Success;
3650 Error(S, "vector register expected");
3651 return MatchOperand_ParseFail;
3654 if (Parser.getTok().isNot(AsmToken::LCurly))
3655 return MatchOperand_NoMatch;
3657 Parser.Lex(); // Eat '{' token.
3658 SMLoc RegLoc = Parser.getTok().getLoc();
3660 int Reg = tryParseRegister();
3662 Error(RegLoc, "register expected");
3663 return MatchOperand_ParseFail;
3667 unsigned FirstReg = Reg;
3668 // The list is of D registers, but we also allow Q regs and just interpret
3669 // them as the two D sub-registers.
3670 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3671 FirstReg = Reg = getDRegFromQReg(Reg);
3672 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3673 // it's ambiguous with four-register single spaced.
3679 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3680 return MatchOperand_ParseFail;
3682 while (Parser.getTok().is(AsmToken::Comma) ||
3683 Parser.getTok().is(AsmToken::Minus)) {
3684 if (Parser.getTok().is(AsmToken::Minus)) {
3686 Spacing = 1; // Register range implies a single spaced list.
3687 else if (Spacing == 2) {
3688 Error(Parser.getTok().getLoc(),
3689 "sequential registers in double spaced list");
3690 return MatchOperand_ParseFail;
3692 Parser.Lex(); // Eat the minus.
3693 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3694 int EndReg = tryParseRegister();
3696 Error(AfterMinusLoc, "register expected");
3697 return MatchOperand_ParseFail;
3699 // Allow Q regs and just interpret them as the two D sub-registers.
3700 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3701 EndReg = getDRegFromQReg(EndReg) + 1;
3702 // If the register is the same as the start reg, there's nothing
3706 // The register must be in the same register class as the first.
3707 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3708 Error(AfterMinusLoc, "invalid register in register list");
3709 return MatchOperand_ParseFail;
3711 // Ranges must go from low to high.
3713 Error(AfterMinusLoc, "bad range in register list");
3714 return MatchOperand_ParseFail;
3716 // Parse the lane specifier if present.
3717 VectorLaneTy NextLaneKind;
3718 unsigned NextLaneIndex;
3719 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3720 MatchOperand_Success)
3721 return MatchOperand_ParseFail;
3722 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3723 Error(AfterMinusLoc, "mismatched lane index in register list");
3724 return MatchOperand_ParseFail;
3727 // Add all the registers in the range to the register list.
3728 Count += EndReg - Reg;
3732 Parser.Lex(); // Eat the comma.
3733 RegLoc = Parser.getTok().getLoc();
3735 Reg = tryParseRegister();
3737 Error(RegLoc, "register expected");
3738 return MatchOperand_ParseFail;
3740 // vector register lists must be contiguous.
3741 // It's OK to use the enumeration values directly here rather, as the
3742 // VFP register classes have the enum sorted properly.
3744 // The list is of D registers, but we also allow Q regs and just interpret
3745 // them as the two D sub-registers.
3746 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3748 Spacing = 1; // Register range implies a single spaced list.
3749 else if (Spacing == 2) {
3751 "invalid register in double-spaced list (must be 'D' register')");
3752 return MatchOperand_ParseFail;
3754 Reg = getDRegFromQReg(Reg);
3755 if (Reg != OldReg + 1) {
3756 Error(RegLoc, "non-contiguous register range");
3757 return MatchOperand_ParseFail;
3761 // Parse the lane specifier if present.
3762 VectorLaneTy NextLaneKind;
3763 unsigned NextLaneIndex;
3764 SMLoc LaneLoc = Parser.getTok().getLoc();
3765 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3766 MatchOperand_Success)
3767 return MatchOperand_ParseFail;
3768 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3769 Error(LaneLoc, "mismatched lane index in register list");
3770 return MatchOperand_ParseFail;
3774 // Normal D register.
3775 // Figure out the register spacing (single or double) of the list if
3776 // we don't know it already.
3778 Spacing = 1 + (Reg == OldReg + 2);
3780 // Just check that it's contiguous and keep going.
3781 if (Reg != OldReg + Spacing) {
3782 Error(RegLoc, "non-contiguous register range");
3783 return MatchOperand_ParseFail;
3786 // Parse the lane specifier if present.
3787 VectorLaneTy NextLaneKind;
3788 unsigned NextLaneIndex;
3789 SMLoc EndLoc = Parser.getTok().getLoc();
3790 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3791 return MatchOperand_ParseFail;
3792 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3793 Error(EndLoc, "mismatched lane index in register list");
3794 return MatchOperand_ParseFail;
3798 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3799 Error(Parser.getTok().getLoc(), "'}' expected");
3800 return MatchOperand_ParseFail;
3802 E = Parser.getTok().getEndLoc();
3803 Parser.Lex(); // Eat '}' token.
3807 // Two-register operands have been converted to the
3808 // composite register classes.
3810 const MCRegisterClass *RC = (Spacing == 1) ?
3811 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3812 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3813 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3816 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3817 (Spacing == 2), S, E));
3820 // Two-register operands have been converted to the
3821 // composite register classes.
3823 const MCRegisterClass *RC = (Spacing == 1) ?
3824 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3825 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3826 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3828 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3833 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3839 return MatchOperand_Success;
3842 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3843 ARMAsmParser::OperandMatchResultTy
3844 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3845 MCAsmParser &Parser = getParser();
3846 SMLoc S = Parser.getTok().getLoc();
3847 const AsmToken &Tok = Parser.getTok();
3850 if (Tok.is(AsmToken::Identifier)) {
3851 StringRef OptStr = Tok.getString();
3853 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3854 .Case("sy", ARM_MB::SY)
3855 .Case("st", ARM_MB::ST)
3856 .Case("ld", ARM_MB::LD)
3857 .Case("sh", ARM_MB::ISH)
3858 .Case("ish", ARM_MB::ISH)
3859 .Case("shst", ARM_MB::ISHST)
3860 .Case("ishst", ARM_MB::ISHST)
3861 .Case("ishld", ARM_MB::ISHLD)
3862 .Case("nsh", ARM_MB::NSH)
3863 .Case("un", ARM_MB::NSH)
3864 .Case("nshst", ARM_MB::NSHST)
3865 .Case("nshld", ARM_MB::NSHLD)
3866 .Case("unst", ARM_MB::NSHST)
3867 .Case("osh", ARM_MB::OSH)
3868 .Case("oshst", ARM_MB::OSHST)
3869 .Case("oshld", ARM_MB::OSHLD)
3872 // ishld, oshld, nshld and ld are only available from ARMv8.
3873 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3874 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3878 return MatchOperand_NoMatch;
3880 Parser.Lex(); // Eat identifier token.
3881 } else if (Tok.is(AsmToken::Hash) ||
3882 Tok.is(AsmToken::Dollar) ||
3883 Tok.is(AsmToken::Integer)) {
3884 if (Parser.getTok().isNot(AsmToken::Integer))
3885 Parser.Lex(); // Eat '#' or '$'.
3886 SMLoc Loc = Parser.getTok().getLoc();
3888 const MCExpr *MemBarrierID;
3889 if (getParser().parseExpression(MemBarrierID)) {
3890 Error(Loc, "illegal expression");
3891 return MatchOperand_ParseFail;
3894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3896 Error(Loc, "constant expression expected");
3897 return MatchOperand_ParseFail;
3900 int Val = CE->getValue();
3902 Error(Loc, "immediate value out of range");
3903 return MatchOperand_ParseFail;
3906 Opt = ARM_MB::RESERVED_0 + Val;
3908 return MatchOperand_ParseFail;
3910 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3911 return MatchOperand_Success;
3914 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3915 ARMAsmParser::OperandMatchResultTy
3916 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3917 MCAsmParser &Parser = getParser();
3918 SMLoc S = Parser.getTok().getLoc();
3919 const AsmToken &Tok = Parser.getTok();
3922 if (Tok.is(AsmToken::Identifier)) {
3923 StringRef OptStr = Tok.getString();
3925 if (OptStr.equals_lower("sy"))
3928 return MatchOperand_NoMatch;
3930 Parser.Lex(); // Eat identifier token.
3931 } else if (Tok.is(AsmToken::Hash) ||
3932 Tok.is(AsmToken::Dollar) ||
3933 Tok.is(AsmToken::Integer)) {
3934 if (Parser.getTok().isNot(AsmToken::Integer))
3935 Parser.Lex(); // Eat '#' or '$'.
3936 SMLoc Loc = Parser.getTok().getLoc();
3938 const MCExpr *ISBarrierID;
3939 if (getParser().parseExpression(ISBarrierID)) {
3940 Error(Loc, "illegal expression");
3941 return MatchOperand_ParseFail;
3944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3946 Error(Loc, "constant expression expected");
3947 return MatchOperand_ParseFail;
3950 int Val = CE->getValue();
3952 Error(Loc, "immediate value out of range");
3953 return MatchOperand_ParseFail;
3956 Opt = ARM_ISB::RESERVED_0 + Val;
3958 return MatchOperand_ParseFail;
3960 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3961 (ARM_ISB::InstSyncBOpt)Opt, S));
3962 return MatchOperand_Success;
3966 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3967 ARMAsmParser::OperandMatchResultTy
3968 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3969 MCAsmParser &Parser = getParser();
3970 SMLoc S = Parser.getTok().getLoc();
3971 const AsmToken &Tok = Parser.getTok();
3972 if (!Tok.is(AsmToken::Identifier))
3973 return MatchOperand_NoMatch;
3974 StringRef IFlagsStr = Tok.getString();
3976 // An iflags string of "none" is interpreted to mean that none of the AIF
3977 // bits are set. Not a terribly useful instruction, but a valid encoding.
3978 unsigned IFlags = 0;
3979 if (IFlagsStr != "none") {
3980 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3981 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3982 .Case("a", ARM_PROC::A)
3983 .Case("i", ARM_PROC::I)
3984 .Case("f", ARM_PROC::F)
3987 // If some specific iflag is already set, it means that some letter is
3988 // present more than once, this is not acceptable.
3989 if (Flag == ~0U || (IFlags & Flag))
3990 return MatchOperand_NoMatch;
3996 Parser.Lex(); // Eat identifier token.
3997 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3998 return MatchOperand_Success;
4001 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4002 ARMAsmParser::OperandMatchResultTy
4003 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4004 MCAsmParser &Parser = getParser();
4005 SMLoc S = Parser.getTok().getLoc();
4006 const AsmToken &Tok = Parser.getTok();
4007 if (!Tok.is(AsmToken::Identifier))
4008 return MatchOperand_NoMatch;
4009 StringRef Mask = Tok.getString();
4012 // See ARMv6-M 10.1.1
4013 std::string Name = Mask.lower();
4014 unsigned FlagsVal = StringSwitch<unsigned>(Name)
4015 // Note: in the documentation:
4016 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4017 // for MSR APSR_nzcvq.
4018 // but we do make it an alias here. This is so to get the "mask encoding"
4019 // bits correct on MSR APSR writes.
4021 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4022 // should really only be allowed when writing a special register. Note
4023 // they get dropped in the MRS instruction reading a special register as
4024 // the SYSm field is only 8 bits.
4025 .Case("apsr", 0x800)
4026 .Case("apsr_nzcvq", 0x800)
4027 .Case("apsr_g", 0x400)
4028 .Case("apsr_nzcvqg", 0xc00)
4029 .Case("iapsr", 0x801)
4030 .Case("iapsr_nzcvq", 0x801)
4031 .Case("iapsr_g", 0x401)
4032 .Case("iapsr_nzcvqg", 0xc01)
4033 .Case("eapsr", 0x802)
4034 .Case("eapsr_nzcvq", 0x802)
4035 .Case("eapsr_g", 0x402)
4036 .Case("eapsr_nzcvqg", 0xc02)
4037 .Case("xpsr", 0x803)
4038 .Case("xpsr_nzcvq", 0x803)
4039 .Case("xpsr_g", 0x403)
4040 .Case("xpsr_nzcvqg", 0xc03)
4041 .Case("ipsr", 0x805)
4042 .Case("epsr", 0x806)
4043 .Case("iepsr", 0x807)
4046 .Case("primask", 0x810)
4047 .Case("basepri", 0x811)
4048 .Case("basepri_max", 0x812)
4049 .Case("faultmask", 0x813)
4050 .Case("control", 0x814)
4053 if (FlagsVal == ~0U)
4054 return MatchOperand_NoMatch;
4056 if (!hasThumb2DSP() && (FlagsVal & 0x400))
4057 // The _g and _nzcvqg versions are only valid if the DSP extension is
4059 return MatchOperand_NoMatch;
4061 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4062 // basepri, basepri_max and faultmask only valid for V7m.
4063 return MatchOperand_NoMatch;
4065 Parser.Lex(); // Eat identifier token.
4066 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4067 return MatchOperand_Success;
4070 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4071 size_t Start = 0, Next = Mask.find('_');
4072 StringRef Flags = "";
4073 std::string SpecReg = Mask.slice(Start, Next).lower();
4074 if (Next != StringRef::npos)
4075 Flags = Mask.slice(Next+1, Mask.size());
4077 // FlagsVal contains the complete mask:
4079 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4080 unsigned FlagsVal = 0;
4082 if (SpecReg == "apsr") {
4083 FlagsVal = StringSwitch<unsigned>(Flags)
4084 .Case("nzcvq", 0x8) // same as CPSR_f
4085 .Case("g", 0x4) // same as CPSR_s
4086 .Case("nzcvqg", 0xc) // same as CPSR_fs
4089 if (FlagsVal == ~0U) {
4091 return MatchOperand_NoMatch;
4093 FlagsVal = 8; // No flag
4095 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4096 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4097 if (Flags == "all" || Flags == "")
4099 for (int i = 0, e = Flags.size(); i != e; ++i) {
4100 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4107 // If some specific flag is already set, it means that some letter is
4108 // present more than once, this is not acceptable.
4109 if (FlagsVal == ~0U || (FlagsVal & Flag))
4110 return MatchOperand_NoMatch;
4113 } else // No match for special register.
4114 return MatchOperand_NoMatch;
4116 // Special register without flags is NOT equivalent to "fc" flags.
4117 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4118 // two lines would enable gas compatibility at the expense of breaking
4124 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4125 if (SpecReg == "spsr")
4128 Parser.Lex(); // Eat identifier token.
4129 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4130 return MatchOperand_Success;
4133 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4134 /// use in the MRS/MSR instructions added to support virtualization.
4135 ARMAsmParser::OperandMatchResultTy
4136 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4137 MCAsmParser &Parser = getParser();
4138 SMLoc S = Parser.getTok().getLoc();
4139 const AsmToken &Tok = Parser.getTok();
4140 if (!Tok.is(AsmToken::Identifier))
4141 return MatchOperand_NoMatch;
4142 StringRef RegName = Tok.getString();
4144 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4146 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4147 .Case("r8_usr", 0x00)
4148 .Case("r9_usr", 0x01)
4149 .Case("r10_usr", 0x02)
4150 .Case("r11_usr", 0x03)
4151 .Case("r12_usr", 0x04)
4152 .Case("sp_usr", 0x05)
4153 .Case("lr_usr", 0x06)
4154 .Case("r8_fiq", 0x08)
4155 .Case("r9_fiq", 0x09)
4156 .Case("r10_fiq", 0x0a)
4157 .Case("r11_fiq", 0x0b)
4158 .Case("r12_fiq", 0x0c)
4159 .Case("sp_fiq", 0x0d)
4160 .Case("lr_fiq", 0x0e)
4161 .Case("lr_irq", 0x10)
4162 .Case("sp_irq", 0x11)
4163 .Case("lr_svc", 0x12)
4164 .Case("sp_svc", 0x13)
4165 .Case("lr_abt", 0x14)
4166 .Case("sp_abt", 0x15)
4167 .Case("lr_und", 0x16)
4168 .Case("sp_und", 0x17)
4169 .Case("lr_mon", 0x1c)
4170 .Case("sp_mon", 0x1d)
4171 .Case("elr_hyp", 0x1e)
4172 .Case("sp_hyp", 0x1f)
4173 .Case("spsr_fiq", 0x2e)
4174 .Case("spsr_irq", 0x30)
4175 .Case("spsr_svc", 0x32)
4176 .Case("spsr_abt", 0x34)
4177 .Case("spsr_und", 0x36)
4178 .Case("spsr_mon", 0x3c)
4179 .Case("spsr_hyp", 0x3e)
4182 if (Encoding == ~0U)
4183 return MatchOperand_NoMatch;
4185 Parser.Lex(); // Eat identifier token.
4186 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4187 return MatchOperand_Success;
4190 ARMAsmParser::OperandMatchResultTy
4191 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4193 MCAsmParser &Parser = getParser();
4194 const AsmToken &Tok = Parser.getTok();
4195 if (Tok.isNot(AsmToken::Identifier)) {
4196 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4197 return MatchOperand_ParseFail;
4199 StringRef ShiftName = Tok.getString();
4200 std::string LowerOp = Op.lower();
4201 std::string UpperOp = Op.upper();
4202 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4203 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4204 return MatchOperand_ParseFail;
4206 Parser.Lex(); // Eat shift type token.
4208 // There must be a '#' and a shift amount.
4209 if (Parser.getTok().isNot(AsmToken::Hash) &&
4210 Parser.getTok().isNot(AsmToken::Dollar)) {
4211 Error(Parser.getTok().getLoc(), "'#' expected");
4212 return MatchOperand_ParseFail;
4214 Parser.Lex(); // Eat hash token.
4216 const MCExpr *ShiftAmount;
4217 SMLoc Loc = Parser.getTok().getLoc();
4219 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4220 Error(Loc, "illegal expression");
4221 return MatchOperand_ParseFail;
4223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4225 Error(Loc, "constant expression expected");
4226 return MatchOperand_ParseFail;
4228 int Val = CE->getValue();
4229 if (Val < Low || Val > High) {
4230 Error(Loc, "immediate value out of range");
4231 return MatchOperand_ParseFail;
4234 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4236 return MatchOperand_Success;
4239 ARMAsmParser::OperandMatchResultTy
4240 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4241 MCAsmParser &Parser = getParser();
4242 const AsmToken &Tok = Parser.getTok();
4243 SMLoc S = Tok.getLoc();
4244 if (Tok.isNot(AsmToken::Identifier)) {
4245 Error(S, "'be' or 'le' operand expected");
4246 return MatchOperand_ParseFail;
4248 int Val = StringSwitch<int>(Tok.getString().lower())
4252 Parser.Lex(); // Eat the token.
4255 Error(S, "'be' or 'le' operand expected");
4256 return MatchOperand_ParseFail;
4258 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4260 S, Tok.getEndLoc()));
4261 return MatchOperand_Success;
4264 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4265 /// instructions. Legal values are:
4266 /// lsl #n 'n' in [0,31]
4267 /// asr #n 'n' in [1,32]
4268 /// n == 32 encoded as n == 0.
4269 ARMAsmParser::OperandMatchResultTy
4270 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4271 MCAsmParser &Parser = getParser();
4272 const AsmToken &Tok = Parser.getTok();
4273 SMLoc S = Tok.getLoc();
4274 if (Tok.isNot(AsmToken::Identifier)) {
4275 Error(S, "shift operator 'asr' or 'lsl' expected");
4276 return MatchOperand_ParseFail;
4278 StringRef ShiftName = Tok.getString();
4280 if (ShiftName == "lsl" || ShiftName == "LSL")
4282 else if (ShiftName == "asr" || ShiftName == "ASR")
4285 Error(S, "shift operator 'asr' or 'lsl' expected");
4286 return MatchOperand_ParseFail;
4288 Parser.Lex(); // Eat the operator.
4290 // A '#' and a shift amount.
4291 if (Parser.getTok().isNot(AsmToken::Hash) &&
4292 Parser.getTok().isNot(AsmToken::Dollar)) {
4293 Error(Parser.getTok().getLoc(), "'#' expected");
4294 return MatchOperand_ParseFail;
4296 Parser.Lex(); // Eat hash token.
4297 SMLoc ExLoc = Parser.getTok().getLoc();
4299 const MCExpr *ShiftAmount;
4301 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4302 Error(ExLoc, "malformed shift expression");
4303 return MatchOperand_ParseFail;
4305 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4307 Error(ExLoc, "shift amount must be an immediate");
4308 return MatchOperand_ParseFail;
4311 int64_t Val = CE->getValue();
4313 // Shift amount must be in [1,32]
4314 if (Val < 1 || Val > 32) {
4315 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4316 return MatchOperand_ParseFail;
4318 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4319 if (isThumb() && Val == 32) {
4320 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4321 return MatchOperand_ParseFail;
4323 if (Val == 32) Val = 0;
4325 // Shift amount must be in [1,32]
4326 if (Val < 0 || Val > 31) {
4327 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4328 return MatchOperand_ParseFail;
4332 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4334 return MatchOperand_Success;
4337 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4338 /// of instructions. Legal values are:
4339 /// ror #n 'n' in {0, 8, 16, 24}
4340 ARMAsmParser::OperandMatchResultTy
4341 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4342 MCAsmParser &Parser = getParser();
4343 const AsmToken &Tok = Parser.getTok();
4344 SMLoc S = Tok.getLoc();
4345 if (Tok.isNot(AsmToken::Identifier))
4346 return MatchOperand_NoMatch;
4347 StringRef ShiftName = Tok.getString();
4348 if (ShiftName != "ror" && ShiftName != "ROR")
4349 return MatchOperand_NoMatch;
4350 Parser.Lex(); // Eat the operator.
4352 // A '#' and a rotate amount.
4353 if (Parser.getTok().isNot(AsmToken::Hash) &&
4354 Parser.getTok().isNot(AsmToken::Dollar)) {
4355 Error(Parser.getTok().getLoc(), "'#' expected");
4356 return MatchOperand_ParseFail;
4358 Parser.Lex(); // Eat hash token.
4359 SMLoc ExLoc = Parser.getTok().getLoc();
4361 const MCExpr *ShiftAmount;
4363 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4364 Error(ExLoc, "malformed rotate expression");
4365 return MatchOperand_ParseFail;
4367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4369 Error(ExLoc, "rotate amount must be an immediate");
4370 return MatchOperand_ParseFail;
4373 int64_t Val = CE->getValue();
4374 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4375 // normally, zero is represented in asm by omitting the rotate operand
4377 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4378 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4379 return MatchOperand_ParseFail;
4382 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4384 return MatchOperand_Success;
4387 ARMAsmParser::OperandMatchResultTy
4388 ARMAsmParser::parseModImm(OperandVector &Operands) {
4389 MCAsmParser &Parser = getParser();
4390 MCAsmLexer &Lexer = getLexer();
4393 SMLoc S = Parser.getTok().getLoc();
4395 // 1) A mod_imm operand can appear in the place of a register name:
4397 // add r0, r0, #mod_imm
4398 // to correctly handle the latter, we bail out as soon as we see an
4401 // 2) Similarly, we do not want to parse into complex operands:
4403 // mov r0, :lower16:(_foo)
4404 if (Parser.getTok().is(AsmToken::Identifier) ||
4405 Parser.getTok().is(AsmToken::Colon))
4406 return MatchOperand_NoMatch;
4408 // Hash (dollar) is optional as per the ARMARM
4409 if (Parser.getTok().is(AsmToken::Hash) ||
4410 Parser.getTok().is(AsmToken::Dollar)) {
4411 // Avoid parsing into complex operands (#:)
4412 if (Lexer.peekTok().is(AsmToken::Colon))
4413 return MatchOperand_NoMatch;
4415 // Eat the hash (dollar)
4420 Sx1 = Parser.getTok().getLoc();
4421 const MCExpr *Imm1Exp;
4422 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4423 Error(Sx1, "malformed expression");
4424 return MatchOperand_ParseFail;
4427 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4430 // Immediate must fit within 32-bits
4431 Imm1 = CE->getValue();
4432 int Enc = ARM_AM::getSOImmVal(Imm1);
4433 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4435 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4438 return MatchOperand_Success;
4441 // We have parsed an immediate which is not for us, fallback to a plain
4442 // immediate. This can happen for instruction aliases. For an example,
4443 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4444 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4445 // instruction with a mod_imm operand. The alias is defined such that the
4446 // parser method is shared, that's why we have to do this here.
4447 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4448 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4449 return MatchOperand_Success;
4452 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4453 // MCFixup). Fallback to a plain immediate.
4454 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4455 return MatchOperand_Success;
4458 // From this point onward, we expect the input to be a (#bits, #rot) pair
4459 if (Parser.getTok().isNot(AsmToken::Comma)) {
4460 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4461 return MatchOperand_ParseFail;
4465 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4466 return MatchOperand_ParseFail;
4474 Sx2 = Parser.getTok().getLoc();
4476 // Eat the optional hash (dollar)
4477 if (Parser.getTok().is(AsmToken::Hash) ||
4478 Parser.getTok().is(AsmToken::Dollar))
4481 const MCExpr *Imm2Exp;
4482 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4483 Error(Sx2, "malformed expression");
4484 return MatchOperand_ParseFail;
4487 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4490 Imm2 = CE->getValue();
4491 if (!(Imm2 & ~0x1E)) {
4493 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4494 return MatchOperand_Success;
4496 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4497 return MatchOperand_ParseFail;
4499 Error(Sx2, "constant expression expected");
4500 return MatchOperand_ParseFail;
4504 ARMAsmParser::OperandMatchResultTy
4505 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4506 MCAsmParser &Parser = getParser();
4507 SMLoc S = Parser.getTok().getLoc();
4508 // The bitfield descriptor is really two operands, the LSB and the width.
4509 if (Parser.getTok().isNot(AsmToken::Hash) &&
4510 Parser.getTok().isNot(AsmToken::Dollar)) {
4511 Error(Parser.getTok().getLoc(), "'#' expected");
4512 return MatchOperand_ParseFail;
4514 Parser.Lex(); // Eat hash token.
4516 const MCExpr *LSBExpr;
4517 SMLoc E = Parser.getTok().getLoc();
4518 if (getParser().parseExpression(LSBExpr)) {
4519 Error(E, "malformed immediate expression");
4520 return MatchOperand_ParseFail;
4522 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4524 Error(E, "'lsb' operand must be an immediate");
4525 return MatchOperand_ParseFail;
4528 int64_t LSB = CE->getValue();
4529 // The LSB must be in the range [0,31]
4530 if (LSB < 0 || LSB > 31) {
4531 Error(E, "'lsb' operand must be in the range [0,31]");
4532 return MatchOperand_ParseFail;
4534 E = Parser.getTok().getLoc();
4536 // Expect another immediate operand.
4537 if (Parser.getTok().isNot(AsmToken::Comma)) {
4538 Error(Parser.getTok().getLoc(), "too few operands");
4539 return MatchOperand_ParseFail;
4541 Parser.Lex(); // Eat hash token.
4542 if (Parser.getTok().isNot(AsmToken::Hash) &&
4543 Parser.getTok().isNot(AsmToken::Dollar)) {
4544 Error(Parser.getTok().getLoc(), "'#' expected");
4545 return MatchOperand_ParseFail;
4547 Parser.Lex(); // Eat hash token.
4549 const MCExpr *WidthExpr;
4551 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4552 Error(E, "malformed immediate expression");
4553 return MatchOperand_ParseFail;
4555 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4557 Error(E, "'width' operand must be an immediate");
4558 return MatchOperand_ParseFail;
4561 int64_t Width = CE->getValue();
4562 // The LSB must be in the range [1,32-lsb]
4563 if (Width < 1 || Width > 32 - LSB) {
4564 Error(E, "'width' operand must be in the range [1,32-lsb]");
4565 return MatchOperand_ParseFail;
4568 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4570 return MatchOperand_Success;
4573 ARMAsmParser::OperandMatchResultTy
4574 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4575 // Check for a post-index addressing register operand. Specifically:
4576 // postidx_reg := '+' register {, shift}
4577 // | '-' register {, shift}
4578 // | register {, shift}
4580 // This method must return MatchOperand_NoMatch without consuming any tokens
4581 // in the case where there is no match, as other alternatives take other
4583 MCAsmParser &Parser = getParser();
4584 AsmToken Tok = Parser.getTok();
4585 SMLoc S = Tok.getLoc();
4586 bool haveEaten = false;
4588 if (Tok.is(AsmToken::Plus)) {
4589 Parser.Lex(); // Eat the '+' token.
4591 } else if (Tok.is(AsmToken::Minus)) {
4592 Parser.Lex(); // Eat the '-' token.
4597 SMLoc E = Parser.getTok().getEndLoc();
4598 int Reg = tryParseRegister();
4601 return MatchOperand_NoMatch;
4602 Error(Parser.getTok().getLoc(), "register expected");
4603 return MatchOperand_ParseFail;
4606 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4607 unsigned ShiftImm = 0;
4608 if (Parser.getTok().is(AsmToken::Comma)) {
4609 Parser.Lex(); // Eat the ','.
4610 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4611 return MatchOperand_ParseFail;
4613 // FIXME: Only approximates end...may include intervening whitespace.
4614 E = Parser.getTok().getLoc();
4617 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4620 return MatchOperand_Success;
4623 ARMAsmParser::OperandMatchResultTy
4624 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4625 // Check for a post-index addressing register operand. Specifically:
4626 // am3offset := '+' register
4633 // This method must return MatchOperand_NoMatch without consuming any tokens
4634 // in the case where there is no match, as other alternatives take other
4636 MCAsmParser &Parser = getParser();
4637 AsmToken Tok = Parser.getTok();
4638 SMLoc S = Tok.getLoc();
4640 // Do immediates first, as we always parse those if we have a '#'.
4641 if (Parser.getTok().is(AsmToken::Hash) ||
4642 Parser.getTok().is(AsmToken::Dollar)) {
4643 Parser.Lex(); // Eat '#' or '$'.
4644 // Explicitly look for a '-', as we need to encode negative zero
4646 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4647 const MCExpr *Offset;
4649 if (getParser().parseExpression(Offset, E))
4650 return MatchOperand_ParseFail;
4651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4653 Error(S, "constant expression expected");
4654 return MatchOperand_ParseFail;
4656 // Negative zero is encoded as the flag value INT32_MIN.
4657 int32_t Val = CE->getValue();
4658 if (isNegative && Val == 0)
4662 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4664 return MatchOperand_Success;
4668 bool haveEaten = false;
4670 if (Tok.is(AsmToken::Plus)) {
4671 Parser.Lex(); // Eat the '+' token.
4673 } else if (Tok.is(AsmToken::Minus)) {
4674 Parser.Lex(); // Eat the '-' token.
4679 Tok = Parser.getTok();
4680 int Reg = tryParseRegister();
4683 return MatchOperand_NoMatch;
4684 Error(Tok.getLoc(), "register expected");
4685 return MatchOperand_ParseFail;
4688 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4689 0, S, Tok.getEndLoc()));
4691 return MatchOperand_Success;
4694 /// Convert parsed operands to MCInst. Needed here because this instruction
4695 /// only has two register operands, but multiplication is commutative so
4696 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4697 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4698 const OperandVector &Operands) {
4699 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4700 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4701 // If we have a three-operand form, make sure to set Rn to be the operand
4702 // that isn't the same as Rd.
4704 if (Operands.size() == 6 &&
4705 ((ARMOperand &)*Operands[4]).getReg() ==
4706 ((ARMOperand &)*Operands[3]).getReg())
4708 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4709 Inst.addOperand(Inst.getOperand(0));
4710 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4713 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4714 const OperandVector &Operands) {
4715 int CondOp = -1, ImmOp = -1;
4716 switch(Inst.getOpcode()) {
4718 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4721 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4723 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4725 // first decide whether or not the branch should be conditional
4726 // by looking at it's location relative to an IT block
4728 // inside an IT block we cannot have any conditional branches. any
4729 // such instructions needs to be converted to unconditional form
4730 switch(Inst.getOpcode()) {
4731 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4732 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4735 // outside IT blocks we can only have unconditional branches with AL
4736 // condition code or conditional branches with non-AL condition code
4737 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4738 switch(Inst.getOpcode()) {
4741 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4745 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4750 // now decide on encoding size based on branch target range
4751 switch(Inst.getOpcode()) {
4752 // classify tB as either t2B or t1B based on range of immediate operand
4754 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4755 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4756 Inst.setOpcode(ARM::t2B);
4759 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4761 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4762 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4763 Inst.setOpcode(ARM::t2Bcc);
4767 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4768 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4771 /// Parse an ARM memory expression, return false if successful else return true
4772 /// or an error. The first token must be a '[' when called.
4773 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4774 MCAsmParser &Parser = getParser();
4776 assert(Parser.getTok().is(AsmToken::LBrac) &&
4777 "Token is not a Left Bracket");
4778 S = Parser.getTok().getLoc();
4779 Parser.Lex(); // Eat left bracket token.
4781 const AsmToken &BaseRegTok = Parser.getTok();
4782 int BaseRegNum = tryParseRegister();
4783 if (BaseRegNum == -1)
4784 return Error(BaseRegTok.getLoc(), "register expected");
4786 // The next token must either be a comma, a colon or a closing bracket.
4787 const AsmToken &Tok = Parser.getTok();
4788 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4789 !Tok.is(AsmToken::RBrac))
4790 return Error(Tok.getLoc(), "malformed memory operand");
4792 if (Tok.is(AsmToken::RBrac)) {
4793 E = Tok.getEndLoc();
4794 Parser.Lex(); // Eat right bracket token.
4796 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4797 ARM_AM::no_shift, 0, 0, false,
4800 // If there's a pre-indexing writeback marker, '!', just add it as a token
4801 // operand. It's rather odd, but syntactically valid.
4802 if (Parser.getTok().is(AsmToken::Exclaim)) {
4803 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4804 Parser.Lex(); // Eat the '!'.
4810 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4811 "Lost colon or comma in memory operand?!");
4812 if (Tok.is(AsmToken::Comma)) {
4813 Parser.Lex(); // Eat the comma.
4816 // If we have a ':', it's an alignment specifier.
4817 if (Parser.getTok().is(AsmToken::Colon)) {
4818 Parser.Lex(); // Eat the ':'.
4819 E = Parser.getTok().getLoc();
4820 SMLoc AlignmentLoc = Tok.getLoc();
4823 if (getParser().parseExpression(Expr))
4826 // The expression has to be a constant. Memory references with relocations
4827 // don't come through here, as they use the <label> forms of the relevant
4829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4831 return Error (E, "constant expression expected");
4834 switch (CE->getValue()) {
4837 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4838 case 16: Align = 2; break;
4839 case 32: Align = 4; break;
4840 case 64: Align = 8; break;
4841 case 128: Align = 16; break;
4842 case 256: Align = 32; break;
4845 // Now we should have the closing ']'
4846 if (Parser.getTok().isNot(AsmToken::RBrac))
4847 return Error(Parser.getTok().getLoc(), "']' expected");
4848 E = Parser.getTok().getEndLoc();
4849 Parser.Lex(); // Eat right bracket token.
4851 // Don't worry about range checking the value here. That's handled by
4852 // the is*() predicates.
4853 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4854 ARM_AM::no_shift, 0, Align,
4855 false, S, E, AlignmentLoc));
4857 // If there's a pre-indexing writeback marker, '!', just add it as a token
4859 if (Parser.getTok().is(AsmToken::Exclaim)) {
4860 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4861 Parser.Lex(); // Eat the '!'.
4867 // If we have a '#', it's an immediate offset, else assume it's a register
4868 // offset. Be friendly and also accept a plain integer (without a leading
4869 // hash) for gas compatibility.
4870 if (Parser.getTok().is(AsmToken::Hash) ||
4871 Parser.getTok().is(AsmToken::Dollar) ||
4872 Parser.getTok().is(AsmToken::Integer)) {
4873 if (Parser.getTok().isNot(AsmToken::Integer))
4874 Parser.Lex(); // Eat '#' or '$'.
4875 E = Parser.getTok().getLoc();
4877 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4878 const MCExpr *Offset;
4879 if (getParser().parseExpression(Offset))
4882 // The expression has to be a constant. Memory references with relocations
4883 // don't come through here, as they use the <label> forms of the relevant
4885 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4887 return Error (E, "constant expression expected");
4889 // If the constant was #-0, represent it as INT32_MIN.
4890 int32_t Val = CE->getValue();
4891 if (isNegative && Val == 0)
4892 CE = MCConstantExpr::create(INT32_MIN, getContext());
4894 // Now we should have the closing ']'
4895 if (Parser.getTok().isNot(AsmToken::RBrac))
4896 return Error(Parser.getTok().getLoc(), "']' expected");
4897 E = Parser.getTok().getEndLoc();
4898 Parser.Lex(); // Eat right bracket token.
4900 // Don't worry about range checking the value here. That's handled by
4901 // the is*() predicates.
4902 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4903 ARM_AM::no_shift, 0, 0,
4906 // If there's a pre-indexing writeback marker, '!', just add it as a token
4908 if (Parser.getTok().is(AsmToken::Exclaim)) {
4909 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4910 Parser.Lex(); // Eat the '!'.
4916 // The register offset is optionally preceded by a '+' or '-'
4917 bool isNegative = false;
4918 if (Parser.getTok().is(AsmToken::Minus)) {
4920 Parser.Lex(); // Eat the '-'.
4921 } else if (Parser.getTok().is(AsmToken::Plus)) {
4923 Parser.Lex(); // Eat the '+'.
4926 E = Parser.getTok().getLoc();
4927 int OffsetRegNum = tryParseRegister();
4928 if (OffsetRegNum == -1)
4929 return Error(E, "register expected");
4931 // If there's a shift operator, handle it.
4932 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4933 unsigned ShiftImm = 0;
4934 if (Parser.getTok().is(AsmToken::Comma)) {
4935 Parser.Lex(); // Eat the ','.
4936 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4940 // Now we should have the closing ']'
4941 if (Parser.getTok().isNot(AsmToken::RBrac))
4942 return Error(Parser.getTok().getLoc(), "']' expected");
4943 E = Parser.getTok().getEndLoc();
4944 Parser.Lex(); // Eat right bracket token.
4946 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4947 ShiftType, ShiftImm, 0, isNegative,
4950 // If there's a pre-indexing writeback marker, '!', just add it as a token
4952 if (Parser.getTok().is(AsmToken::Exclaim)) {
4953 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4954 Parser.Lex(); // Eat the '!'.
4960 /// parseMemRegOffsetShift - one of these two:
4961 /// ( lsl | lsr | asr | ror ) , # shift_amount
4963 /// return true if it parses a shift otherwise it returns false.
4964 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4966 MCAsmParser &Parser = getParser();
4967 SMLoc Loc = Parser.getTok().getLoc();
4968 const AsmToken &Tok = Parser.getTok();
4969 if (Tok.isNot(AsmToken::Identifier))
4971 StringRef ShiftName = Tok.getString();
4972 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4973 ShiftName == "asl" || ShiftName == "ASL")
4975 else if (ShiftName == "lsr" || ShiftName == "LSR")
4977 else if (ShiftName == "asr" || ShiftName == "ASR")
4979 else if (ShiftName == "ror" || ShiftName == "ROR")
4981 else if (ShiftName == "rrx" || ShiftName == "RRX")
4984 return Error(Loc, "illegal shift operator");
4985 Parser.Lex(); // Eat shift type token.
4987 // rrx stands alone.
4989 if (St != ARM_AM::rrx) {
4990 Loc = Parser.getTok().getLoc();
4991 // A '#' and a shift amount.
4992 const AsmToken &HashTok = Parser.getTok();
4993 if (HashTok.isNot(AsmToken::Hash) &&
4994 HashTok.isNot(AsmToken::Dollar))
4995 return Error(HashTok.getLoc(), "'#' expected");
4996 Parser.Lex(); // Eat hash token.
4999 if (getParser().parseExpression(Expr))
5001 // Range check the immediate.
5002 // lsl, ror: 0 <= imm <= 31
5003 // lsr, asr: 0 <= imm <= 32
5004 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5006 return Error(Loc, "shift amount must be an immediate");
5007 int64_t Imm = CE->getValue();
5009 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5010 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5011 return Error(Loc, "immediate shift value out of range");
5012 // If <ShiftTy> #0, turn it into a no_shift.
5015 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5024 /// parseFPImm - A floating point immediate expression operand.
5025 ARMAsmParser::OperandMatchResultTy
5026 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5027 MCAsmParser &Parser = getParser();
5028 // Anything that can accept a floating point constant as an operand
5029 // needs to go through here, as the regular parseExpression is
5032 // This routine still creates a generic Immediate operand, containing
5033 // a bitcast of the 64-bit floating point value. The various operands
5034 // that accept floats can check whether the value is valid for them
5035 // via the standard is*() predicates.
5037 SMLoc S = Parser.getTok().getLoc();
5039 if (Parser.getTok().isNot(AsmToken::Hash) &&
5040 Parser.getTok().isNot(AsmToken::Dollar))
5041 return MatchOperand_NoMatch;
5043 // Disambiguate the VMOV forms that can accept an FP immediate.
5044 // vmov.f32 <sreg>, #imm
5045 // vmov.f64 <dreg>, #imm
5046 // vmov.f32 <dreg>, #imm @ vector f32x2
5047 // vmov.f32 <qreg>, #imm @ vector f32x4
5049 // There are also the NEON VMOV instructions which expect an
5050 // integer constant. Make sure we don't try to parse an FPImm
5052 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5053 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5054 bool isVmovf = TyOp.isToken() &&
5055 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5056 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5057 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5058 Mnemonic.getToken() == "fconsts");
5059 if (!(isVmovf || isFconst))
5060 return MatchOperand_NoMatch;
5062 Parser.Lex(); // Eat '#' or '$'.
5064 // Handle negation, as that still comes through as a separate token.
5065 bool isNegative = false;
5066 if (Parser.getTok().is(AsmToken::Minus)) {
5070 const AsmToken &Tok = Parser.getTok();
5071 SMLoc Loc = Tok.getLoc();
5072 if (Tok.is(AsmToken::Real) && isVmovf) {
5073 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5074 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5075 // If we had a '-' in front, toggle the sign bit.
5076 IntVal ^= (uint64_t)isNegative << 31;
5077 Parser.Lex(); // Eat the token.
5078 Operands.push_back(ARMOperand::CreateImm(
5079 MCConstantExpr::create(IntVal, getContext()),
5080 S, Parser.getTok().getLoc()));
5081 return MatchOperand_Success;
5083 // Also handle plain integers. Instructions which allow floating point
5084 // immediates also allow a raw encoded 8-bit value.
5085 if (Tok.is(AsmToken::Integer) && isFconst) {
5086 int64_t Val = Tok.getIntVal();
5087 Parser.Lex(); // Eat the token.
5088 if (Val > 255 || Val < 0) {
5089 Error(Loc, "encoded floating point value out of range");
5090 return MatchOperand_ParseFail;
5092 float RealVal = ARM_AM::getFPImmFloat(Val);
5093 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5095 Operands.push_back(ARMOperand::CreateImm(
5096 MCConstantExpr::create(Val, getContext()), S,
5097 Parser.getTok().getLoc()));
5098 return MatchOperand_Success;
5101 Error(Loc, "invalid floating point immediate");
5102 return MatchOperand_ParseFail;
5105 /// Parse a arm instruction operand. For now this parses the operand regardless
5106 /// of the mnemonic.
5107 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5108 MCAsmParser &Parser = getParser();
5111 // Check if the current operand has a custom associated parser, if so, try to
5112 // custom parse the operand, or fallback to the general approach.
5113 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5114 if (ResTy == MatchOperand_Success)
5116 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5117 // there was a match, but an error occurred, in which case, just return that
5118 // the operand parsing failed.
5119 if (ResTy == MatchOperand_ParseFail)
5122 switch (getLexer().getKind()) {
5124 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5126 case AsmToken::Identifier: {
5127 // If we've seen a branch mnemonic, the next operand must be a label. This
5128 // is true even if the label is a register name. So "br r1" means branch to
5130 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5132 if (!tryParseRegisterWithWriteBack(Operands))
5134 int Res = tryParseShiftRegister(Operands);
5135 if (Res == 0) // success
5137 else if (Res == -1) // irrecoverable error
5139 // If this is VMRS, check for the apsr_nzcv operand.
5140 if (Mnemonic == "vmrs" &&
5141 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5142 S = Parser.getTok().getLoc();
5144 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5149 // Fall though for the Identifier case that is not a register or a
5152 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5153 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5154 case AsmToken::String: // quoted label names.
5155 case AsmToken::Dot: { // . as a branch target
5156 // This was not a register so parse other operands that start with an
5157 // identifier (like labels) as expressions and create them as immediates.
5158 const MCExpr *IdVal;
5159 S = Parser.getTok().getLoc();
5160 if (getParser().parseExpression(IdVal))
5162 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5163 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5166 case AsmToken::LBrac:
5167 return parseMemory(Operands);
5168 case AsmToken::LCurly:
5169 return parseRegisterList(Operands);
5170 case AsmToken::Dollar:
5171 case AsmToken::Hash: {
5172 // #42 -> immediate.
5173 S = Parser.getTok().getLoc();
5176 if (Parser.getTok().isNot(AsmToken::Colon)) {
5177 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5178 const MCExpr *ImmVal;
5179 if (getParser().parseExpression(ImmVal))
5181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5183 int32_t Val = CE->getValue();
5184 if (isNegative && Val == 0)
5185 ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5187 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5188 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5190 // There can be a trailing '!' on operands that we want as a separate
5191 // '!' Token operand. Handle that here. For example, the compatibility
5192 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5193 if (Parser.getTok().is(AsmToken::Exclaim)) {
5194 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5195 Parser.getTok().getLoc()));
5196 Parser.Lex(); // Eat exclaim token
5200 // w/ a ':' after the '#', it's just like a plain ':'.
5203 case AsmToken::Colon: {
5204 // ":lower16:" and ":upper16:" expression prefixes
5205 // FIXME: Check it's an expression prefix,
5206 // e.g. (FOO - :lower16:BAR) isn't legal.
5207 ARMMCExpr::VariantKind RefKind;
5208 if (parsePrefix(RefKind))
5211 const MCExpr *SubExprVal;
5212 if (getParser().parseExpression(SubExprVal))
5215 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5217 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5218 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5221 case AsmToken::Equal: {
5222 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5223 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5225 Parser.Lex(); // Eat '='
5226 const MCExpr *SubExprVal;
5227 if (getParser().parseExpression(SubExprVal))
5229 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5231 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5232 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5238 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5239 // :lower16: and :upper16:.
5240 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5241 MCAsmParser &Parser = getParser();
5242 RefKind = ARMMCExpr::VK_ARM_None;
5244 // consume an optional '#' (GNU compatibility)
5245 if (getLexer().is(AsmToken::Hash))
5248 // :lower16: and :upper16: modifiers
5249 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5250 Parser.Lex(); // Eat ':'
5252 if (getLexer().isNot(AsmToken::Identifier)) {
5253 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5258 COFF = (1 << MCObjectFileInfo::IsCOFF),
5259 ELF = (1 << MCObjectFileInfo::IsELF),
5260 MACHO = (1 << MCObjectFileInfo::IsMachO)
5262 static const struct PrefixEntry {
5263 const char *Spelling;
5264 ARMMCExpr::VariantKind VariantKind;
5265 uint8_t SupportedFormats;
5266 } PrefixEntries[] = {
5267 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5268 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5271 StringRef IDVal = Parser.getTok().getIdentifier();
5273 const auto &Prefix =
5274 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5275 [&IDVal](const PrefixEntry &PE) {
5276 return PE.Spelling == IDVal;
5278 if (Prefix == std::end(PrefixEntries)) {
5279 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5283 uint8_t CurrentFormat;
5284 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5285 case MCObjectFileInfo::IsMachO:
5286 CurrentFormat = MACHO;
5288 case MCObjectFileInfo::IsELF:
5289 CurrentFormat = ELF;
5291 case MCObjectFileInfo::IsCOFF:
5292 CurrentFormat = COFF;
5296 if (~Prefix->SupportedFormats & CurrentFormat) {
5297 Error(Parser.getTok().getLoc(),
5298 "cannot represent relocation in the current file format");
5302 RefKind = Prefix->VariantKind;
5305 if (getLexer().isNot(AsmToken::Colon)) {
5306 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5309 Parser.Lex(); // Eat the last ':'
5314 /// \brief Given a mnemonic, split out possible predication code and carry
5315 /// setting letters to form a canonical mnemonic and flags.
5317 // FIXME: Would be nice to autogen this.
5318 // FIXME: This is a bit of a maze of special cases.
5319 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5320 unsigned &PredicationCode,
5322 unsigned &ProcessorIMod,
5323 StringRef &ITMask) {
5324 PredicationCode = ARMCC::AL;
5325 CarrySetting = false;
5328 // Ignore some mnemonics we know aren't predicated forms.
5330 // FIXME: Would be nice to autogen this.
5331 if ((Mnemonic == "movs" && isThumb()) ||
5332 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5333 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5334 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5335 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5336 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5337 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5338 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5339 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5340 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5341 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5342 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5343 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5344 Mnemonic.startswith("vsel"))
5347 // First, split out any predication code. Ignore mnemonics we know aren't
5348 // predicated but do have a carry-set and so weren't caught above.
5349 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5350 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5351 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5352 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5353 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5354 .Case("eq", ARMCC::EQ)
5355 .Case("ne", ARMCC::NE)
5356 .Case("hs", ARMCC::HS)
5357 .Case("cs", ARMCC::HS)
5358 .Case("lo", ARMCC::LO)
5359 .Case("cc", ARMCC::LO)
5360 .Case("mi", ARMCC::MI)
5361 .Case("pl", ARMCC::PL)
5362 .Case("vs", ARMCC::VS)
5363 .Case("vc", ARMCC::VC)
5364 .Case("hi", ARMCC::HI)
5365 .Case("ls", ARMCC::LS)
5366 .Case("ge", ARMCC::GE)
5367 .Case("lt", ARMCC::LT)
5368 .Case("gt", ARMCC::GT)
5369 .Case("le", ARMCC::LE)
5370 .Case("al", ARMCC::AL)
5373 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5374 PredicationCode = CC;
5378 // Next, determine if we have a carry setting bit. We explicitly ignore all
5379 // the instructions we know end in 's'.
5380 if (Mnemonic.endswith("s") &&
5381 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5382 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5383 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5384 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5385 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5386 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5387 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5388 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5389 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5390 (Mnemonic == "movs" && isThumb()))) {
5391 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5392 CarrySetting = true;
5395 // The "cps" instruction can have a interrupt mode operand which is glued into
5396 // the mnemonic. Check if this is the case, split it and parse the imod op
5397 if (Mnemonic.startswith("cps")) {
5398 // Split out any imod code.
5400 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5401 .Case("ie", ARM_PROC::IE)
5402 .Case("id", ARM_PROC::ID)
5405 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5406 ProcessorIMod = IMod;
5410 // The "it" instruction has the condition mask on the end of the mnemonic.
5411 if (Mnemonic.startswith("it")) {
5412 ITMask = Mnemonic.slice(2, Mnemonic.size());
5413 Mnemonic = Mnemonic.slice(0, 2);
5419 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5420 /// inclusion of carry set or predication code operands.
5422 // FIXME: It would be nice to autogen this.
5423 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5424 bool &CanAcceptCarrySet,
5425 bool &CanAcceptPredicationCode) {
5427 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5428 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5429 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5430 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5431 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5432 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5433 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5435 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5436 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5438 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5439 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5440 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5441 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5442 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5443 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5444 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5445 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5446 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5447 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5448 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5449 // These mnemonics are never predicable
5450 CanAcceptPredicationCode = false;
5451 } else if (!isThumb()) {
5452 // Some instructions are only predicable in Thumb mode
5453 CanAcceptPredicationCode =
5454 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5455 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5456 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5457 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5458 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5459 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5460 !Mnemonic.startswith("srs");
5461 } else if (isThumbOne()) {
5463 CanAcceptPredicationCode = Mnemonic != "movs";
5465 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5467 CanAcceptPredicationCode = true;
5470 // \brief Some Thumb instructions have two operand forms that are not
5471 // available as three operand, convert to two operand form if possible.
5473 // FIXME: We would really like to be able to tablegen'erate this.
5474 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5476 OperandVector &Operands) {
5477 if (Operands.size() != 6)
5480 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5481 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5482 if (!Op3.isReg() || !Op4.isReg())
5485 auto Op3Reg = Op3.getReg();
5486 auto Op4Reg = Op4.getReg();
5488 // For most Thumb2 cases we just generate the 3 operand form and reduce
5489 // it in processInstruction(), but for ADD involving PC the the 3 operand
5490 // form won't accept PC so we do the transformation here.
5491 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5493 if (Mnemonic != "add" ||
5494 !(Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5495 (Op5.isReg() && Op5.getReg() == ARM::PC)))
5497 } else if (!isThumbOne())
5500 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5501 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5502 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5503 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5506 // If first 2 operands of a 3 operand instruction are the same
5507 // then transform to 2 operand version of the same instruction
5508 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5509 bool Transform = Op3Reg == Op4Reg;
5511 // For communtative operations, we might be able to transform if we swap
5512 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
5514 const ARMOperand *LastOp = &Op5;
5516 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5517 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5518 Mnemonic == "and" || Mnemonic == "eor" ||
5519 Mnemonic == "adc" || Mnemonic == "orr")) {
5525 // If both registers are the same then remove one of them from
5526 // the operand list, with certain exceptions.
5528 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5529 // 2 operand forms don't exist.
5530 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5534 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5535 // 3-bits because the ARMARM says not to.
5536 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5542 std::swap(Op4, Op5);
5543 Operands.erase(Operands.begin() + 3);
5547 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5548 OperandVector &Operands) {
5549 // FIXME: This is all horribly hacky. We really need a better way to deal
5550 // with optional operands like this in the matcher table.
5552 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5553 // another does not. Specifically, the MOVW instruction does not. So we
5554 // special case it here and remove the defaulted (non-setting) cc_out
5555 // operand if that's the instruction we're trying to match.
5557 // We do this as post-processing of the explicit operands rather than just
5558 // conditionally adding the cc_out in the first place because we need
5559 // to check the type of the parsed immediate operand.
5560 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5561 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5562 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5563 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5566 // Register-register 'add' for thumb does not have a cc_out operand
5567 // when there are only two register operands.
5568 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5569 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5570 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5571 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5573 // Register-register 'add' for thumb does not have a cc_out operand
5574 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5575 // have to check the immediate range here since Thumb2 has a variant
5576 // that can handle a different range and has a cc_out operand.
5577 if (((isThumb() && Mnemonic == "add") ||
5578 (isThumbTwo() && Mnemonic == "sub")) &&
5579 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5580 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5581 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5582 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5583 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5584 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5586 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5587 // imm0_4095 variant. That's the least-preferred variant when
5588 // selecting via the generic "add" mnemonic, so to know that we
5589 // should remove the cc_out operand, we have to explicitly check that
5590 // it's not one of the other variants. Ugh.
5591 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5592 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5593 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5594 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5595 // Nest conditions rather than one big 'if' statement for readability.
5597 // If both registers are low, we're in an IT block, and the immediate is
5598 // in range, we should use encoding T1 instead, which has a cc_out.
5600 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5601 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5602 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5604 // Check against T3. If the second register is the PC, this is an
5605 // alternate form of ADR, which uses encoding T4, so check for that too.
5606 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5607 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5610 // Otherwise, we use encoding T4, which does not have a cc_out
5615 // The thumb2 multiply instruction doesn't have a CCOut register, so
5616 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5617 // use the 16-bit encoding or not.
5618 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5619 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5620 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5621 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5622 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5623 // If the registers aren't low regs, the destination reg isn't the
5624 // same as one of the source regs, or the cc_out operand is zero
5625 // outside of an IT block, we have to use the 32-bit encoding, so
5626 // remove the cc_out operand.
5627 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5628 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5629 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5630 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5631 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5632 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5633 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5636 // Also check the 'mul' syntax variant that doesn't specify an explicit
5637 // destination register.
5638 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5639 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5640 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5641 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5642 // If the registers aren't low regs or the cc_out operand is zero
5643 // outside of an IT block, we have to use the 32-bit encoding, so
5644 // remove the cc_out operand.
5645 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5646 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5652 // Register-register 'add/sub' for thumb does not have a cc_out operand
5653 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5654 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5655 // right, this will result in better diagnostics (which operand is off)
5657 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5658 (Operands.size() == 5 || Operands.size() == 6) &&
5659 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5660 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5661 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5662 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5663 (Operands.size() == 6 &&
5664 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5670 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5671 OperandVector &Operands) {
5672 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5673 unsigned RegIdx = 3;
5674 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5675 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5676 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5677 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5680 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5681 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5682 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5683 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5684 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5690 static bool isDataTypeToken(StringRef Tok) {
5691 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5692 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5693 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5694 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5695 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5696 Tok == ".f" || Tok == ".d";
5699 // FIXME: This bit should probably be handled via an explicit match class
5700 // in the .td files that matches the suffix instead of having it be
5701 // a literal string token the way it is now.
5702 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5703 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5705 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5706 unsigned VariantID);
5708 static bool RequiresVFPRegListValidation(StringRef Inst,
5709 bool &AcceptSinglePrecisionOnly,
5710 bool &AcceptDoublePrecisionOnly) {
5711 if (Inst.size() < 7)
5714 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5715 StringRef AddressingMode = Inst.substr(4, 2);
5716 if (AddressingMode == "ia" || AddressingMode == "db" ||
5717 AddressingMode == "ea" || AddressingMode == "fd") {
5718 AcceptSinglePrecisionOnly = Inst[6] == 's';
5719 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5727 /// Parse an arm instruction mnemonic followed by its operands.
5728 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5729 SMLoc NameLoc, OperandVector &Operands) {
5730 MCAsmParser &Parser = getParser();
5731 // FIXME: Can this be done via tablegen in some fashion?
5732 bool RequireVFPRegisterListCheck;
5733 bool AcceptSinglePrecisionOnly;
5734 bool AcceptDoublePrecisionOnly;
5735 RequireVFPRegisterListCheck =
5736 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5737 AcceptDoublePrecisionOnly);
5739 // Apply mnemonic aliases before doing anything else, as the destination
5740 // mnemonic may include suffices and we want to handle them normally.
5741 // The generic tblgen'erated code does this later, at the start of
5742 // MatchInstructionImpl(), but that's too late for aliases that include
5743 // any sort of suffix.
5744 uint64_t AvailableFeatures = getAvailableFeatures();
5745 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5746 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5748 // First check for the ARM-specific .req directive.
5749 if (Parser.getTok().is(AsmToken::Identifier) &&
5750 Parser.getTok().getIdentifier() == ".req") {
5751 parseDirectiveReq(Name, NameLoc);
5752 // We always return 'error' for this, as we're done with this
5753 // statement and don't need to match the 'instruction."
5757 // Create the leading tokens for the mnemonic, split by '.' characters.
5758 size_t Start = 0, Next = Name.find('.');
5759 StringRef Mnemonic = Name.slice(Start, Next);
5761 // Split out the predication code and carry setting flag from the mnemonic.
5762 unsigned PredicationCode;
5763 unsigned ProcessorIMod;
5766 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5767 ProcessorIMod, ITMask);
5769 // In Thumb1, only the branch (B) instruction can be predicated.
5770 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5771 Parser.eatToEndOfStatement();
5772 return Error(NameLoc, "conditional execution not supported in Thumb1");
5775 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5777 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5778 // is the mask as it will be for the IT encoding if the conditional
5779 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5780 // where the conditional bit0 is zero, the instruction post-processing
5781 // will adjust the mask accordingly.
5782 if (Mnemonic == "it") {
5783 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5784 if (ITMask.size() > 3) {
5785 Parser.eatToEndOfStatement();
5786 return Error(Loc, "too many conditions on IT instruction");
5789 for (unsigned i = ITMask.size(); i != 0; --i) {
5790 char pos = ITMask[i - 1];
5791 if (pos != 't' && pos != 'e') {
5792 Parser.eatToEndOfStatement();
5793 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5796 if (ITMask[i - 1] == 't')
5799 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5802 // FIXME: This is all a pretty gross hack. We should automatically handle
5803 // optional operands like this via tblgen.
5805 // Next, add the CCOut and ConditionCode operands, if needed.
5807 // For mnemonics which can ever incorporate a carry setting bit or predication
5808 // code, our matching model involves us always generating CCOut and
5809 // ConditionCode operands to match the mnemonic "as written" and then we let
5810 // the matcher deal with finding the right instruction or generating an
5811 // appropriate error.
5812 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5813 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5815 // If we had a carry-set on an instruction that can't do that, issue an
5817 if (!CanAcceptCarrySet && CarrySetting) {
5818 Parser.eatToEndOfStatement();
5819 return Error(NameLoc, "instruction '" + Mnemonic +
5820 "' can not set flags, but 's' suffix specified");
5822 // If we had a predication code on an instruction that can't do that, issue an
5824 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5825 Parser.eatToEndOfStatement();
5826 return Error(NameLoc, "instruction '" + Mnemonic +
5827 "' is not predicable, but condition code specified");
5830 // Add the carry setting operand, if necessary.
5831 if (CanAcceptCarrySet) {
5832 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5833 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5837 // Add the predication code operand, if necessary.
5838 if (CanAcceptPredicationCode) {
5839 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5841 Operands.push_back(ARMOperand::CreateCondCode(
5842 ARMCC::CondCodes(PredicationCode), Loc));
5845 // Add the processor imod operand, if necessary.
5846 if (ProcessorIMod) {
5847 Operands.push_back(ARMOperand::CreateImm(
5848 MCConstantExpr::create(ProcessorIMod, getContext()),
5850 } else if (Mnemonic == "cps" && isMClass()) {
5851 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5854 // Add the remaining tokens in the mnemonic.
5855 while (Next != StringRef::npos) {
5857 Next = Name.find('.', Start + 1);
5858 StringRef ExtraToken = Name.slice(Start, Next);
5860 // Some NEON instructions have an optional datatype suffix that is
5861 // completely ignored. Check for that.
5862 if (isDataTypeToken(ExtraToken) &&
5863 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5866 // For for ARM mode generate an error if the .n qualifier is used.
5867 if (ExtraToken == ".n" && !isThumb()) {
5868 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5869 Parser.eatToEndOfStatement();
5870 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5874 // The .n qualifier is always discarded as that is what the tables
5875 // and matcher expect. In ARM mode the .w qualifier has no effect,
5876 // so discard it to avoid errors that can be caused by the matcher.
5877 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5878 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5879 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5883 // Read the remaining operands.
5884 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5885 // Read the first operand.
5886 if (parseOperand(Operands, Mnemonic)) {
5887 Parser.eatToEndOfStatement();
5891 while (getLexer().is(AsmToken::Comma)) {
5892 Parser.Lex(); // Eat the comma.
5894 // Parse and remember the operand.
5895 if (parseOperand(Operands, Mnemonic)) {
5896 Parser.eatToEndOfStatement();
5902 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5903 SMLoc Loc = getLexer().getLoc();
5904 Parser.eatToEndOfStatement();
5905 return Error(Loc, "unexpected token in argument list");
5908 Parser.Lex(); // Consume the EndOfStatement
5910 if (RequireVFPRegisterListCheck) {
5911 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5912 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5913 return Error(Op.getStartLoc(),
5914 "VFP/Neon single precision register expected");
5915 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5916 return Error(Op.getStartLoc(),
5917 "VFP/Neon double precision register expected");
5920 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
5922 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5923 // do and don't have a cc_out optional-def operand. With some spot-checks
5924 // of the operand list, we can figure out which variant we're trying to
5925 // parse and adjust accordingly before actually matching. We shouldn't ever
5926 // try to remove a cc_out operand that was explicitly set on the
5927 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5928 // table driven matcher doesn't fit well with the ARM instruction set.
5929 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5930 Operands.erase(Operands.begin() + 1);
5932 // Some instructions have the same mnemonic, but don't always
5933 // have a predicate. Distinguish them here and delete the
5934 // predicate if needed.
5935 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5936 Operands.erase(Operands.begin() + 1);
5938 // ARM mode 'blx' need special handling, as the register operand version
5939 // is predicable, but the label operand version is not. So, we can't rely
5940 // on the Mnemonic based checking to correctly figure out when to put
5941 // a k_CondCode operand in the list. If we're trying to match the label
5942 // version, remove the k_CondCode operand here.
5943 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5944 static_cast<ARMOperand &>(*Operands[2]).isImm())
5945 Operands.erase(Operands.begin() + 1);
5947 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5948 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5949 // a single GPRPair reg operand is used in the .td file to replace the two
5950 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5951 // expressed as a GPRPair, so we have to manually merge them.
5952 // FIXME: We would really like to be able to tablegen'erate this.
5953 if (!isThumb() && Operands.size() > 4 &&
5954 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5955 Mnemonic == "stlexd")) {
5956 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5957 unsigned Idx = isLoad ? 2 : 3;
5958 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5959 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5961 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5962 // Adjust only if Op1 and Op2 are GPRs.
5963 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5964 MRC.contains(Op2.getReg())) {
5965 unsigned Reg1 = Op1.getReg();
5966 unsigned Reg2 = Op2.getReg();
5967 unsigned Rt = MRI->getEncodingValue(Reg1);
5968 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5970 // Rt2 must be Rt + 1 and Rt must be even.
5971 if (Rt + 1 != Rt2 || (Rt & 1)) {
5972 Error(Op2.getStartLoc(), isLoad
5973 ? "destination operands must be sequential"
5974 : "source operands must be sequential");
5977 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5978 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5980 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5981 Operands.erase(Operands.begin() + Idx + 1);
5985 // GNU Assembler extension (compatibility)
5986 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5987 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5988 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5990 assert(Op2.isReg() && "expected register argument");
5992 unsigned SuperReg = MRI->getMatchingSuperReg(
5993 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5995 assert(SuperReg && "expected register pair");
5997 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
6000 Operands.begin() + 3,
6001 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6005 // FIXME: As said above, this is all a pretty gross hack. This instruction
6006 // does not fit with other "subs" and tblgen.
6007 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6008 // so the Mnemonic is the original name "subs" and delete the predicate
6009 // operand so it will match the table entry.
6010 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6011 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6012 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
6013 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6014 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6015 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6016 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
6017 Operands.erase(Operands.begin() + 1);
6022 // Validate context-sensitive operand constraints.
6024 // return 'true' if register list contains non-low GPR registers,
6025 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6026 // 'containsReg' to true.
6027 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
6028 unsigned HiReg, bool &containsReg) {
6029 containsReg = false;
6030 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6031 unsigned OpReg = Inst.getOperand(i).getReg();
6034 // Anything other than a low register isn't legal here.
6035 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6041 // Check if the specified regisgter is in the register list of the inst,
6042 // starting at the indicated operand number.
6043 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
6044 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6045 unsigned OpReg = Inst.getOperand(i).getReg();
6052 // Return true if instruction has the interesting property of being
6053 // allowed in IT blocks, but not being predicable.
6054 static bool instIsBreakpoint(const MCInst &Inst) {
6055 return Inst.getOpcode() == ARM::tBKPT ||
6056 Inst.getOpcode() == ARM::BKPT ||
6057 Inst.getOpcode() == ARM::tHLT ||
6058 Inst.getOpcode() == ARM::HLT;
6062 bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
6063 const OperandVector &Operands,
6064 unsigned ListNo, bool IsARPop) {
6065 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6066 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6068 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6069 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6070 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6072 if (!IsARPop && ListContainsSP)
6073 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6074 "SP may not be in the register list");
6075 else if (ListContainsPC && ListContainsLR)
6076 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6077 "PC and LR may not be in the register list simultaneously");
6078 else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6079 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6080 "instruction must be outside of IT block or the last "
6081 "instruction in an IT block");
6085 bool ARMAsmParser::validatetSTMRegList(MCInst Inst,
6086 const OperandVector &Operands,
6088 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6089 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6091 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6092 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6094 if (ListContainsSP && ListContainsPC)
6095 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6096 "SP and PC may not be in the register list");
6097 else if (ListContainsSP)
6098 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6099 "SP may not be in the register list");
6100 else if (ListContainsPC)
6101 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6102 "PC may not be in the register list");
6106 // FIXME: We would really like to be able to tablegen'erate this.
6107 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6108 const OperandVector &Operands) {
6109 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6110 SMLoc Loc = Operands[0]->getStartLoc();
6112 // Check the IT block state first.
6113 // NOTE: BKPT and HLT instructions have the interesting property of being
6114 // allowed in IT blocks, but not being predicable. They just always execute.
6115 if (inITBlock() && !instIsBreakpoint(Inst)) {
6117 if (ITState.FirstCond)
6118 ITState.FirstCond = false;
6120 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6121 // The instruction must be predicable.
6122 if (!MCID.isPredicable())
6123 return Error(Loc, "instructions in IT block must be predicable");
6124 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6125 unsigned ITCond = Bit ? ITState.Cond :
6126 ARMCC::getOppositeCondition(ITState.Cond);
6127 if (Cond != ITCond) {
6128 // Find the condition code Operand to get its SMLoc information.
6130 for (unsigned I = 1; I < Operands.size(); ++I)
6131 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6132 CondLoc = Operands[I]->getStartLoc();
6133 return Error(CondLoc, "incorrect condition in IT block; got '" +
6134 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6135 "', but expected '" +
6136 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6138 // Check for non-'al' condition codes outside of the IT block.
6139 } else if (isThumbTwo() && MCID.isPredicable() &&
6140 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6141 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6142 Inst.getOpcode() != ARM::t2Bcc)
6143 return Error(Loc, "predicated instructions must be in IT block");
6145 const unsigned Opcode = Inst.getOpcode();
6149 case ARM::LDRD_POST: {
6150 const unsigned RtReg = Inst.getOperand(0).getReg();
6153 if (RtReg == ARM::LR)
6154 return Error(Operands[3]->getStartLoc(),
6157 const unsigned Rt = MRI->getEncodingValue(RtReg);
6158 // Rt must be even-numbered.
6160 return Error(Operands[3]->getStartLoc(),
6161 "Rt must be even-numbered");
6163 // Rt2 must be Rt + 1.
6164 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6166 return Error(Operands[3]->getStartLoc(),
6167 "destination operands must be sequential");
6169 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6170 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6171 // For addressing modes with writeback, the base register needs to be
6172 // different from the destination registers.
6173 if (Rn == Rt || Rn == Rt2)
6174 return Error(Operands[3]->getStartLoc(),
6175 "base register needs to be different from destination "
6182 case ARM::t2LDRD_PRE:
6183 case ARM::t2LDRD_POST: {
6184 // Rt2 must be different from Rt.
6185 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6186 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6188 return Error(Operands[3]->getStartLoc(),
6189 "destination operands can't be identical");
6193 const unsigned RmReg = Inst.getOperand(0).getReg();
6194 // Rm = SP is no longer unpredictable in v8-A
6195 if (RmReg == ARM::SP && !hasV8Ops())
6196 return Error(Operands[2]->getStartLoc(),
6197 "r13 (SP) is an unpredictable operand to BXJ");
6201 // Rt2 must be Rt + 1.
6202 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6203 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6205 return Error(Operands[3]->getStartLoc(),
6206 "source operands must be sequential");
6210 case ARM::STRD_POST: {
6211 // Rt2 must be Rt + 1.
6212 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6213 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6215 return Error(Operands[3]->getStartLoc(),
6216 "source operands must be sequential");
6219 case ARM::STR_PRE_IMM:
6220 case ARM::STR_PRE_REG:
6221 case ARM::STR_POST_IMM:
6222 case ARM::STR_POST_REG:
6224 case ARM::STRH_POST:
6225 case ARM::STRB_PRE_IMM:
6226 case ARM::STRB_PRE_REG:
6227 case ARM::STRB_POST_IMM:
6228 case ARM::STRB_POST_REG: {
6229 // Rt must be different from Rn.
6230 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6231 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6234 return Error(Operands[3]->getStartLoc(),
6235 "source register and base register can't be identical");
6238 case ARM::LDR_PRE_IMM:
6239 case ARM::LDR_PRE_REG:
6240 case ARM::LDR_POST_IMM:
6241 case ARM::LDR_POST_REG:
6243 case ARM::LDRH_POST:
6244 case ARM::LDRSH_PRE:
6245 case ARM::LDRSH_POST:
6246 case ARM::LDRB_PRE_IMM:
6247 case ARM::LDRB_PRE_REG:
6248 case ARM::LDRB_POST_IMM:
6249 case ARM::LDRB_POST_REG:
6250 case ARM::LDRSB_PRE:
6251 case ARM::LDRSB_POST: {
6252 // Rt must be different from Rn.
6253 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6254 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6257 return Error(Operands[3]->getStartLoc(),
6258 "destination register and base register can't be identical");
6263 // Width must be in range [1, 32-lsb].
6264 unsigned LSB = Inst.getOperand(2).getImm();
6265 unsigned Widthm1 = Inst.getOperand(3).getImm();
6266 if (Widthm1 >= 32 - LSB)
6267 return Error(Operands[5]->getStartLoc(),
6268 "bitfield width must be in range [1,32-lsb]");
6271 // Notionally handles ARM::tLDMIA_UPD too.
6273 // If we're parsing Thumb2, the .w variant is available and handles
6274 // most cases that are normally illegal for a Thumb1 LDM instruction.
6275 // We'll make the transformation in processInstruction() if necessary.
6277 // Thumb LDM instructions are writeback iff the base register is not
6278 // in the register list.
6279 unsigned Rn = Inst.getOperand(0).getReg();
6280 bool HasWritebackToken =
6281 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6282 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6283 bool ListContainsBase;
6284 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6285 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6286 "registers must be in range r0-r7");
6287 // If we should have writeback, then there should be a '!' token.
6288 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6289 return Error(Operands[2]->getStartLoc(),
6290 "writeback operator '!' expected");
6291 // If we should not have writeback, there must not be a '!'. This is
6292 // true even for the 32-bit wide encodings.
6293 if (ListContainsBase && HasWritebackToken)
6294 return Error(Operands[3]->getStartLoc(),
6295 "writeback operator '!' not allowed when base register "
6296 "in register list");
6298 if (validatetLDMRegList(Inst, Operands, 3))
6302 case ARM::LDMIA_UPD:
6303 case ARM::LDMDB_UPD:
6304 case ARM::LDMIB_UPD:
6305 case ARM::LDMDA_UPD:
6306 // ARM variants loading and updating the same register are only officially
6307 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6310 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6311 return Error(Operands.back()->getStartLoc(),
6312 "writeback register not allowed in register list");
6316 if (validatetLDMRegList(Inst, Operands, 3))
6321 if (validatetSTMRegList(Inst, Operands, 3))
6324 case ARM::t2LDMIA_UPD:
6325 case ARM::t2LDMDB_UPD:
6326 case ARM::t2STMIA_UPD:
6327 case ARM::t2STMDB_UPD: {
6328 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6329 return Error(Operands.back()->getStartLoc(),
6330 "writeback register not allowed in register list");
6332 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6333 if (validatetLDMRegList(Inst, Operands, 3))
6336 if (validatetSTMRegList(Inst, Operands, 3))
6341 case ARM::sysLDMIA_UPD:
6342 case ARM::sysLDMDA_UPD:
6343 case ARM::sysLDMDB_UPD:
6344 case ARM::sysLDMIB_UPD:
6345 if (!listContainsReg(Inst, 3, ARM::PC))
6346 return Error(Operands[4]->getStartLoc(),
6347 "writeback register only allowed on system LDM "
6348 "if PC in register-list");
6350 case ARM::sysSTMIA_UPD:
6351 case ARM::sysSTMDA_UPD:
6352 case ARM::sysSTMDB_UPD:
6353 case ARM::sysSTMIB_UPD:
6354 return Error(Operands[2]->getStartLoc(),
6355 "system STM cannot have writeback register");
6357 // The second source operand must be the same register as the destination
6360 // In this case, we must directly check the parsed operands because the
6361 // cvtThumbMultiply() function is written in such a way that it guarantees
6362 // this first statement is always true for the new Inst. Essentially, the
6363 // destination is unconditionally copied into the second source operand
6364 // without checking to see if it matches what we actually parsed.
6365 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6366 ((ARMOperand &)*Operands[5]).getReg()) &&
6367 (((ARMOperand &)*Operands[3]).getReg() !=
6368 ((ARMOperand &)*Operands[4]).getReg())) {
6369 return Error(Operands[3]->getStartLoc(),
6370 "destination register must match source register");
6374 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6375 // so only issue a diagnostic for thumb1. The instructions will be
6376 // switched to the t2 encodings in processInstruction() if necessary.
6378 bool ListContainsBase;
6379 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6381 return Error(Operands[2]->getStartLoc(),
6382 "registers must be in range r0-r7 or pc");
6383 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6388 bool ListContainsBase;
6389 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6391 return Error(Operands[2]->getStartLoc(),
6392 "registers must be in range r0-r7 or lr");
6393 if (validatetSTMRegList(Inst, Operands, 2))
6397 case ARM::tSTMIA_UPD: {
6398 bool ListContainsBase, InvalidLowList;
6399 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6400 0, ListContainsBase);
6401 if (InvalidLowList && !isThumbTwo())
6402 return Error(Operands[4]->getStartLoc(),
6403 "registers must be in range r0-r7");
6405 // This would be converted to a 32-bit stm, but that's not valid if the
6406 // writeback register is in the list.
6407 if (InvalidLowList && ListContainsBase)
6408 return Error(Operands[4]->getStartLoc(),
6409 "writeback operator '!' not allowed when base register "
6410 "in register list");
6412 if (validatetSTMRegList(Inst, Operands, 4))
6416 case ARM::tADDrSP: {
6417 // If the non-SP source operand and the destination operand are not the
6418 // same, we need thumb2 (for the wide encoding), or we have an error.
6419 if (!isThumbTwo() &&
6420 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6421 return Error(Operands[4]->getStartLoc(),
6422 "source register must be the same as destination");
6426 // Final range checking for Thumb unconditional branch instructions.
6428 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6429 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6432 int op = (Operands[2]->isImm()) ? 2 : 3;
6433 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6434 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6437 // Final range checking for Thumb conditional branch instructions.
6439 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6440 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6443 int Op = (Operands[2]->isImm()) ? 2 : 3;
6444 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6445 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6450 case ARM::t2MOVTi16:
6452 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6453 // especially when we turn it into a movw and the expression <symbol> does
6454 // not have a :lower16: or :upper16 as part of the expression. We don't
6455 // want the behavior of silently truncating, which can be unexpected and
6456 // lead to bugs that are difficult to find since this is an easy mistake
6458 int i = (Operands[3]->isImm()) ? 3 : 4;
6459 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6460 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6462 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6464 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6465 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6466 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6469 "immediate expression for mov requires :lower16: or :upper16");
6477 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6479 default: llvm_unreachable("unexpected opcode!");
6481 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6482 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6483 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6484 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6485 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6486 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6487 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6488 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6489 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6492 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6493 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6494 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6495 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6496 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6498 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6499 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6500 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6501 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6502 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6504 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6505 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6506 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6507 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6508 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6511 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6512 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6513 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6514 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6515 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6516 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6517 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6518 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6519 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6520 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6521 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6522 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6523 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6524 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6525 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6528 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6529 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6530 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6531 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6532 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6533 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6534 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6535 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6536 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6537 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6538 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6539 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6540 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6541 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6542 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6543 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6544 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6545 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6548 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6549 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6550 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6551 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6552 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6553 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6554 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6555 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6556 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6557 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6558 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6559 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6560 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6561 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6562 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6565 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6566 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6567 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6568 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6569 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6570 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6571 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6572 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6573 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6574 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6575 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6576 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6577 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6578 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6579 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6580 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6581 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6582 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6586 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6588 default: llvm_unreachable("unexpected opcode!");
6590 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6591 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6592 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6593 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6594 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6595 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6596 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6597 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6598 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6601 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6602 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6603 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6604 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6605 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6606 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6607 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6608 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6609 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6610 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6611 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6612 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6613 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6614 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6615 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6618 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6619 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6620 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6621 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6622 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6623 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6624 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6625 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6626 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6627 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6628 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6629 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6630 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6631 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6632 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6633 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6634 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6635 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6638 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6639 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6640 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6641 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6642 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6643 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6644 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6645 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6646 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6647 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6648 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6649 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6650 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6651 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6652 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6655 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6656 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6657 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6658 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6659 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6660 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6661 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6662 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6663 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6664 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6665 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6666 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6667 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6668 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6669 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6670 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6671 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6672 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6675 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6676 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6677 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6678 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6679 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6680 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6681 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6682 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6683 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6684 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6685 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6686 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6687 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6688 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6689 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6692 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6693 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6694 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6695 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6696 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6697 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6698 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6699 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6700 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6701 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6702 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6703 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6704 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6705 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6706 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6707 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6708 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6709 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6712 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6713 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6714 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6715 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6716 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6717 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6718 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6719 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6720 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6721 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6722 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6723 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6724 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6725 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6726 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6727 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6728 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6729 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6733 bool ARMAsmParser::processInstruction(MCInst &Inst,
6734 const OperandVector &Operands,
6736 switch (Inst.getOpcode()) {
6737 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6738 case ARM::LDRT_POST:
6739 case ARM::LDRBT_POST: {
6740 const unsigned Opcode =
6741 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6742 : ARM::LDRBT_POST_IMM;
6744 TmpInst.setOpcode(Opcode);
6745 TmpInst.addOperand(Inst.getOperand(0));
6746 TmpInst.addOperand(Inst.getOperand(1));
6747 TmpInst.addOperand(Inst.getOperand(1));
6748 TmpInst.addOperand(MCOperand::createReg(0));
6749 TmpInst.addOperand(MCOperand::createImm(0));
6750 TmpInst.addOperand(Inst.getOperand(2));
6751 TmpInst.addOperand(Inst.getOperand(3));
6755 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6756 case ARM::STRT_POST:
6757 case ARM::STRBT_POST: {
6758 const unsigned Opcode =
6759 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6760 : ARM::STRBT_POST_IMM;
6762 TmpInst.setOpcode(Opcode);
6763 TmpInst.addOperand(Inst.getOperand(1));
6764 TmpInst.addOperand(Inst.getOperand(0));
6765 TmpInst.addOperand(Inst.getOperand(1));
6766 TmpInst.addOperand(MCOperand::createReg(0));
6767 TmpInst.addOperand(MCOperand::createImm(0));
6768 TmpInst.addOperand(Inst.getOperand(2));
6769 TmpInst.addOperand(Inst.getOperand(3));
6773 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6775 if (Inst.getOperand(1).getReg() != ARM::PC ||
6776 Inst.getOperand(5).getReg() != 0 ||
6777 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6780 TmpInst.setOpcode(ARM::ADR);
6781 TmpInst.addOperand(Inst.getOperand(0));
6782 if (Inst.getOperand(2).isImm()) {
6783 // Immediate (mod_imm) will be in its encoded form, we must unencode it
6784 // before passing it to the ADR instruction.
6785 unsigned Enc = Inst.getOperand(2).getImm();
6786 TmpInst.addOperand(MCOperand::createImm(
6787 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6789 // Turn PC-relative expression into absolute expression.
6790 // Reading PC provides the start of the current instruction + 8 and
6791 // the transform to adr is biased by that.
6792 MCSymbol *Dot = getContext().createTempSymbol();
6794 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6795 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
6796 MCSymbolRefExpr::VK_None,
6798 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
6799 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
6801 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
6803 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
6805 TmpInst.addOperand(Inst.getOperand(3));
6806 TmpInst.addOperand(Inst.getOperand(4));
6810 // Aliases for alternate PC+imm syntax of LDR instructions.
6811 case ARM::t2LDRpcrel:
6812 // Select the narrow version if the immediate will fit.
6813 if (Inst.getOperand(1).getImm() > 0 &&
6814 Inst.getOperand(1).getImm() <= 0xff &&
6815 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6816 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6817 Inst.setOpcode(ARM::tLDRpci);
6819 Inst.setOpcode(ARM::t2LDRpci);
6821 case ARM::t2LDRBpcrel:
6822 Inst.setOpcode(ARM::t2LDRBpci);
6824 case ARM::t2LDRHpcrel:
6825 Inst.setOpcode(ARM::t2LDRHpci);
6827 case ARM::t2LDRSBpcrel:
6828 Inst.setOpcode(ARM::t2LDRSBpci);
6830 case ARM::t2LDRSHpcrel:
6831 Inst.setOpcode(ARM::t2LDRSHpci);
6833 // Handle NEON VST complex aliases.
6834 case ARM::VST1LNdWB_register_Asm_8:
6835 case ARM::VST1LNdWB_register_Asm_16:
6836 case ARM::VST1LNdWB_register_Asm_32: {
6838 // Shuffle the operands around so the lane index operand is in the
6841 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6842 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6843 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6844 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6845 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6846 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6847 TmpInst.addOperand(Inst.getOperand(1)); // lane
6848 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6849 TmpInst.addOperand(Inst.getOperand(6));
6854 case ARM::VST2LNdWB_register_Asm_8:
6855 case ARM::VST2LNdWB_register_Asm_16:
6856 case ARM::VST2LNdWB_register_Asm_32:
6857 case ARM::VST2LNqWB_register_Asm_16:
6858 case ARM::VST2LNqWB_register_Asm_32: {
6860 // Shuffle the operands around so the lane index operand is in the
6863 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6864 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6865 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6866 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6867 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6868 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6869 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6871 TmpInst.addOperand(Inst.getOperand(1)); // lane
6872 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6873 TmpInst.addOperand(Inst.getOperand(6));
6878 case ARM::VST3LNdWB_register_Asm_8:
6879 case ARM::VST3LNdWB_register_Asm_16:
6880 case ARM::VST3LNdWB_register_Asm_32:
6881 case ARM::VST3LNqWB_register_Asm_16:
6882 case ARM::VST3LNqWB_register_Asm_32: {
6884 // Shuffle the operands around so the lane index operand is in the
6887 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6888 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6889 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6890 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6891 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6892 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6893 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(Inst.getOperand(1)); // lane
6898 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6899 TmpInst.addOperand(Inst.getOperand(6));
6904 case ARM::VST4LNdWB_register_Asm_8:
6905 case ARM::VST4LNdWB_register_Asm_16:
6906 case ARM::VST4LNdWB_register_Asm_32:
6907 case ARM::VST4LNqWB_register_Asm_16:
6908 case ARM::VST4LNqWB_register_Asm_32: {
6910 // Shuffle the operands around so the lane index operand is in the
6913 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6914 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6915 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6916 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6917 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6919 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6925 TmpInst.addOperand(Inst.getOperand(1)); // lane
6926 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6927 TmpInst.addOperand(Inst.getOperand(6));
6932 case ARM::VST1LNdWB_fixed_Asm_8:
6933 case ARM::VST1LNdWB_fixed_Asm_16:
6934 case ARM::VST1LNdWB_fixed_Asm_32: {
6936 // Shuffle the operands around so the lane index operand is in the
6939 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6940 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6941 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6942 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6943 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6944 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6945 TmpInst.addOperand(Inst.getOperand(1)); // lane
6946 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6947 TmpInst.addOperand(Inst.getOperand(5));
6952 case ARM::VST2LNdWB_fixed_Asm_8:
6953 case ARM::VST2LNdWB_fixed_Asm_16:
6954 case ARM::VST2LNdWB_fixed_Asm_32:
6955 case ARM::VST2LNqWB_fixed_Asm_16:
6956 case ARM::VST2LNqWB_fixed_Asm_32: {
6958 // Shuffle the operands around so the lane index operand is in the
6961 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6962 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6963 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6964 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6965 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6966 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6967 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6969 TmpInst.addOperand(Inst.getOperand(1)); // lane
6970 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6971 TmpInst.addOperand(Inst.getOperand(5));
6976 case ARM::VST3LNdWB_fixed_Asm_8:
6977 case ARM::VST3LNdWB_fixed_Asm_16:
6978 case ARM::VST3LNdWB_fixed_Asm_32:
6979 case ARM::VST3LNqWB_fixed_Asm_16:
6980 case ARM::VST3LNqWB_fixed_Asm_32: {
6982 // Shuffle the operands around so the lane index operand is in the
6985 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6986 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6987 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6988 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6989 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6990 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6991 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6993 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6995 TmpInst.addOperand(Inst.getOperand(1)); // lane
6996 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6997 TmpInst.addOperand(Inst.getOperand(5));
7002 case ARM::VST4LNdWB_fixed_Asm_8:
7003 case ARM::VST4LNdWB_fixed_Asm_16:
7004 case ARM::VST4LNdWB_fixed_Asm_32:
7005 case ARM::VST4LNqWB_fixed_Asm_16:
7006 case ARM::VST4LNqWB_fixed_Asm_32: {
7008 // Shuffle the operands around so the lane index operand is in the
7011 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7012 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7013 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7014 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7015 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7016 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7017 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7019 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7021 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7023 TmpInst.addOperand(Inst.getOperand(1)); // lane
7024 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7025 TmpInst.addOperand(Inst.getOperand(5));
7030 case ARM::VST1LNdAsm_8:
7031 case ARM::VST1LNdAsm_16:
7032 case ARM::VST1LNdAsm_32: {
7034 // Shuffle the operands around so the lane index operand is in the
7037 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7038 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7039 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7040 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7041 TmpInst.addOperand(Inst.getOperand(1)); // lane
7042 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7043 TmpInst.addOperand(Inst.getOperand(5));
7048 case ARM::VST2LNdAsm_8:
7049 case ARM::VST2LNdAsm_16:
7050 case ARM::VST2LNdAsm_32:
7051 case ARM::VST2LNqAsm_16:
7052 case ARM::VST2LNqAsm_32: {
7054 // Shuffle the operands around so the lane index operand is in the
7057 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7058 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7059 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7060 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7061 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7063 TmpInst.addOperand(Inst.getOperand(1)); // lane
7064 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7065 TmpInst.addOperand(Inst.getOperand(5));
7070 case ARM::VST3LNdAsm_8:
7071 case ARM::VST3LNdAsm_16:
7072 case ARM::VST3LNdAsm_32:
7073 case ARM::VST3LNqAsm_16:
7074 case ARM::VST3LNqAsm_32: {
7076 // Shuffle the operands around so the lane index operand is in the
7079 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7080 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7081 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7082 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7083 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7085 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7087 TmpInst.addOperand(Inst.getOperand(1)); // lane
7088 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7089 TmpInst.addOperand(Inst.getOperand(5));
7094 case ARM::VST4LNdAsm_8:
7095 case ARM::VST4LNdAsm_16:
7096 case ARM::VST4LNdAsm_32:
7097 case ARM::VST4LNqAsm_16:
7098 case ARM::VST4LNqAsm_32: {
7100 // Shuffle the operands around so the lane index operand is in the
7103 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7104 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7105 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7106 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7107 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7109 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7111 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(Inst.getOperand(1)); // lane
7114 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7115 TmpInst.addOperand(Inst.getOperand(5));
7120 // Handle NEON VLD complex aliases.
7121 case ARM::VLD1LNdWB_register_Asm_8:
7122 case ARM::VLD1LNdWB_register_Asm_16:
7123 case ARM::VLD1LNdWB_register_Asm_32: {
7125 // Shuffle the operands around so the lane index operand is in the
7128 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7129 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7130 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7131 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7132 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7133 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7134 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7135 TmpInst.addOperand(Inst.getOperand(1)); // lane
7136 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7137 TmpInst.addOperand(Inst.getOperand(6));
7142 case ARM::VLD2LNdWB_register_Asm_8:
7143 case ARM::VLD2LNdWB_register_Asm_16:
7144 case ARM::VLD2LNdWB_register_Asm_32:
7145 case ARM::VLD2LNqWB_register_Asm_16:
7146 case ARM::VLD2LNqWB_register_Asm_32: {
7148 // Shuffle the operands around so the lane index operand is in the
7151 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7152 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7153 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7155 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7156 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7157 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7158 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7159 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7160 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7162 TmpInst.addOperand(Inst.getOperand(1)); // lane
7163 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7164 TmpInst.addOperand(Inst.getOperand(6));
7169 case ARM::VLD3LNdWB_register_Asm_8:
7170 case ARM::VLD3LNdWB_register_Asm_16:
7171 case ARM::VLD3LNdWB_register_Asm_32:
7172 case ARM::VLD3LNqWB_register_Asm_16:
7173 case ARM::VLD3LNqWB_register_Asm_32: {
7175 // Shuffle the operands around so the lane index operand is in the
7178 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7179 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7180 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7182 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7184 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7185 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7186 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7187 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7188 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7189 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7191 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7193 TmpInst.addOperand(Inst.getOperand(1)); // lane
7194 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7195 TmpInst.addOperand(Inst.getOperand(6));
7200 case ARM::VLD4LNdWB_register_Asm_8:
7201 case ARM::VLD4LNdWB_register_Asm_16:
7202 case ARM::VLD4LNdWB_register_Asm_32:
7203 case ARM::VLD4LNqWB_register_Asm_16:
7204 case ARM::VLD4LNqWB_register_Asm_32: {
7206 // Shuffle the operands around so the lane index operand is in the
7209 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7210 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7211 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7213 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7215 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7217 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7218 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7219 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7220 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7221 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7222 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7224 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7226 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7228 TmpInst.addOperand(Inst.getOperand(1)); // lane
7229 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7230 TmpInst.addOperand(Inst.getOperand(6));
7235 case ARM::VLD1LNdWB_fixed_Asm_8:
7236 case ARM::VLD1LNdWB_fixed_Asm_16:
7237 case ARM::VLD1LNdWB_fixed_Asm_32: {
7239 // Shuffle the operands around so the lane index operand is in the
7242 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7243 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7244 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7245 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7246 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7247 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7248 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7249 TmpInst.addOperand(Inst.getOperand(1)); // lane
7250 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7251 TmpInst.addOperand(Inst.getOperand(5));
7256 case ARM::VLD2LNdWB_fixed_Asm_8:
7257 case ARM::VLD2LNdWB_fixed_Asm_16:
7258 case ARM::VLD2LNdWB_fixed_Asm_32:
7259 case ARM::VLD2LNqWB_fixed_Asm_16:
7260 case ARM::VLD2LNqWB_fixed_Asm_32: {
7262 // Shuffle the operands around so the lane index operand is in the
7265 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7266 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7267 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7269 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7270 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7271 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7272 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7273 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7274 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7276 TmpInst.addOperand(Inst.getOperand(1)); // lane
7277 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7278 TmpInst.addOperand(Inst.getOperand(5));
7283 case ARM::VLD3LNdWB_fixed_Asm_8:
7284 case ARM::VLD3LNdWB_fixed_Asm_16:
7285 case ARM::VLD3LNdWB_fixed_Asm_32:
7286 case ARM::VLD3LNqWB_fixed_Asm_16:
7287 case ARM::VLD3LNqWB_fixed_Asm_32: {
7289 // Shuffle the operands around so the lane index operand is in the
7292 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7293 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7294 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7296 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7298 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7299 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7300 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7301 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7302 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7303 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7307 TmpInst.addOperand(Inst.getOperand(1)); // lane
7308 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7309 TmpInst.addOperand(Inst.getOperand(5));
7314 case ARM::VLD4LNdWB_fixed_Asm_8:
7315 case ARM::VLD4LNdWB_fixed_Asm_16:
7316 case ARM::VLD4LNdWB_fixed_Asm_32:
7317 case ARM::VLD4LNqWB_fixed_Asm_16:
7318 case ARM::VLD4LNqWB_fixed_Asm_32: {
7320 // Shuffle the operands around so the lane index operand is in the
7323 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7324 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7325 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7327 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7329 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7331 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7332 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7333 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7334 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7335 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7336 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7338 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7340 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(Inst.getOperand(1)); // lane
7343 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7344 TmpInst.addOperand(Inst.getOperand(5));
7349 case ARM::VLD1LNdAsm_8:
7350 case ARM::VLD1LNdAsm_16:
7351 case ARM::VLD1LNdAsm_32: {
7353 // Shuffle the operands around so the lane index operand is in the
7356 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7357 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7358 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7359 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7360 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7361 TmpInst.addOperand(Inst.getOperand(1)); // lane
7362 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7363 TmpInst.addOperand(Inst.getOperand(5));
7368 case ARM::VLD2LNdAsm_8:
7369 case ARM::VLD2LNdAsm_16:
7370 case ARM::VLD2LNdAsm_32:
7371 case ARM::VLD2LNqAsm_16:
7372 case ARM::VLD2LNqAsm_32: {
7374 // Shuffle the operands around so the lane index operand is in the
7377 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7378 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7379 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7381 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7382 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7383 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7386 TmpInst.addOperand(Inst.getOperand(1)); // lane
7387 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7388 TmpInst.addOperand(Inst.getOperand(5));
7393 case ARM::VLD3LNdAsm_8:
7394 case ARM::VLD3LNdAsm_16:
7395 case ARM::VLD3LNdAsm_32:
7396 case ARM::VLD3LNqAsm_16:
7397 case ARM::VLD3LNqAsm_32: {
7399 // Shuffle the operands around so the lane index operand is in the
7402 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7403 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7404 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7406 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7408 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7409 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7410 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7411 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7413 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7415 TmpInst.addOperand(Inst.getOperand(1)); // lane
7416 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7417 TmpInst.addOperand(Inst.getOperand(5));
7422 case ARM::VLD4LNdAsm_8:
7423 case ARM::VLD4LNdAsm_16:
7424 case ARM::VLD4LNdAsm_32:
7425 case ARM::VLD4LNqAsm_16:
7426 case ARM::VLD4LNqAsm_32: {
7428 // Shuffle the operands around so the lane index operand is in the
7431 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7432 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7435 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7437 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7439 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7440 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7441 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7442 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7444 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7446 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7448 TmpInst.addOperand(Inst.getOperand(1)); // lane
7449 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7450 TmpInst.addOperand(Inst.getOperand(5));
7455 // VLD3DUP single 3-element structure to all lanes instructions.
7456 case ARM::VLD3DUPdAsm_8:
7457 case ARM::VLD3DUPdAsm_16:
7458 case ARM::VLD3DUPdAsm_32:
7459 case ARM::VLD3DUPqAsm_8:
7460 case ARM::VLD3DUPqAsm_16:
7461 case ARM::VLD3DUPqAsm_32: {
7464 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7465 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7466 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7468 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7470 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7471 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7472 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7473 TmpInst.addOperand(Inst.getOperand(4));
7478 case ARM::VLD3DUPdWB_fixed_Asm_8:
7479 case ARM::VLD3DUPdWB_fixed_Asm_16:
7480 case ARM::VLD3DUPdWB_fixed_Asm_32:
7481 case ARM::VLD3DUPqWB_fixed_Asm_8:
7482 case ARM::VLD3DUPqWB_fixed_Asm_16:
7483 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7486 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7487 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7488 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7490 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7492 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7493 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7494 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7495 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7496 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7497 TmpInst.addOperand(Inst.getOperand(4));
7502 case ARM::VLD3DUPdWB_register_Asm_8:
7503 case ARM::VLD3DUPdWB_register_Asm_16:
7504 case ARM::VLD3DUPdWB_register_Asm_32:
7505 case ARM::VLD3DUPqWB_register_Asm_8:
7506 case ARM::VLD3DUPqWB_register_Asm_16:
7507 case ARM::VLD3DUPqWB_register_Asm_32: {
7510 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7511 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7512 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7514 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7516 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7517 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7518 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7519 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7520 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7521 TmpInst.addOperand(Inst.getOperand(5));
7526 // VLD3 multiple 3-element structure instructions.
7527 case ARM::VLD3dAsm_8:
7528 case ARM::VLD3dAsm_16:
7529 case ARM::VLD3dAsm_32:
7530 case ARM::VLD3qAsm_8:
7531 case ARM::VLD3qAsm_16:
7532 case ARM::VLD3qAsm_32: {
7535 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7536 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7537 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7539 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7541 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7542 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7543 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7544 TmpInst.addOperand(Inst.getOperand(4));
7549 case ARM::VLD3dWB_fixed_Asm_8:
7550 case ARM::VLD3dWB_fixed_Asm_16:
7551 case ARM::VLD3dWB_fixed_Asm_32:
7552 case ARM::VLD3qWB_fixed_Asm_8:
7553 case ARM::VLD3qWB_fixed_Asm_16:
7554 case ARM::VLD3qWB_fixed_Asm_32: {
7557 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7558 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7559 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7561 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7563 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7564 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7565 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7566 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7567 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7568 TmpInst.addOperand(Inst.getOperand(4));
7573 case ARM::VLD3dWB_register_Asm_8:
7574 case ARM::VLD3dWB_register_Asm_16:
7575 case ARM::VLD3dWB_register_Asm_32:
7576 case ARM::VLD3qWB_register_Asm_8:
7577 case ARM::VLD3qWB_register_Asm_16:
7578 case ARM::VLD3qWB_register_Asm_32: {
7581 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7582 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7583 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7585 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7587 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7588 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7589 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7590 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7591 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7592 TmpInst.addOperand(Inst.getOperand(5));
7597 // VLD4DUP single 3-element structure to all lanes instructions.
7598 case ARM::VLD4DUPdAsm_8:
7599 case ARM::VLD4DUPdAsm_16:
7600 case ARM::VLD4DUPdAsm_32:
7601 case ARM::VLD4DUPqAsm_8:
7602 case ARM::VLD4DUPqAsm_16:
7603 case ARM::VLD4DUPqAsm_32: {
7606 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7607 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7608 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7610 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7612 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7614 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7615 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7616 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7617 TmpInst.addOperand(Inst.getOperand(4));
7622 case ARM::VLD4DUPdWB_fixed_Asm_8:
7623 case ARM::VLD4DUPdWB_fixed_Asm_16:
7624 case ARM::VLD4DUPdWB_fixed_Asm_32:
7625 case ARM::VLD4DUPqWB_fixed_Asm_8:
7626 case ARM::VLD4DUPqWB_fixed_Asm_16:
7627 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7630 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7631 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7632 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7634 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7636 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7638 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7639 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7640 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7641 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7642 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7643 TmpInst.addOperand(Inst.getOperand(4));
7648 case ARM::VLD4DUPdWB_register_Asm_8:
7649 case ARM::VLD4DUPdWB_register_Asm_16:
7650 case ARM::VLD4DUPdWB_register_Asm_32:
7651 case ARM::VLD4DUPqWB_register_Asm_8:
7652 case ARM::VLD4DUPqWB_register_Asm_16:
7653 case ARM::VLD4DUPqWB_register_Asm_32: {
7656 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7657 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7658 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7660 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7662 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7664 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7665 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7666 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7667 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7668 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7669 TmpInst.addOperand(Inst.getOperand(5));
7674 // VLD4 multiple 4-element structure instructions.
7675 case ARM::VLD4dAsm_8:
7676 case ARM::VLD4dAsm_16:
7677 case ARM::VLD4dAsm_32:
7678 case ARM::VLD4qAsm_8:
7679 case ARM::VLD4qAsm_16:
7680 case ARM::VLD4qAsm_32: {
7683 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7684 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7685 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7687 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7689 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7691 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7692 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7693 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7694 TmpInst.addOperand(Inst.getOperand(4));
7699 case ARM::VLD4dWB_fixed_Asm_8:
7700 case ARM::VLD4dWB_fixed_Asm_16:
7701 case ARM::VLD4dWB_fixed_Asm_32:
7702 case ARM::VLD4qWB_fixed_Asm_8:
7703 case ARM::VLD4qWB_fixed_Asm_16:
7704 case ARM::VLD4qWB_fixed_Asm_32: {
7707 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7708 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7709 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7711 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7713 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7715 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7716 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7717 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7718 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7719 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7720 TmpInst.addOperand(Inst.getOperand(4));
7725 case ARM::VLD4dWB_register_Asm_8:
7726 case ARM::VLD4dWB_register_Asm_16:
7727 case ARM::VLD4dWB_register_Asm_32:
7728 case ARM::VLD4qWB_register_Asm_8:
7729 case ARM::VLD4qWB_register_Asm_16:
7730 case ARM::VLD4qWB_register_Asm_32: {
7733 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7734 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7735 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7737 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7739 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7741 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7742 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7743 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7744 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7745 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7746 TmpInst.addOperand(Inst.getOperand(5));
7751 // VST3 multiple 3-element structure instructions.
7752 case ARM::VST3dAsm_8:
7753 case ARM::VST3dAsm_16:
7754 case ARM::VST3dAsm_32:
7755 case ARM::VST3qAsm_8:
7756 case ARM::VST3qAsm_16:
7757 case ARM::VST3qAsm_32: {
7760 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7761 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7762 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7763 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7764 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7766 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7768 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7769 TmpInst.addOperand(Inst.getOperand(4));
7774 case ARM::VST3dWB_fixed_Asm_8:
7775 case ARM::VST3dWB_fixed_Asm_16:
7776 case ARM::VST3dWB_fixed_Asm_32:
7777 case ARM::VST3qWB_fixed_Asm_8:
7778 case ARM::VST3qWB_fixed_Asm_16:
7779 case ARM::VST3qWB_fixed_Asm_32: {
7782 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7783 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7784 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7785 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7786 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7787 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7788 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7790 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7792 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7793 TmpInst.addOperand(Inst.getOperand(4));
7798 case ARM::VST3dWB_register_Asm_8:
7799 case ARM::VST3dWB_register_Asm_16:
7800 case ARM::VST3dWB_register_Asm_32:
7801 case ARM::VST3qWB_register_Asm_8:
7802 case ARM::VST3qWB_register_Asm_16:
7803 case ARM::VST3qWB_register_Asm_32: {
7806 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7807 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7808 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7809 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7810 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7811 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7812 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7814 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7816 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7817 TmpInst.addOperand(Inst.getOperand(5));
7822 // VST4 multiple 3-element structure instructions.
7823 case ARM::VST4dAsm_8:
7824 case ARM::VST4dAsm_16:
7825 case ARM::VST4dAsm_32:
7826 case ARM::VST4qAsm_8:
7827 case ARM::VST4qAsm_16:
7828 case ARM::VST4qAsm_32: {
7831 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7832 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7833 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7834 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7835 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7837 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7839 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7841 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7842 TmpInst.addOperand(Inst.getOperand(4));
7847 case ARM::VST4dWB_fixed_Asm_8:
7848 case ARM::VST4dWB_fixed_Asm_16:
7849 case ARM::VST4dWB_fixed_Asm_32:
7850 case ARM::VST4qWB_fixed_Asm_8:
7851 case ARM::VST4qWB_fixed_Asm_16:
7852 case ARM::VST4qWB_fixed_Asm_32: {
7855 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7856 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7857 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7858 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7859 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7860 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7861 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7863 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7865 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7867 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7868 TmpInst.addOperand(Inst.getOperand(4));
7873 case ARM::VST4dWB_register_Asm_8:
7874 case ARM::VST4dWB_register_Asm_16:
7875 case ARM::VST4dWB_register_Asm_32:
7876 case ARM::VST4qWB_register_Asm_8:
7877 case ARM::VST4qWB_register_Asm_16:
7878 case ARM::VST4qWB_register_Asm_32: {
7881 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7882 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7883 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7884 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7885 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7886 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7887 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7889 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7891 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7893 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7894 TmpInst.addOperand(Inst.getOperand(5));
7899 // Handle encoding choice for the shift-immediate instructions.
7902 case ARM::t2ASRri: {
7903 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7904 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7905 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7906 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7907 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7909 switch (Inst.getOpcode()) {
7910 default: llvm_unreachable("unexpected opcode");
7911 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7912 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7913 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7915 // The Thumb1 operands aren't in the same order. Awesome, eh?
7917 TmpInst.setOpcode(NewOpc);
7918 TmpInst.addOperand(Inst.getOperand(0));
7919 TmpInst.addOperand(Inst.getOperand(5));
7920 TmpInst.addOperand(Inst.getOperand(1));
7921 TmpInst.addOperand(Inst.getOperand(2));
7922 TmpInst.addOperand(Inst.getOperand(3));
7923 TmpInst.addOperand(Inst.getOperand(4));
7930 // Handle the Thumb2 mode MOV complex aliases.
7932 case ARM::t2MOVSsr: {
7933 // Which instruction to expand to depends on the CCOut operand and
7934 // whether we're in an IT block if the register operands are low
7936 bool isNarrow = false;
7937 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7938 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7939 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7940 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7941 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7945 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7946 default: llvm_unreachable("unexpected opcode!");
7947 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7948 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7949 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7950 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7952 TmpInst.setOpcode(newOpc);
7953 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7955 TmpInst.addOperand(MCOperand::createReg(
7956 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7957 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7958 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7959 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7960 TmpInst.addOperand(Inst.getOperand(5));
7962 TmpInst.addOperand(MCOperand::createReg(
7963 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7968 case ARM::t2MOVSsi: {
7969 // Which instruction to expand to depends on the CCOut operand and
7970 // whether we're in an IT block if the register operands are low
7972 bool isNarrow = false;
7973 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7974 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7975 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7979 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7980 default: llvm_unreachable("unexpected opcode!");
7981 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7982 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7983 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7984 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7985 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7987 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7988 if (Amount == 32) Amount = 0;
7989 TmpInst.setOpcode(newOpc);
7990 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7992 TmpInst.addOperand(MCOperand::createReg(
7993 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7994 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7995 if (newOpc != ARM::t2RRX)
7996 TmpInst.addOperand(MCOperand::createImm(Amount));
7997 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7998 TmpInst.addOperand(Inst.getOperand(4));
8000 TmpInst.addOperand(MCOperand::createReg(
8001 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8005 // Handle the ARM mode MOV complex aliases.
8010 ARM_AM::ShiftOpc ShiftTy;
8011 switch(Inst.getOpcode()) {
8012 default: llvm_unreachable("unexpected opcode!");
8013 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
8014 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
8015 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
8016 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
8018 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
8020 TmpInst.setOpcode(ARM::MOVsr);
8021 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8022 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8023 TmpInst.addOperand(Inst.getOperand(2)); // Rm
8024 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8025 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8026 TmpInst.addOperand(Inst.getOperand(4));
8027 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8035 ARM_AM::ShiftOpc ShiftTy;
8036 switch(Inst.getOpcode()) {
8037 default: llvm_unreachable("unexpected opcode!");
8038 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8039 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8040 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8041 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8043 // A shift by zero is a plain MOVr, not a MOVsi.
8044 unsigned Amt = Inst.getOperand(2).getImm();
8045 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8046 // A shift by 32 should be encoded as 0 when permitted
8047 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8049 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8051 TmpInst.setOpcode(Opc);
8052 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8053 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8054 if (Opc == ARM::MOVsi)
8055 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8056 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8057 TmpInst.addOperand(Inst.getOperand(4));
8058 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8063 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8065 TmpInst.setOpcode(ARM::MOVsi);
8066 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8067 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8068 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8069 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8070 TmpInst.addOperand(Inst.getOperand(3));
8071 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8075 case ARM::t2LDMIA_UPD: {
8076 // If this is a load of a single register, then we should use
8077 // a post-indexed LDR instruction instead, per the ARM ARM.
8078 if (Inst.getNumOperands() != 5)
8081 TmpInst.setOpcode(ARM::t2LDR_POST);
8082 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8083 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8084 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8085 TmpInst.addOperand(MCOperand::createImm(4));
8086 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8087 TmpInst.addOperand(Inst.getOperand(3));
8091 case ARM::t2STMDB_UPD: {
8092 // If this is a store of a single register, then we should use
8093 // a pre-indexed STR instruction instead, per the ARM ARM.
8094 if (Inst.getNumOperands() != 5)
8097 TmpInst.setOpcode(ARM::t2STR_PRE);
8098 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8099 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8100 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8101 TmpInst.addOperand(MCOperand::createImm(-4));
8102 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8103 TmpInst.addOperand(Inst.getOperand(3));
8107 case ARM::LDMIA_UPD:
8108 // If this is a load of a single register via a 'pop', then we should use
8109 // a post-indexed LDR instruction instead, per the ARM ARM.
8110 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8111 Inst.getNumOperands() == 5) {
8113 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8114 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8115 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8116 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8117 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
8118 TmpInst.addOperand(MCOperand::createImm(4));
8119 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8120 TmpInst.addOperand(Inst.getOperand(3));
8125 case ARM::STMDB_UPD:
8126 // If this is a store of a single register via a 'push', then we should use
8127 // a pre-indexed STR instruction instead, per the ARM ARM.
8128 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8129 Inst.getNumOperands() == 5) {
8131 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8132 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8133 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8134 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8135 TmpInst.addOperand(MCOperand::createImm(-4));
8136 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8137 TmpInst.addOperand(Inst.getOperand(3));
8141 case ARM::t2ADDri12:
8142 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8143 // mnemonic was used (not "addw"), encoding T3 is preferred.
8144 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8145 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8147 Inst.setOpcode(ARM::t2ADDri);
8148 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8150 case ARM::t2SUBri12:
8151 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8152 // mnemonic was used (not "subw"), encoding T3 is preferred.
8153 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8154 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8156 Inst.setOpcode(ARM::t2SUBri);
8157 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8160 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8161 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8162 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8163 // to encoding T1 if <Rd> is omitted."
8164 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8165 Inst.setOpcode(ARM::tADDi3);
8170 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8171 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8172 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8173 // to encoding T1 if <Rd> is omitted."
8174 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8175 Inst.setOpcode(ARM::tSUBi3);
8180 case ARM::t2SUBri: {
8181 // If the destination and first source operand are the same, and
8182 // the flags are compatible with the current IT status, use encoding T2
8183 // instead of T3. For compatibility with the system 'as'. Make sure the
8184 // wide encoding wasn't explicit.
8185 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8186 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8187 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8188 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8189 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8190 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8191 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8194 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8195 ARM::tADDi8 : ARM::tSUBi8);
8196 TmpInst.addOperand(Inst.getOperand(0));
8197 TmpInst.addOperand(Inst.getOperand(5));
8198 TmpInst.addOperand(Inst.getOperand(0));
8199 TmpInst.addOperand(Inst.getOperand(2));
8200 TmpInst.addOperand(Inst.getOperand(3));
8201 TmpInst.addOperand(Inst.getOperand(4));
8205 case ARM::t2ADDrr: {
8206 // If the destination and first source operand are the same, and
8207 // there's no setting of the flags, use encoding T2 instead of T3.
8208 // Note that this is only for ADD, not SUB. This mirrors the system
8209 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
8210 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8211 Inst.getOperand(5).getReg() != 0 ||
8212 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8213 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8216 TmpInst.setOpcode(ARM::tADDhirr);
8217 TmpInst.addOperand(Inst.getOperand(0));
8218 TmpInst.addOperand(Inst.getOperand(0));
8219 TmpInst.addOperand(Inst.getOperand(2));
8220 TmpInst.addOperand(Inst.getOperand(3));
8221 TmpInst.addOperand(Inst.getOperand(4));
8225 case ARM::tADDrSP: {
8226 // If the non-SP source operand and the destination operand are not the
8227 // same, we need to use the 32-bit encoding if it's available.
8228 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8229 Inst.setOpcode(ARM::t2ADDrr);
8230 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8236 // A Thumb conditional branch outside of an IT block is a tBcc.
8237 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8238 Inst.setOpcode(ARM::tBcc);
8243 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8244 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8245 Inst.setOpcode(ARM::t2Bcc);
8250 // If the conditional is AL or we're in an IT block, we really want t2B.
8251 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8252 Inst.setOpcode(ARM::t2B);
8257 // If the conditional is AL, we really want tB.
8258 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8259 Inst.setOpcode(ARM::tB);
8264 // If the register list contains any high registers, or if the writeback
8265 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8266 // instead if we're in Thumb2. Otherwise, this should have generated
8267 // an error in validateInstruction().
8268 unsigned Rn = Inst.getOperand(0).getReg();
8269 bool hasWritebackToken =
8270 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8271 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8272 bool listContainsBase;
8273 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8274 (!listContainsBase && !hasWritebackToken) ||
8275 (listContainsBase && hasWritebackToken)) {
8276 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8277 assert (isThumbTwo());
8278 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8279 // If we're switching to the updating version, we need to insert
8280 // the writeback tied operand.
8281 if (hasWritebackToken)
8282 Inst.insert(Inst.begin(),
8283 MCOperand::createReg(Inst.getOperand(0).getReg()));
8288 case ARM::tSTMIA_UPD: {
8289 // If the register list contains any high registers, we need to use
8290 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8291 // should have generated an error in validateInstruction().
8292 unsigned Rn = Inst.getOperand(0).getReg();
8293 bool listContainsBase;
8294 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8295 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8296 assert (isThumbTwo());
8297 Inst.setOpcode(ARM::t2STMIA_UPD);
8303 bool listContainsBase;
8304 // If the register list contains any high registers, we need to use
8305 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8306 // should have generated an error in validateInstruction().
8307 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8309 assert (isThumbTwo());
8310 Inst.setOpcode(ARM::t2LDMIA_UPD);
8311 // Add the base register and writeback operands.
8312 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8313 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8317 bool listContainsBase;
8318 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8320 assert (isThumbTwo());
8321 Inst.setOpcode(ARM::t2STMDB_UPD);
8322 // Add the base register and writeback operands.
8323 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8324 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8328 // If we can use the 16-bit encoding and the user didn't explicitly
8329 // request the 32-bit variant, transform it here.
8330 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8331 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8332 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8333 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8334 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8335 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8336 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8337 // The operands aren't in the same order for tMOVi8...
8339 TmpInst.setOpcode(ARM::tMOVi8);
8340 TmpInst.addOperand(Inst.getOperand(0));
8341 TmpInst.addOperand(Inst.getOperand(4));
8342 TmpInst.addOperand(Inst.getOperand(1));
8343 TmpInst.addOperand(Inst.getOperand(2));
8344 TmpInst.addOperand(Inst.getOperand(3));
8351 // If we can use the 16-bit encoding and the user didn't explicitly
8352 // request the 32-bit variant, transform it here.
8353 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8354 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8355 Inst.getOperand(2).getImm() == ARMCC::AL &&
8356 Inst.getOperand(4).getReg() == ARM::CPSR &&
8357 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8358 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8359 // The operands aren't the same for tMOV[S]r... (no cc_out)
8361 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8362 TmpInst.addOperand(Inst.getOperand(0));
8363 TmpInst.addOperand(Inst.getOperand(1));
8364 TmpInst.addOperand(Inst.getOperand(2));
8365 TmpInst.addOperand(Inst.getOperand(3));
8375 // If we can use the 16-bit encoding and the user didn't explicitly
8376 // request the 32-bit variant, transform it here.
8377 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8378 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8379 Inst.getOperand(2).getImm() == 0 &&
8380 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8381 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8383 switch (Inst.getOpcode()) {
8384 default: llvm_unreachable("Illegal opcode!");
8385 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8386 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8387 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8388 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8390 // The operands aren't the same for thumb1 (no rotate operand).
8392 TmpInst.setOpcode(NewOpc);
8393 TmpInst.addOperand(Inst.getOperand(0));
8394 TmpInst.addOperand(Inst.getOperand(1));
8395 TmpInst.addOperand(Inst.getOperand(3));
8396 TmpInst.addOperand(Inst.getOperand(4));
8403 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8404 // rrx shifts and asr/lsr of #32 is encoded as 0
8405 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8407 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8408 // Shifting by zero is accepted as a vanilla 'MOVr'
8410 TmpInst.setOpcode(ARM::MOVr);
8411 TmpInst.addOperand(Inst.getOperand(0));
8412 TmpInst.addOperand(Inst.getOperand(1));
8413 TmpInst.addOperand(Inst.getOperand(3));
8414 TmpInst.addOperand(Inst.getOperand(4));
8415 TmpInst.addOperand(Inst.getOperand(5));
8428 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8429 if (SOpc == ARM_AM::rrx) return false;
8430 switch (Inst.getOpcode()) {
8431 default: llvm_unreachable("unexpected opcode!");
8432 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8433 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8434 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8435 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8436 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8437 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8439 // If the shift is by zero, use the non-shifted instruction definition.
8440 // The exception is for right shifts, where 0 == 32
8441 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8442 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8444 TmpInst.setOpcode(newOpc);
8445 TmpInst.addOperand(Inst.getOperand(0));
8446 TmpInst.addOperand(Inst.getOperand(1));
8447 TmpInst.addOperand(Inst.getOperand(2));
8448 TmpInst.addOperand(Inst.getOperand(4));
8449 TmpInst.addOperand(Inst.getOperand(5));
8450 TmpInst.addOperand(Inst.getOperand(6));
8458 // The mask bits for all but the first condition are represented as
8459 // the low bit of the condition code value implies 't'. We currently
8460 // always have 1 implies 't', so XOR toggle the bits if the low bit
8461 // of the condition code is zero.
8462 MCOperand &MO = Inst.getOperand(1);
8463 unsigned Mask = MO.getImm();
8464 unsigned OrigMask = Mask;
8465 unsigned TZ = countTrailingZeros(Mask);
8466 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8467 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8468 Mask ^= (0xE << TZ) & 0xF;
8472 // Set up the IT block state according to the IT instruction we just
8474 assert(!inITBlock() && "nested IT blocks?!");
8475 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8476 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8477 ITState.CurPosition = 0;
8478 ITState.FirstCond = true;
8488 // Assemblers should use the narrow encodings of these instructions when permissible.
8489 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8490 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8491 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8492 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8493 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8494 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8495 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8498 switch (Inst.getOpcode()) {
8499 default: llvm_unreachable("unexpected opcode");
8500 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8501 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8502 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8503 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8504 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8505 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8508 TmpInst.setOpcode(NewOpc);
8509 TmpInst.addOperand(Inst.getOperand(0));
8510 TmpInst.addOperand(Inst.getOperand(5));
8511 TmpInst.addOperand(Inst.getOperand(1));
8512 TmpInst.addOperand(Inst.getOperand(2));
8513 TmpInst.addOperand(Inst.getOperand(3));
8514 TmpInst.addOperand(Inst.getOperand(4));
8525 // Assemblers should use the narrow encodings of these instructions when permissible.
8526 // These instructions are special in that they are commutable, so shorter encodings
8527 // are available more often.
8528 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8529 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8530 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8531 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8532 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8533 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8534 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8535 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8538 switch (Inst.getOpcode()) {
8539 default: llvm_unreachable("unexpected opcode");
8540 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8541 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8542 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8543 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8546 TmpInst.setOpcode(NewOpc);
8547 TmpInst.addOperand(Inst.getOperand(0));
8548 TmpInst.addOperand(Inst.getOperand(5));
8549 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8550 TmpInst.addOperand(Inst.getOperand(1));
8551 TmpInst.addOperand(Inst.getOperand(2));
8553 TmpInst.addOperand(Inst.getOperand(2));
8554 TmpInst.addOperand(Inst.getOperand(1));
8556 TmpInst.addOperand(Inst.getOperand(3));
8557 TmpInst.addOperand(Inst.getOperand(4));
8567 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8568 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8569 // suffix depending on whether they're in an IT block or not.
8570 unsigned Opc = Inst.getOpcode();
8571 const MCInstrDesc &MCID = MII.get(Opc);
8572 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8573 assert(MCID.hasOptionalDef() &&
8574 "optionally flag setting instruction missing optional def operand");
8575 assert(MCID.NumOperands == Inst.getNumOperands() &&
8576 "operand count mismatch!");
8577 // Find the optional-def operand (cc_out).
8580 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8583 // If we're parsing Thumb1, reject it completely.
8584 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8585 return Match_MnemonicFail;
8586 // If we're parsing Thumb2, which form is legal depends on whether we're
8588 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8590 return Match_RequiresITBlock;
8591 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8593 return Match_RequiresNotITBlock;
8595 // Some high-register supporting Thumb1 encodings only allow both registers
8596 // to be from r0-r7 when in Thumb2.
8597 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8598 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8599 isARMLowRegister(Inst.getOperand(2).getReg()))
8600 return Match_RequiresThumb2;
8601 // Others only require ARMv6 or later.
8602 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8603 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8604 isARMLowRegister(Inst.getOperand(1).getReg()))
8605 return Match_RequiresV6;
8606 return Match_Success;
8610 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8611 return true; // In an assembly source, no need to second-guess
8615 static const char *getSubtargetFeatureName(uint64_t Val);
8616 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8617 OperandVector &Operands,
8618 MCStreamer &Out, uint64_t &ErrorInfo,
8619 bool MatchingInlineAsm) {
8621 unsigned MatchResult;
8623 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8625 switch (MatchResult) {
8627 // Context sensitive operand constraints aren't handled by the matcher,
8628 // so check them here.
8629 if (validateInstruction(Inst, Operands)) {
8630 // Still progress the IT block, otherwise one wrong condition causes
8631 // nasty cascading errors.
8632 forwardITPosition();
8636 { // processInstruction() updates inITBlock state, we need to save it away
8637 bool wasInITBlock = inITBlock();
8639 // Some instructions need post-processing to, for example, tweak which
8640 // encoding is selected. Loop on it while changes happen so the
8641 // individual transformations can chain off each other. E.g.,
8642 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8643 while (processInstruction(Inst, Operands, Out))
8646 // Only after the instruction is fully processed, we can validate it
8647 if (wasInITBlock && hasV8Ops() && isThumb() &&
8648 !isV8EligibleForIT(&Inst)) {
8649 Warning(IDLoc, "deprecated instruction in IT block");
8653 // Only move forward at the very end so that everything in validate
8654 // and process gets a consistent answer about whether we're in an IT
8656 forwardITPosition();
8658 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8659 // doesn't actually encode.
8660 if (Inst.getOpcode() == ARM::ITasm)
8664 Out.EmitInstruction(Inst, STI);
8666 case Match_MissingFeature: {
8667 assert(ErrorInfo && "Unknown missing feature!");
8668 // Special case the error message for the very common case where only
8669 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8670 std::string Msg = "instruction requires:";
8672 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8673 if (ErrorInfo & Mask) {
8675 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8679 return Error(IDLoc, Msg);
8681 case Match_InvalidOperand: {
8682 SMLoc ErrorLoc = IDLoc;
8683 if (ErrorInfo != ~0ULL) {
8684 if (ErrorInfo >= Operands.size())
8685 return Error(IDLoc, "too few operands for instruction");
8687 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8688 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8691 return Error(ErrorLoc, "invalid operand for instruction");
8693 case Match_MnemonicFail:
8694 return Error(IDLoc, "invalid instruction",
8695 ((ARMOperand &)*Operands[0]).getLocRange());
8696 case Match_RequiresNotITBlock:
8697 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8698 case Match_RequiresITBlock:
8699 return Error(IDLoc, "instruction only valid inside IT block");
8700 case Match_RequiresV6:
8701 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8702 case Match_RequiresThumb2:
8703 return Error(IDLoc, "instruction variant requires Thumb2");
8704 case Match_ImmRange0_15: {
8705 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8706 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8707 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8709 case Match_ImmRange0_239: {
8710 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8711 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8712 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8714 case Match_AlignedMemoryRequiresNone:
8715 case Match_DupAlignedMemoryRequiresNone:
8716 case Match_AlignedMemoryRequires16:
8717 case Match_DupAlignedMemoryRequires16:
8718 case Match_AlignedMemoryRequires32:
8719 case Match_DupAlignedMemoryRequires32:
8720 case Match_AlignedMemoryRequires64:
8721 case Match_DupAlignedMemoryRequires64:
8722 case Match_AlignedMemoryRequires64or128:
8723 case Match_DupAlignedMemoryRequires64or128:
8724 case Match_AlignedMemoryRequires64or128or256:
8726 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8727 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8728 switch (MatchResult) {
8730 llvm_unreachable("Missing Match_Aligned type");
8731 case Match_AlignedMemoryRequiresNone:
8732 case Match_DupAlignedMemoryRequiresNone:
8733 return Error(ErrorLoc, "alignment must be omitted");
8734 case Match_AlignedMemoryRequires16:
8735 case Match_DupAlignedMemoryRequires16:
8736 return Error(ErrorLoc, "alignment must be 16 or omitted");
8737 case Match_AlignedMemoryRequires32:
8738 case Match_DupAlignedMemoryRequires32:
8739 return Error(ErrorLoc, "alignment must be 32 or omitted");
8740 case Match_AlignedMemoryRequires64:
8741 case Match_DupAlignedMemoryRequires64:
8742 return Error(ErrorLoc, "alignment must be 64 or omitted");
8743 case Match_AlignedMemoryRequires64or128:
8744 case Match_DupAlignedMemoryRequires64or128:
8745 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8746 case Match_AlignedMemoryRequires64or128or256:
8747 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8752 llvm_unreachable("Implement any new match types added!");
8755 /// parseDirective parses the arm specific directives
8756 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8757 const MCObjectFileInfo::Environment Format =
8758 getContext().getObjectFileInfo()->getObjectFileType();
8759 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8760 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8762 StringRef IDVal = DirectiveID.getIdentifier();
8763 if (IDVal == ".word")
8764 return parseLiteralValues(4, DirectiveID.getLoc());
8765 else if (IDVal == ".short" || IDVal == ".hword")
8766 return parseLiteralValues(2, DirectiveID.getLoc());
8767 else if (IDVal == ".thumb")
8768 return parseDirectiveThumb(DirectiveID.getLoc());
8769 else if (IDVal == ".arm")
8770 return parseDirectiveARM(DirectiveID.getLoc());
8771 else if (IDVal == ".thumb_func")
8772 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8773 else if (IDVal == ".code")
8774 return parseDirectiveCode(DirectiveID.getLoc());
8775 else if (IDVal == ".syntax")
8776 return parseDirectiveSyntax(DirectiveID.getLoc());
8777 else if (IDVal == ".unreq")
8778 return parseDirectiveUnreq(DirectiveID.getLoc());
8779 else if (IDVal == ".fnend")
8780 return parseDirectiveFnEnd(DirectiveID.getLoc());
8781 else if (IDVal == ".cantunwind")
8782 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8783 else if (IDVal == ".personality")
8784 return parseDirectivePersonality(DirectiveID.getLoc());
8785 else if (IDVal == ".handlerdata")
8786 return parseDirectiveHandlerData(DirectiveID.getLoc());
8787 else if (IDVal == ".setfp")
8788 return parseDirectiveSetFP(DirectiveID.getLoc());
8789 else if (IDVal == ".pad")
8790 return parseDirectivePad(DirectiveID.getLoc());
8791 else if (IDVal == ".save")
8792 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8793 else if (IDVal == ".vsave")
8794 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8795 else if (IDVal == ".ltorg" || IDVal == ".pool")
8796 return parseDirectiveLtorg(DirectiveID.getLoc());
8797 else if (IDVal == ".even")
8798 return parseDirectiveEven(DirectiveID.getLoc());
8799 else if (IDVal == ".personalityindex")
8800 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8801 else if (IDVal == ".unwind_raw")
8802 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8803 else if (IDVal == ".movsp")
8804 return parseDirectiveMovSP(DirectiveID.getLoc());
8805 else if (IDVal == ".arch_extension")
8806 return parseDirectiveArchExtension(DirectiveID.getLoc());
8807 else if (IDVal == ".align")
8808 return parseDirectiveAlign(DirectiveID.getLoc());
8809 else if (IDVal == ".thumb_set")
8810 return parseDirectiveThumbSet(DirectiveID.getLoc());
8812 if (!IsMachO && !IsCOFF) {
8813 if (IDVal == ".arch")
8814 return parseDirectiveArch(DirectiveID.getLoc());
8815 else if (IDVal == ".cpu")
8816 return parseDirectiveCPU(DirectiveID.getLoc());
8817 else if (IDVal == ".eabi_attribute")
8818 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8819 else if (IDVal == ".fpu")
8820 return parseDirectiveFPU(DirectiveID.getLoc());
8821 else if (IDVal == ".fnstart")
8822 return parseDirectiveFnStart(DirectiveID.getLoc());
8823 else if (IDVal == ".inst")
8824 return parseDirectiveInst(DirectiveID.getLoc());
8825 else if (IDVal == ".inst.n")
8826 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8827 else if (IDVal == ".inst.w")
8828 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8829 else if (IDVal == ".object_arch")
8830 return parseDirectiveObjectArch(DirectiveID.getLoc());
8831 else if (IDVal == ".tlsdescseq")
8832 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8838 /// parseLiteralValues
8839 /// ::= .hword expression [, expression]*
8840 /// ::= .short expression [, expression]*
8841 /// ::= .word expression [, expression]*
8842 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8843 MCAsmParser &Parser = getParser();
8844 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8846 const MCExpr *Value;
8847 if (getParser().parseExpression(Value)) {
8848 Parser.eatToEndOfStatement();
8852 getParser().getStreamer().EmitValue(Value, Size);
8854 if (getLexer().is(AsmToken::EndOfStatement))
8857 // FIXME: Improve diagnostic.
8858 if (getLexer().isNot(AsmToken::Comma)) {
8859 Error(L, "unexpected token in directive");
8870 /// parseDirectiveThumb
8872 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8873 MCAsmParser &Parser = getParser();
8874 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8875 Error(L, "unexpected token in directive");
8881 Error(L, "target does not support Thumb mode");
8888 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8892 /// parseDirectiveARM
8894 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8895 MCAsmParser &Parser = getParser();
8896 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8897 Error(L, "unexpected token in directive");
8903 Error(L, "target does not support ARM mode");
8910 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8914 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8915 if (NextSymbolIsThumb) {
8916 getParser().getStreamer().EmitThumbFunc(Symbol);
8917 NextSymbolIsThumb = false;
8921 /// parseDirectiveThumbFunc
8922 /// ::= .thumbfunc symbol_name
8923 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8924 MCAsmParser &Parser = getParser();
8925 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8926 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8928 // Darwin asm has (optionally) function name after .thumb_func direction
8931 const AsmToken &Tok = Parser.getTok();
8932 if (Tok.isNot(AsmToken::EndOfStatement)) {
8933 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8934 Error(L, "unexpected token in .thumb_func directive");
8939 getParser().getContext().getOrCreateSymbol(Tok.getIdentifier());
8940 getParser().getStreamer().EmitThumbFunc(Func);
8941 Parser.Lex(); // Consume the identifier token.
8946 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8947 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8948 Parser.eatToEndOfStatement();
8952 NextSymbolIsThumb = true;
8956 /// parseDirectiveSyntax
8957 /// ::= .syntax unified | divided
8958 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8959 MCAsmParser &Parser = getParser();
8960 const AsmToken &Tok = Parser.getTok();
8961 if (Tok.isNot(AsmToken::Identifier)) {
8962 Error(L, "unexpected token in .syntax directive");
8966 StringRef Mode = Tok.getString();
8967 if (Mode == "unified" || Mode == "UNIFIED") {
8969 } else if (Mode == "divided" || Mode == "DIVIDED") {
8970 Error(L, "'.syntax divided' arm asssembly not supported");
8973 Error(L, "unrecognized syntax mode in .syntax directive");
8977 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8978 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8983 // TODO tell the MC streamer the mode
8984 // getParser().getStreamer().Emit???();
8988 /// parseDirectiveCode
8989 /// ::= .code 16 | 32
8990 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8991 MCAsmParser &Parser = getParser();
8992 const AsmToken &Tok = Parser.getTok();
8993 if (Tok.isNot(AsmToken::Integer)) {
8994 Error(L, "unexpected token in .code directive");
8997 int64_t Val = Parser.getTok().getIntVal();
8998 if (Val != 16 && Val != 32) {
8999 Error(L, "invalid operand to .code directive");
9004 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9005 Error(Parser.getTok().getLoc(), "unexpected token in directive");
9012 Error(L, "target does not support Thumb mode");
9018 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9021 Error(L, "target does not support ARM mode");
9027 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9033 /// parseDirectiveReq
9034 /// ::= name .req registername
9035 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9036 MCAsmParser &Parser = getParser();
9037 Parser.Lex(); // Eat the '.req' token.
9039 SMLoc SRegLoc, ERegLoc;
9040 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
9041 Parser.eatToEndOfStatement();
9042 Error(SRegLoc, "register name expected");
9046 // Shouldn't be anything else.
9047 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9048 Parser.eatToEndOfStatement();
9049 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9053 Parser.Lex(); // Consume the EndOfStatement
9055 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
9056 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9063 /// parseDirectiveUneq
9064 /// ::= .unreq registername
9065 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9066 MCAsmParser &Parser = getParser();
9067 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9068 Parser.eatToEndOfStatement();
9069 Error(L, "unexpected input in .unreq directive.");
9072 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9073 Parser.Lex(); // Eat the identifier.
9077 /// parseDirectiveArch
9079 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9080 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9082 unsigned ID = ARMTargetParser::parseArch(Arch);
9084 if (ID == ARM::AK_INVALID) {
9085 Error(L, "Unknown arch name");
9089 getTargetStreamer().emitArch(ID);
9093 /// parseDirectiveEabiAttr
9094 /// ::= .eabi_attribute int, int [, "str"]
9095 /// ::= .eabi_attribute Tag_name, int [, "str"]
9096 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9097 MCAsmParser &Parser = getParser();
9100 TagLoc = Parser.getTok().getLoc();
9101 if (Parser.getTok().is(AsmToken::Identifier)) {
9102 StringRef Name = Parser.getTok().getIdentifier();
9103 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9105 Error(TagLoc, "attribute name not recognised: " + Name);
9106 Parser.eatToEndOfStatement();
9111 const MCExpr *AttrExpr;
9113 TagLoc = Parser.getTok().getLoc();
9114 if (Parser.parseExpression(AttrExpr)) {
9115 Parser.eatToEndOfStatement();
9119 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9121 Error(TagLoc, "expected numeric constant");
9122 Parser.eatToEndOfStatement();
9126 Tag = CE->getValue();
9129 if (Parser.getTok().isNot(AsmToken::Comma)) {
9130 Error(Parser.getTok().getLoc(), "comma expected");
9131 Parser.eatToEndOfStatement();
9134 Parser.Lex(); // skip comma
9136 StringRef StringValue = "";
9137 bool IsStringValue = false;
9139 int64_t IntegerValue = 0;
9140 bool IsIntegerValue = false;
9142 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9143 IsStringValue = true;
9144 else if (Tag == ARMBuildAttrs::compatibility) {
9145 IsStringValue = true;
9146 IsIntegerValue = true;
9147 } else if (Tag < 32 || Tag % 2 == 0)
9148 IsIntegerValue = true;
9149 else if (Tag % 2 == 1)
9150 IsStringValue = true;
9152 llvm_unreachable("invalid tag type");
9154 if (IsIntegerValue) {
9155 const MCExpr *ValueExpr;
9156 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9157 if (Parser.parseExpression(ValueExpr)) {
9158 Parser.eatToEndOfStatement();
9162 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9164 Error(ValueExprLoc, "expected numeric constant");
9165 Parser.eatToEndOfStatement();
9169 IntegerValue = CE->getValue();
9172 if (Tag == ARMBuildAttrs::compatibility) {
9173 if (Parser.getTok().isNot(AsmToken::Comma))
9174 IsStringValue = false;
9175 if (Parser.getTok().isNot(AsmToken::Comma)) {
9176 Error(Parser.getTok().getLoc(), "comma expected");
9177 Parser.eatToEndOfStatement();
9184 if (IsStringValue) {
9185 if (Parser.getTok().isNot(AsmToken::String)) {
9186 Error(Parser.getTok().getLoc(), "bad string constant");
9187 Parser.eatToEndOfStatement();
9191 StringValue = Parser.getTok().getStringContents();
9195 if (IsIntegerValue && IsStringValue) {
9196 assert(Tag == ARMBuildAttrs::compatibility);
9197 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9198 } else if (IsIntegerValue)
9199 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9200 else if (IsStringValue)
9201 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9205 /// parseDirectiveCPU
9207 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9208 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9209 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9211 // FIXME: This is using table-gen data, but should be moved to
9212 // ARMTargetParser once that is table-gen'd.
9213 if (!STI.isCPUStringValid(CPU)) {
9214 Error(L, "Unknown CPU name");
9218 STI.setDefaultFeatures(CPU);
9219 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9223 /// parseDirectiveFPU
9225 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9226 SMLoc FPUNameLoc = getTok().getLoc();
9227 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9229 unsigned ID = ARMTargetParser::parseFPU(FPU);
9230 std::vector<const char *> Features;
9231 if (!ARMTargetParser::getFPUFeatures(ID, Features)) {
9232 Error(FPUNameLoc, "Unknown FPU name");
9236 for (auto Feature : Features)
9237 STI.ApplyFeatureFlag(Feature);
9238 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9240 getTargetStreamer().emitFPU(ID);
9244 /// parseDirectiveFnStart
9246 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9247 if (UC.hasFnStart()) {
9248 Error(L, ".fnstart starts before the end of previous one");
9249 UC.emitFnStartLocNotes();
9253 // Reset the unwind directives parser state
9256 getTargetStreamer().emitFnStart();
9258 UC.recordFnStart(L);
9262 /// parseDirectiveFnEnd
9264 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9265 // Check the ordering of unwind directives
9266 if (!UC.hasFnStart()) {
9267 Error(L, ".fnstart must precede .fnend directive");
9271 // Reset the unwind directives parser state
9272 getTargetStreamer().emitFnEnd();
9278 /// parseDirectiveCantUnwind
9280 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9281 UC.recordCantUnwind(L);
9283 // Check the ordering of unwind directives
9284 if (!UC.hasFnStart()) {
9285 Error(L, ".fnstart must precede .cantunwind directive");
9288 if (UC.hasHandlerData()) {
9289 Error(L, ".cantunwind can't be used with .handlerdata directive");
9290 UC.emitHandlerDataLocNotes();
9293 if (UC.hasPersonality()) {
9294 Error(L, ".cantunwind can't be used with .personality directive");
9295 UC.emitPersonalityLocNotes();
9299 getTargetStreamer().emitCantUnwind();
9303 /// parseDirectivePersonality
9304 /// ::= .personality name
9305 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9306 MCAsmParser &Parser = getParser();
9307 bool HasExistingPersonality = UC.hasPersonality();
9309 UC.recordPersonality(L);
9311 // Check the ordering of unwind directives
9312 if (!UC.hasFnStart()) {
9313 Error(L, ".fnstart must precede .personality directive");
9316 if (UC.cantUnwind()) {
9317 Error(L, ".personality can't be used with .cantunwind directive");
9318 UC.emitCantUnwindLocNotes();
9321 if (UC.hasHandlerData()) {
9322 Error(L, ".personality must precede .handlerdata directive");
9323 UC.emitHandlerDataLocNotes();
9326 if (HasExistingPersonality) {
9327 Parser.eatToEndOfStatement();
9328 Error(L, "multiple personality directives");
9329 UC.emitPersonalityLocNotes();
9333 // Parse the name of the personality routine
9334 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9335 Parser.eatToEndOfStatement();
9336 Error(L, "unexpected input in .personality directive.");
9339 StringRef Name(Parser.getTok().getIdentifier());
9342 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9343 getTargetStreamer().emitPersonality(PR);
9347 /// parseDirectiveHandlerData
9348 /// ::= .handlerdata
9349 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9350 UC.recordHandlerData(L);
9352 // Check the ordering of unwind directives
9353 if (!UC.hasFnStart()) {
9354 Error(L, ".fnstart must precede .personality directive");
9357 if (UC.cantUnwind()) {
9358 Error(L, ".handlerdata can't be used with .cantunwind directive");
9359 UC.emitCantUnwindLocNotes();
9363 getTargetStreamer().emitHandlerData();
9367 /// parseDirectiveSetFP
9368 /// ::= .setfp fpreg, spreg [, offset]
9369 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9370 MCAsmParser &Parser = getParser();
9371 // Check the ordering of unwind directives
9372 if (!UC.hasFnStart()) {
9373 Error(L, ".fnstart must precede .setfp directive");
9376 if (UC.hasHandlerData()) {
9377 Error(L, ".setfp must precede .handlerdata directive");
9382 SMLoc FPRegLoc = Parser.getTok().getLoc();
9383 int FPReg = tryParseRegister();
9385 Error(FPRegLoc, "frame pointer register expected");
9390 if (Parser.getTok().isNot(AsmToken::Comma)) {
9391 Error(Parser.getTok().getLoc(), "comma expected");
9394 Parser.Lex(); // skip comma
9397 SMLoc SPRegLoc = Parser.getTok().getLoc();
9398 int SPReg = tryParseRegister();
9400 Error(SPRegLoc, "stack pointer register expected");
9404 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9405 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9409 // Update the frame pointer register
9410 UC.saveFPReg(FPReg);
9414 if (Parser.getTok().is(AsmToken::Comma)) {
9415 Parser.Lex(); // skip comma
9417 if (Parser.getTok().isNot(AsmToken::Hash) &&
9418 Parser.getTok().isNot(AsmToken::Dollar)) {
9419 Error(Parser.getTok().getLoc(), "'#' expected");
9422 Parser.Lex(); // skip hash token.
9424 const MCExpr *OffsetExpr;
9425 SMLoc ExLoc = Parser.getTok().getLoc();
9427 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9428 Error(ExLoc, "malformed setfp offset");
9431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9433 Error(ExLoc, "setfp offset must be an immediate");
9437 Offset = CE->getValue();
9440 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9441 static_cast<unsigned>(SPReg), Offset);
9447 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9448 MCAsmParser &Parser = getParser();
9449 // Check the ordering of unwind directives
9450 if (!UC.hasFnStart()) {
9451 Error(L, ".fnstart must precede .pad directive");
9454 if (UC.hasHandlerData()) {
9455 Error(L, ".pad must precede .handlerdata directive");
9460 if (Parser.getTok().isNot(AsmToken::Hash) &&
9461 Parser.getTok().isNot(AsmToken::Dollar)) {
9462 Error(Parser.getTok().getLoc(), "'#' expected");
9465 Parser.Lex(); // skip hash token.
9467 const MCExpr *OffsetExpr;
9468 SMLoc ExLoc = Parser.getTok().getLoc();
9470 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9471 Error(ExLoc, "malformed pad offset");
9474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9476 Error(ExLoc, "pad offset must be an immediate");
9480 getTargetStreamer().emitPad(CE->getValue());
9484 /// parseDirectiveRegSave
9485 /// ::= .save { registers }
9486 /// ::= .vsave { registers }
9487 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9488 // Check the ordering of unwind directives
9489 if (!UC.hasFnStart()) {
9490 Error(L, ".fnstart must precede .save or .vsave directives");
9493 if (UC.hasHandlerData()) {
9494 Error(L, ".save or .vsave must precede .handlerdata directive");
9498 // RAII object to make sure parsed operands are deleted.
9499 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9501 // Parse the register list
9502 if (parseRegisterList(Operands))
9504 ARMOperand &Op = (ARMOperand &)*Operands[0];
9505 if (!IsVector && !Op.isRegList()) {
9506 Error(L, ".save expects GPR registers");
9509 if (IsVector && !Op.isDPRRegList()) {
9510 Error(L, ".vsave expects DPR registers");
9514 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9518 /// parseDirectiveInst
9519 /// ::= .inst opcode [, ...]
9520 /// ::= .inst.n opcode [, ...]
9521 /// ::= .inst.w opcode [, ...]
9522 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9523 MCAsmParser &Parser = getParser();
9535 Parser.eatToEndOfStatement();
9536 Error(Loc, "cannot determine Thumb instruction size, "
9537 "use inst.n/inst.w instead");
9542 Parser.eatToEndOfStatement();
9543 Error(Loc, "width suffixes are invalid in ARM mode");
9549 if (getLexer().is(AsmToken::EndOfStatement)) {
9550 Parser.eatToEndOfStatement();
9551 Error(Loc, "expected expression following directive");
9558 if (getParser().parseExpression(Expr)) {
9559 Error(Loc, "expected expression");
9563 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9565 Error(Loc, "expected constant expression");
9571 if (Value->getValue() > 0xffff) {
9572 Error(Loc, "inst.n operand is too big, use inst.w instead");
9577 if (Value->getValue() > 0xffffffff) {
9579 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9584 llvm_unreachable("only supported widths are 2 and 4");
9587 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9589 if (getLexer().is(AsmToken::EndOfStatement))
9592 if (getLexer().isNot(AsmToken::Comma)) {
9593 Error(Loc, "unexpected token in directive");
9604 /// parseDirectiveLtorg
9605 /// ::= .ltorg | .pool
9606 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9607 getTargetStreamer().emitCurrentConstantPool();
9611 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9612 const MCSection *Section = getStreamer().getCurrentSection().first;
9614 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9615 TokError("unexpected token in directive");
9620 getStreamer().InitSections(false);
9621 Section = getStreamer().getCurrentSection().first;
9624 assert(Section && "must have section to emit alignment");
9625 if (Section->UseCodeAlign())
9626 getStreamer().EmitCodeAlignment(2);
9628 getStreamer().EmitValueToAlignment(2);
9633 /// parseDirectivePersonalityIndex
9634 /// ::= .personalityindex index
9635 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9636 MCAsmParser &Parser = getParser();
9637 bool HasExistingPersonality = UC.hasPersonality();
9639 UC.recordPersonalityIndex(L);
9641 if (!UC.hasFnStart()) {
9642 Parser.eatToEndOfStatement();
9643 Error(L, ".fnstart must precede .personalityindex directive");
9646 if (UC.cantUnwind()) {
9647 Parser.eatToEndOfStatement();
9648 Error(L, ".personalityindex cannot be used with .cantunwind");
9649 UC.emitCantUnwindLocNotes();
9652 if (UC.hasHandlerData()) {
9653 Parser.eatToEndOfStatement();
9654 Error(L, ".personalityindex must precede .handlerdata directive");
9655 UC.emitHandlerDataLocNotes();
9658 if (HasExistingPersonality) {
9659 Parser.eatToEndOfStatement();
9660 Error(L, "multiple personality directives");
9661 UC.emitPersonalityLocNotes();
9665 const MCExpr *IndexExpression;
9666 SMLoc IndexLoc = Parser.getTok().getLoc();
9667 if (Parser.parseExpression(IndexExpression)) {
9668 Parser.eatToEndOfStatement();
9672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9674 Parser.eatToEndOfStatement();
9675 Error(IndexLoc, "index must be a constant number");
9678 if (CE->getValue() < 0 ||
9679 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9680 Parser.eatToEndOfStatement();
9681 Error(IndexLoc, "personality routine index should be in range [0-3]");
9685 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9689 /// parseDirectiveUnwindRaw
9690 /// ::= .unwind_raw offset, opcode [, opcode...]
9691 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9692 MCAsmParser &Parser = getParser();
9693 if (!UC.hasFnStart()) {
9694 Parser.eatToEndOfStatement();
9695 Error(L, ".fnstart must precede .unwind_raw directives");
9699 int64_t StackOffset;
9701 const MCExpr *OffsetExpr;
9702 SMLoc OffsetLoc = getLexer().getLoc();
9703 if (getLexer().is(AsmToken::EndOfStatement) ||
9704 getParser().parseExpression(OffsetExpr)) {
9705 Error(OffsetLoc, "expected expression");
9706 Parser.eatToEndOfStatement();
9710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9712 Error(OffsetLoc, "offset must be a constant");
9713 Parser.eatToEndOfStatement();
9717 StackOffset = CE->getValue();
9719 if (getLexer().isNot(AsmToken::Comma)) {
9720 Error(getLexer().getLoc(), "expected comma");
9721 Parser.eatToEndOfStatement();
9726 SmallVector<uint8_t, 16> Opcodes;
9730 SMLoc OpcodeLoc = getLexer().getLoc();
9731 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9732 Error(OpcodeLoc, "expected opcode expression");
9733 Parser.eatToEndOfStatement();
9737 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9739 Error(OpcodeLoc, "opcode value must be a constant");
9740 Parser.eatToEndOfStatement();
9744 const int64_t Opcode = OC->getValue();
9745 if (Opcode & ~0xff) {
9746 Error(OpcodeLoc, "invalid opcode");
9747 Parser.eatToEndOfStatement();
9751 Opcodes.push_back(uint8_t(Opcode));
9753 if (getLexer().is(AsmToken::EndOfStatement))
9756 if (getLexer().isNot(AsmToken::Comma)) {
9757 Error(getLexer().getLoc(), "unexpected token in directive");
9758 Parser.eatToEndOfStatement();
9765 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9771 /// parseDirectiveTLSDescSeq
9772 /// ::= .tlsdescseq tls-variable
9773 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9774 MCAsmParser &Parser = getParser();
9776 if (getLexer().isNot(AsmToken::Identifier)) {
9777 TokError("expected variable after '.tlsdescseq' directive");
9778 Parser.eatToEndOfStatement();
9782 const MCSymbolRefExpr *SRE =
9783 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
9784 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9787 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9788 Error(Parser.getTok().getLoc(), "unexpected token");
9789 Parser.eatToEndOfStatement();
9793 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9797 /// parseDirectiveMovSP
9798 /// ::= .movsp reg [, #offset]
9799 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9800 MCAsmParser &Parser = getParser();
9801 if (!UC.hasFnStart()) {
9802 Parser.eatToEndOfStatement();
9803 Error(L, ".fnstart must precede .movsp directives");
9806 if (UC.getFPReg() != ARM::SP) {
9807 Parser.eatToEndOfStatement();
9808 Error(L, "unexpected .movsp directive");
9812 SMLoc SPRegLoc = Parser.getTok().getLoc();
9813 int SPReg = tryParseRegister();
9815 Parser.eatToEndOfStatement();
9816 Error(SPRegLoc, "register expected");
9820 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9821 Parser.eatToEndOfStatement();
9822 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9827 if (Parser.getTok().is(AsmToken::Comma)) {
9830 if (Parser.getTok().isNot(AsmToken::Hash)) {
9831 Error(Parser.getTok().getLoc(), "expected #constant");
9832 Parser.eatToEndOfStatement();
9837 const MCExpr *OffsetExpr;
9838 SMLoc OffsetLoc = Parser.getTok().getLoc();
9839 if (Parser.parseExpression(OffsetExpr)) {
9840 Parser.eatToEndOfStatement();
9841 Error(OffsetLoc, "malformed offset expression");
9845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9847 Parser.eatToEndOfStatement();
9848 Error(OffsetLoc, "offset must be an immediate constant");
9852 Offset = CE->getValue();
9855 getTargetStreamer().emitMovSP(SPReg, Offset);
9856 UC.saveFPReg(SPReg);
9861 /// parseDirectiveObjectArch
9862 /// ::= .object_arch name
9863 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9864 MCAsmParser &Parser = getParser();
9865 if (getLexer().isNot(AsmToken::Identifier)) {
9866 Error(getLexer().getLoc(), "unexpected token");
9867 Parser.eatToEndOfStatement();
9871 StringRef Arch = Parser.getTok().getString();
9872 SMLoc ArchLoc = Parser.getTok().getLoc();
9875 unsigned ID = ARMTargetParser::parseArch(Arch);
9877 if (ID == ARM::AK_INVALID) {
9878 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9879 Parser.eatToEndOfStatement();
9883 getTargetStreamer().emitObjectArch(ID);
9885 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9886 Error(getLexer().getLoc(), "unexpected token");
9887 Parser.eatToEndOfStatement();
9893 /// parseDirectiveAlign
9895 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9896 // NOTE: if this is not the end of the statement, fall back to the target
9897 // agnostic handling for this directive which will correctly handle this.
9898 if (getLexer().isNot(AsmToken::EndOfStatement))
9901 // '.align' is target specifically handled to mean 2**2 byte alignment.
9902 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9903 getStreamer().EmitCodeAlignment(4, 0);
9905 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9910 /// parseDirectiveThumbSet
9911 /// ::= .thumb_set name, value
9912 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9913 MCAsmParser &Parser = getParser();
9916 if (Parser.parseIdentifier(Name)) {
9917 TokError("expected identifier after '.thumb_set'");
9918 Parser.eatToEndOfStatement();
9922 if (getLexer().isNot(AsmToken::Comma)) {
9923 TokError("expected comma after name '" + Name + "'");
9924 Parser.eatToEndOfStatement();
9930 const MCExpr *Value;
9931 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
9932 Parser, Sym, Value))
9935 getTargetStreamer().emitThumbSet(Sym, Value);
9939 /// Force static initialization.
9940 extern "C" void LLVMInitializeARMAsmParser() {
9941 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9942 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9943 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9944 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9947 #define GET_REGISTER_MATCHER
9948 #define GET_SUBTARGET_FEATURE_NAME
9949 #define GET_MATCHER_IMPLEMENTATION
9950 #include "ARMGenAsmMatcher.inc"
9952 // FIXME: This structure should be moved inside ARMTargetParser
9953 // when we start to table-generate them, and we can use the ARM
9954 // flags below, that were generated by table-gen.
9955 static const struct {
9956 const ARM::ArchExtKind Kind;
9957 const unsigned ArchCheck;
9958 const FeatureBitset Features;
9960 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
9961 { ARM::AEK_CRYPTO, Feature_HasV8,
9962 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9963 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
9964 { ARM::AEK_HWDIV, Feature_HasV7 | Feature_IsNotMClass,
9965 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
9966 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
9967 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9968 // FIXME: Also available in ARMv6-K
9969 { ARM::AEK_SEC, Feature_HasV7, {ARM::FeatureTrustZone} },
9970 // FIXME: Only available in A-class, isel not predicated
9971 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
9972 // FIXME: Unsupported extensions.
9973 { ARM::AEK_OS, Feature_None, {} },
9974 { ARM::AEK_IWMMXT, Feature_None, {} },
9975 { ARM::AEK_IWMMXT2, Feature_None, {} },
9976 { ARM::AEK_MAVERICK, Feature_None, {} },
9977 { ARM::AEK_XSCALE, Feature_None, {} },
9980 /// parseDirectiveArchExtension
9981 /// ::= .arch_extension [no]feature
9982 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9983 MCAsmParser &Parser = getParser();
9985 if (getLexer().isNot(AsmToken::Identifier)) {
9986 Error(getLexer().getLoc(), "unexpected token");
9987 Parser.eatToEndOfStatement();
9991 StringRef Name = Parser.getTok().getString();
9992 SMLoc ExtLoc = Parser.getTok().getLoc();
9995 bool EnableFeature = true;
9996 if (Name.startswith_lower("no")) {
9997 EnableFeature = false;
9998 Name = Name.substr(2);
10000 unsigned FeatureKind = ARMTargetParser::parseArchExt(Name);
10001 if (FeatureKind == ARM::AEK_INVALID)
10002 Error(ExtLoc, "unknown architectural extension: " + Name);
10004 for (const auto &Extension : Extensions) {
10005 if (Extension.Kind != FeatureKind)
10008 if (Extension.Features.none())
10009 report_fatal_error("unsupported architectural extension: " + Name);
10011 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
10012 Error(ExtLoc, "architectural extension '" + Name + "' is not "
10013 "allowed for the current base architecture");
10017 FeatureBitset ToggleFeatures = EnableFeature
10018 ? (~STI.getFeatureBits() & Extension.Features)
10019 : ( STI.getFeatureBits() & Extension.Features);
10021 uint64_t Features =
10022 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10023 setAvailableFeatures(Features);
10027 Error(ExtLoc, "unknown architectural extension: " + Name);
10028 Parser.eatToEndOfStatement();
10032 // Define this matcher function after the auto-generated include so we
10033 // have the match class enum definitions.
10034 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10036 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10037 // If the kind is a token for a literal immediate, check if our asm
10038 // operand matches. This is for InstAliases which have a fixed-value
10039 // immediate in the syntax.
10044 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10045 if (CE->getValue() == 0)
10046 return Match_Success;
10050 const MCExpr *SOExpr = Op.getImm();
10052 if (!SOExpr->evaluateAsAbsolute(Value))
10053 return Match_Success;
10054 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10055 "expression value must be representable in 32 bits");
10060 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10061 return Match_Success;
10064 return Match_InvalidOperand;