1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Target/TargetMachine.h"
32 class ARMBaseTargetMachine : public LLVMTargetMachine {
34 ARMSubtarget Subtarget;
36 InstrItineraryData InstrItins;
39 ARMBaseTargetMachine(const Target &T, StringRef TT,
40 StringRef CPU, StringRef FS,
41 const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
46 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
47 const ARMTargetLowering *getTargetLowering() const override {
48 // Implemented by derived classes
49 llvm_unreachable("getTargetLowering not implemented");
51 const InstrItineraryData *getInstrItineraryData() const override {
55 /// \brief Register ARM analysis passes with a pass manager.
56 void addAnalysisPasses(PassManagerBase &PM) override;
58 // Pass Pipeline Configuration
59 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
61 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
64 /// ARMTargetMachine - ARM target machine.
66 class ARMTargetMachine : public ARMBaseTargetMachine {
67 virtual void anchor();
68 ARMInstrInfo InstrInfo;
69 ARMTargetLowering TLInfo;
70 ARMFrameLowering FrameLowering;
72 ARMTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
79 const ARMRegisterInfo *getRegisterInfo() const override {
80 return &InstrInfo.getRegisterInfo();
83 const ARMTargetLowering *getTargetLowering() const override {
87 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
88 return getSubtargetImpl()->getSelectionDAGInfo();
90 const ARMFrameLowering *getFrameLowering() const override {
91 return &FrameLowering;
93 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
94 const DataLayout *getDataLayout() const override {
95 return getSubtargetImpl()->getDataLayout();
99 /// ARMLETargetMachine - ARM little endian target machine.
101 class ARMLETargetMachine : public ARMTargetMachine {
102 void anchor() override;
104 ARMLETargetMachine(const Target &T, StringRef TT,
105 StringRef CPU, StringRef FS, const TargetOptions &Options,
106 Reloc::Model RM, CodeModel::Model CM,
107 CodeGenOpt::Level OL);
110 /// ARMBETargetMachine - ARM big endian target machine.
112 class ARMBETargetMachine : public ARMTargetMachine {
113 void anchor() override;
115 ARMBETargetMachine(const Target &T, StringRef TT,
116 StringRef CPU, StringRef FS, const TargetOptions &Options,
117 Reloc::Model RM, CodeModel::Model CM,
118 CodeGenOpt::Level OL);
121 /// ThumbTargetMachine - Thumb target machine.
122 /// Due to the way architectures are handled, this represents both
123 /// Thumb-1 and Thumb-2.
125 class ThumbTargetMachine : public ARMBaseTargetMachine {
126 virtual void anchor();
127 // Either Thumb1InstrInfo or Thumb2InstrInfo.
128 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
129 ARMTargetLowering TLInfo;
130 // Either Thumb1FrameLowering or ARMFrameLowering.
131 std::unique_ptr<ARMFrameLowering> FrameLowering;
133 ThumbTargetMachine(const Target &T, StringRef TT,
134 StringRef CPU, StringRef FS,
135 const TargetOptions &Options,
136 Reloc::Model RM, CodeModel::Model CM,
137 CodeGenOpt::Level OL,
140 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
141 const ARMBaseRegisterInfo *getRegisterInfo() const override {
142 return &InstrInfo->getRegisterInfo();
145 const ARMTargetLowering *getTargetLowering() const override {
149 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
150 return getSubtargetImpl()->getSelectionDAGInfo();
153 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
154 const ARMBaseInstrInfo *getInstrInfo() const override {
155 return InstrInfo.get();
157 /// returns either Thumb1FrameLowering or ARMFrameLowering
158 const ARMFrameLowering *getFrameLowering() const override {
159 return FrameLowering.get();
161 const DataLayout *getDataLayout() const override {
162 return getSubtargetImpl()->getDataLayout();
166 /// ThumbLETargetMachine - Thumb little endian target machine.
168 class ThumbLETargetMachine : public ThumbTargetMachine {
169 void anchor() override;
171 ThumbLETargetMachine(const Target &T, StringRef TT,
172 StringRef CPU, StringRef FS, const TargetOptions &Options,
173 Reloc::Model RM, CodeModel::Model CM,
174 CodeGenOpt::Level OL);
177 /// ThumbBETargetMachine - Thumb big endian target machine.
179 class ThumbBETargetMachine : public ThumbTargetMachine {
180 void anchor() override;
182 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
183 StringRef FS, const TargetOptions &Options,
184 Reloc::Model RM, CodeModel::Model CM,
185 CodeGenOpt::Level OL);
188 } // end namespace llvm