1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS // ARM EABI
34 std::unique_ptr<TargetLoweringObjectFile> TLOF;
35 ARMSubtarget Subtarget;
37 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
40 ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
46 ~ARMBaseTargetMachine() override;
48 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
50 const DataLayout *getDataLayout() const override { return &DL; }
52 /// \brief Register ARM analysis passes with a pass manager.
53 void addAnalysisPasses(PassManagerBase &PM) override;
55 // Pass Pipeline Configuration
56 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
58 TargetLoweringObjectFile *getObjFileLowering() const override {
63 /// ARMTargetMachine - ARM target machine.
65 class ARMTargetMachine : public ARMBaseTargetMachine {
66 virtual void anchor();
68 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
69 const TargetOptions &Options, Reloc::Model RM,
70 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
73 /// ARMLETargetMachine - ARM little endian target machine.
75 class ARMLETargetMachine : public ARMTargetMachine {
76 void anchor() override;
78 ARMLETargetMachine(const Target &T, StringRef TT,
79 StringRef CPU, StringRef FS, const TargetOptions &Options,
80 Reloc::Model RM, CodeModel::Model CM,
81 CodeGenOpt::Level OL);
84 /// ARMBETargetMachine - ARM big endian target machine.
86 class ARMBETargetMachine : public ARMTargetMachine {
87 void anchor() override;
89 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
90 const TargetOptions &Options, Reloc::Model RM,
91 CodeModel::Model CM, CodeGenOpt::Level OL);
94 /// ThumbTargetMachine - Thumb target machine.
95 /// Due to the way architectures are handled, this represents both
96 /// Thumb-1 and Thumb-2.
98 class ThumbTargetMachine : public ARMBaseTargetMachine {
99 virtual void anchor();
101 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
102 const TargetOptions &Options, Reloc::Model RM,
103 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
106 /// ThumbLETargetMachine - Thumb little endian target machine.
108 class ThumbLETargetMachine : public ThumbTargetMachine {
109 void anchor() override;
111 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
112 StringRef FS, const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL);
117 /// ThumbBETargetMachine - Thumb big endian target machine.
119 class ThumbBETargetMachine : public ThumbTargetMachine {
120 void anchor() override;
122 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
123 StringRef FS, const TargetOptions &Options,
124 Reloc::Model RM, CodeModel::Model CM,
125 CodeGenOpt::Level OL);
128 } // end namespace llvm