1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Target/TargetMachine.h"
32 class ARMBaseTargetMachine : public LLVMTargetMachine {
34 ARMSubtarget Subtarget;
37 InstrItineraryData InstrItins;
40 ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
47 ARMJITInfo *getJITInfo() override { return &JITInfo; }
48 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
49 const ARMTargetLowering *getTargetLowering() const override {
50 // Implemented by derived classes
51 llvm_unreachable("getTargetLowering not implemented");
53 const InstrItineraryData *getInstrItineraryData() const override {
57 /// \brief Register ARM analysis passes with a pass manager.
58 void addAnalysisPasses(PassManagerBase &PM) override;
60 // Pass Pipeline Configuration
61 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
63 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
66 /// ARMTargetMachine - ARM target machine.
68 class ARMTargetMachine : public ARMBaseTargetMachine {
69 virtual void anchor();
70 ARMInstrInfo InstrInfo;
71 ARMTargetLowering TLInfo;
72 ARMSelectionDAGInfo TSInfo;
73 ARMFrameLowering FrameLowering;
75 ARMTargetMachine(const Target &T, StringRef TT,
76 StringRef CPU, StringRef FS,
77 const TargetOptions &Options,
78 Reloc::Model RM, CodeModel::Model CM,
82 const ARMRegisterInfo *getRegisterInfo() const override {
83 return &InstrInfo.getRegisterInfo();
86 const ARMTargetLowering *getTargetLowering() const override {
90 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
93 const ARMFrameLowering *getFrameLowering() const override {
94 return &FrameLowering;
96 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
97 const DataLayout *getDataLayout() const override {
98 return getSubtargetImpl()->getDataLayout();
102 /// ARMLETargetMachine - ARM little endian target machine.
104 class ARMLETargetMachine : public ARMTargetMachine {
105 void anchor() override;
107 ARMLETargetMachine(const Target &T, StringRef TT,
108 StringRef CPU, StringRef FS, const TargetOptions &Options,
109 Reloc::Model RM, CodeModel::Model CM,
110 CodeGenOpt::Level OL);
113 /// ARMBETargetMachine - ARM big endian target machine.
115 class ARMBETargetMachine : public ARMTargetMachine {
116 void anchor() override;
118 ARMBETargetMachine(const Target &T, StringRef TT,
119 StringRef CPU, StringRef FS, const TargetOptions &Options,
120 Reloc::Model RM, CodeModel::Model CM,
121 CodeGenOpt::Level OL);
124 /// ThumbTargetMachine - Thumb target machine.
125 /// Due to the way architectures are handled, this represents both
126 /// Thumb-1 and Thumb-2.
128 class ThumbTargetMachine : public ARMBaseTargetMachine {
129 virtual void anchor();
130 // Either Thumb1InstrInfo or Thumb2InstrInfo.
131 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
132 ARMTargetLowering TLInfo;
133 ARMSelectionDAGInfo TSInfo;
134 // Either Thumb1FrameLowering or ARMFrameLowering.
135 std::unique_ptr<ARMFrameLowering> FrameLowering;
137 ThumbTargetMachine(const Target &T, StringRef TT,
138 StringRef CPU, StringRef FS,
139 const TargetOptions &Options,
140 Reloc::Model RM, CodeModel::Model CM,
141 CodeGenOpt::Level OL,
144 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
145 const ARMBaseRegisterInfo *getRegisterInfo() const override {
146 return &InstrInfo->getRegisterInfo();
149 const ARMTargetLowering *getTargetLowering() const override {
153 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
157 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
158 const ARMBaseInstrInfo *getInstrInfo() const override {
159 return InstrInfo.get();
161 /// returns either Thumb1FrameLowering or ARMFrameLowering
162 const ARMFrameLowering *getFrameLowering() const override {
163 return FrameLowering.get();
165 const DataLayout *getDataLayout() const override {
166 return getSubtargetImpl()->getDataLayout();
170 /// ThumbLETargetMachine - Thumb little endian target machine.
172 class ThumbLETargetMachine : public ThumbTargetMachine {
173 void anchor() override;
175 ThumbLETargetMachine(const Target &T, StringRef TT,
176 StringRef CPU, StringRef FS, const TargetOptions &Options,
177 Reloc::Model RM, CodeModel::Model CM,
178 CodeGenOpt::Level OL);
181 /// ThumbBETargetMachine - Thumb big endian target machine.
183 class ThumbBETargetMachine : public ThumbTargetMachine {
184 void anchor() override;
186 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
187 StringRef FS, const TargetOptions &Options,
188 Reloc::Model RM, CodeModel::Model CM,
189 CodeGenOpt::Level OL);
192 } // end namespace llvm