1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS // ARM EABI
33 std::unique_ptr<TargetLoweringObjectFile> TLOF;
34 ARMSubtarget Subtarget;
36 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
39 ARMBaseTargetMachine(const Target &T, StringRef TT,
40 StringRef CPU, StringRef FS,
41 const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
45 ~ARMBaseTargetMachine() override;
47 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
48 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
50 /// \brief Register ARM analysis passes with a pass manager.
51 void addAnalysisPasses(PassManagerBase &PM) override;
53 // Pass Pipeline Configuration
54 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
56 TargetLoweringObjectFile *getObjFileLowering() const override {
61 /// ARMTargetMachine - ARM target machine.
63 class ARMTargetMachine : public ARMBaseTargetMachine {
64 virtual void anchor();
66 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
67 const TargetOptions &Options, Reloc::Model RM,
68 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
71 /// ARMLETargetMachine - ARM little endian target machine.
73 class ARMLETargetMachine : public ARMTargetMachine {
74 void anchor() override;
76 ARMLETargetMachine(const Target &T, StringRef TT,
77 StringRef CPU, StringRef FS, const TargetOptions &Options,
78 Reloc::Model RM, CodeModel::Model CM,
79 CodeGenOpt::Level OL);
82 /// ARMBETargetMachine - ARM big endian target machine.
84 class ARMBETargetMachine : public ARMTargetMachine {
85 void anchor() override;
87 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
88 const TargetOptions &Options, Reloc::Model RM,
89 CodeModel::Model CM, CodeGenOpt::Level OL);
92 /// ThumbTargetMachine - Thumb target machine.
93 /// Due to the way architectures are handled, this represents both
94 /// Thumb-1 and Thumb-2.
96 class ThumbTargetMachine : public ARMBaseTargetMachine {
97 virtual void anchor();
99 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
100 const TargetOptions &Options, Reloc::Model RM,
101 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
104 /// ThumbLETargetMachine - Thumb little endian target machine.
106 class ThumbLETargetMachine : public ThumbTargetMachine {
107 void anchor() override;
109 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
110 StringRef FS, const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL);
115 /// ThumbBETargetMachine - Thumb big endian target machine.
117 class ThumbBETargetMachine : public ThumbTargetMachine {
118 void anchor() override;
120 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
121 StringRef FS, const TargetOptions &Options,
122 Reloc::Model RM, CodeModel::Model CM,
123 CodeGenOpt::Level OL);
126 } // end namespace llvm