1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
35 CortexR5, Swift, CortexA53, CortexA57
37 enum ARMProcClassEnum {
38 None, AClass, RClass, MClass
41 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
42 ARMProcFamilyEnum ARMProcFamily;
44 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
45 ARMProcClassEnum ARMProcClass;
47 /// HasV4TOps, HasV5TOps, HasV5TEOps,
48 /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
49 /// Specify whether target support specific ARM ISA variants.
59 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
60 /// floating point ISAs are supported.
67 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
68 /// specified. Use the method useNEONForSinglePrecisionFP() to
69 /// determine if NEON should actually be used.
70 bool UseNEONForSinglePrecisionFP;
72 /// UseMulOps - True if non-microcoded fused integer multiply-add and
73 /// multiply-subtract instructions should be used.
76 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
77 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
80 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
81 /// forwarding to allow mul + mla being issued back to back.
82 bool HasVMLxForwarding;
84 /// SlowFPBrcc - True if floating point compare + branch is slow.
87 /// InThumbMode - True if compiling for Thumb, false for ARM.
90 /// HasThumb2 - True if Thumb2 instructions are supported.
93 /// NoARM - True if subtarget does not support ARM mode execution.
96 /// PostRAScheduler - True if using post-register-allocation scheduler.
99 /// IsR9Reserved - True if R9 is a not available as general purpose register.
102 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
103 /// imms (including global addresses).
106 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
107 /// must be able to synthesize call stubs for interworking between ARM and
109 bool SupportsTailCall;
111 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
115 /// HasD16 - True if subtarget is limited to 16 double precision
116 /// FP registers for VFPv3.
119 /// HasHardwareDivide - True if subtarget supports [su]div
120 bool HasHardwareDivide;
122 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
123 bool HasHardwareDivideInARM;
125 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
127 bool HasT2ExtractPack;
129 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
133 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
134 /// over 16-bit ones.
137 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
138 /// that partially update CPSR and add false dependency on the previous
139 /// CPSR setting instruction.
140 bool AvoidCPSRPartialUpdate;
142 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
143 /// movs with shifter operand (i.e. asr, lsl, lsr).
144 bool AvoidMOVsShifterOperand;
146 /// HasRAS - Some processors perform return stack prediction. CodeGen should
147 /// avoid issue "normal" call instructions to callees which do not return.
150 /// HasMPExtension - True if the subtarget supports Multiprocessing
151 /// extension (ARMv7 only).
154 /// HasVirtualization - True if the subtarget supports the Virtualization
156 bool HasVirtualization;
158 /// FPOnlySP - If true, the floating point unit only supports single
162 /// If true, the processor supports the Performance Monitor Extensions. These
163 /// include a generic cycle-counter as well as more fine-grained (often
164 /// implementation-specific) events.
167 /// HasTrustZone - if true, processor supports TrustZone security extensions
170 /// HasCrypto - if true, processor supports Cryptography extensions
173 /// HasCRC - if true, processor supports CRC instructions
176 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
177 /// accesses for some types. For details, see
178 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
179 bool AllowsUnalignedMem;
181 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
182 /// blocks to conform to ARMv8 rule.
185 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
186 /// and such) instructions in Thumb2 code.
189 /// NaCl TRAP instruction is generated instead of the regular TRAP.
192 /// Target machine allowed unsafe FP math (such as use of NEON fp)
195 /// stackAlignment - The minimum alignment known to hold of the stack frame on
196 /// entry to the function and which must be maintained by every function.
197 unsigned stackAlignment;
199 /// CPUString - String name of used CPU.
200 std::string CPUString;
202 /// TargetTriple - What processor and OS we're targeting.
205 /// SchedModel - Processor specific instruction costs.
206 const MCSchedModel *SchedModel;
208 /// Selected instruction itineraries (one entry per itinerary class.)
209 InstrItineraryData InstrItins;
211 /// Options passed via command line that could influence the target
212 const TargetOptions &Options;
217 ARM_ABI_AAPCS // ARM EABI
220 /// This constructor initializes the data members to match that
221 /// of the specified triple.
223 ARMSubtarget(const std::string &TT, const std::string &CPU,
224 const std::string &FS, const TargetOptions &Options);
226 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
227 /// that still makes it profitable to inline the call.
228 unsigned getMaxInlineSizeThreshold() const {
229 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
230 // Change this once Thumb1 ldmia / stmia support is added.
231 return isThumb1Only() ? 0 : 64;
233 /// ParseSubtargetFeatures - Parses features string setting specified
234 /// subtarget options. Definition of function is auto generated by tblgen.
235 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
237 /// \brief Reset the features for the ARM target.
238 virtual void resetSubtargetFeatures(const MachineFunction *MF);
240 void initializeEnvironment();
241 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
243 void computeIssueWidth();
245 bool hasV4TOps() const { return HasV4TOps; }
246 bool hasV5TOps() const { return HasV5TOps; }
247 bool hasV5TEOps() const { return HasV5TEOps; }
248 bool hasV6Ops() const { return HasV6Ops; }
249 bool hasV6MOps() const { return HasV6MOps; }
250 bool hasV6T2Ops() const { return HasV6T2Ops; }
251 bool hasV7Ops() const { return HasV7Ops; }
252 bool hasV8Ops() const { return HasV8Ops; }
254 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
255 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
256 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
257 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
258 bool isSwift() const { return ARMProcFamily == Swift; }
259 bool isCortexM3() const { return CPUString == "cortex-m3"; }
260 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
261 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
263 bool hasARMOps() const { return !NoARM; }
265 bool hasVFP2() const { return HasVFPv2; }
266 bool hasVFP3() const { return HasVFPv3; }
267 bool hasVFP4() const { return HasVFPv4; }
268 bool hasFPARMv8() const { return HasFPARMv8; }
269 bool hasNEON() const { return HasNEON; }
270 bool hasCrypto() const { return HasCrypto; }
271 bool hasCRC() const { return HasCRC; }
272 bool hasVirtualization() const { return HasVirtualization; }
273 bool useNEONForSinglePrecisionFP() const {
274 return hasNEON() && UseNEONForSinglePrecisionFP; }
276 bool hasDivide() const { return HasHardwareDivide; }
277 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
278 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
279 bool hasDataBarrier() const { return HasDataBarrier; }
280 bool hasAnyDataBarrier() const {
281 return HasDataBarrier || (hasV6Ops() && !isThumb());
283 bool useMulOps() const { return UseMulOps; }
284 bool useFPVMLx() const { return !SlowFPVMLx; }
285 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
286 bool isFPBrccSlow() const { return SlowFPBrcc; }
287 bool isFPOnlySP() const { return FPOnlySP; }
288 bool hasPerfMon() const { return HasPerfMon; }
289 bool hasTrustZone() const { return HasTrustZone; }
290 bool prefers32BitThumb() const { return Pref32BitThumb; }
291 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
292 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
293 bool hasRAS() const { return HasRAS; }
294 bool hasMPExtension() const { return HasMPExtension; }
295 bool hasThumb2DSP() const { return Thumb2DSP; }
296 bool useNaClTrap() const { return UseNaClTrap; }
298 bool hasFP16() const { return HasFP16; }
299 bool hasD16() const { return HasD16; }
301 const Triple &getTargetTriple() const { return TargetTriple; }
303 bool isTargetIOS() const { return TargetTriple.isiOS(); }
304 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
305 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
306 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
307 bool isTargetELF() const { return !isTargetDarwin(); }
308 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
309 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
310 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
311 // even for GNUEABI, so we can make a distinction here and still conform to
312 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
313 bool isTargetAEABI() const {
314 return TargetTriple.getEnvironment() == Triple::EABI;
317 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
318 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
320 bool isThumb() const { return InThumbMode; }
321 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
322 bool isThumb2() const { return InThumbMode && HasThumb2; }
323 bool hasThumb2() const { return HasThumb2; }
324 bool isMClass() const { return ARMProcClass == MClass; }
325 bool isRClass() const { return ARMProcClass == RClass; }
326 bool isAClass() const { return ARMProcClass == AClass; }
328 bool isR9Reserved() const { return IsR9Reserved; }
330 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
331 bool supportsTailCall() const { return SupportsTailCall; }
333 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
335 bool restrictIT() const { return RestrictIT; }
337 const std::string & getCPUString() const { return CPUString; }
339 unsigned getMispredictionPenalty() const;
341 /// This function returns true if the target has sincos() routine in its
342 /// compiler runtime or math libraries.
343 bool hasSinCos() const;
345 /// enablePostRAScheduler - True at 'More' optimization.
346 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
347 TargetSubtargetInfo::AntiDepBreakMode& Mode,
348 RegClassVector& CriticalPathRCs) const;
350 /// getInstrItins - Return the instruction itineraies based on subtarget
352 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
354 /// getStackAlignment - Returns the minimum alignment known to hold of the
355 /// stack frame on entry to the function and which must be maintained by every
356 /// function for this subtarget.
357 unsigned getStackAlignment() const { return stackAlignment; }
359 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
361 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
363 } // End llvm namespace
365 #endif // ARMSUBTARGET_H