1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
36 enum ARMProcClassEnum {
37 None, AClass, RClass, MClass
40 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
41 ARMProcFamilyEnum ARMProcFamily;
43 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
44 ARMProcClassEnum ARMProcClass;
46 /// HasV4TOps, HasV5TOps, HasV5TEOps,
47 /// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
48 /// Specify whether target support specific ARM ISA variants.
57 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
58 /// floating point ISAs are supported.
65 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
66 /// specified. Use the method useNEONForSinglePrecisionFP() to
67 /// determine if NEON should actually be used.
68 bool UseNEONForSinglePrecisionFP;
70 /// UseMulOps - True if non-microcoded fused integer multiply-add and
71 /// multiply-subtract instructions should be used.
74 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
75 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
78 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
79 /// forwarding to allow mul + mla being issued back to back.
80 bool HasVMLxForwarding;
82 /// SlowFPBrcc - True if floating point compare + branch is slow.
85 /// InThumbMode - True if compiling for Thumb, false for ARM.
88 /// HasThumb2 - True if Thumb2 instructions are supported.
91 /// NoARM - True if subtarget does not support ARM mode execution.
94 /// PostRAScheduler - True if using post-register-allocation scheduler.
97 /// IsR9Reserved - True if R9 is a not available as general purpose register.
100 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
101 /// imms (including global addresses).
104 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
105 /// must be able to synthesize call stubs for interworking between ARM and
107 bool SupportsTailCall;
109 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
113 /// HasD16 - True if subtarget is limited to 16 double precision
114 /// FP registers for VFPv3.
117 /// HasHardwareDivide - True if subtarget supports [su]div
118 bool HasHardwareDivide;
120 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
121 bool HasHardwareDivideInARM;
123 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
125 bool HasT2ExtractPack;
127 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
131 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
132 /// over 16-bit ones.
135 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
136 /// that partially update CPSR and add false dependency on the previous
137 /// CPSR setting instruction.
138 bool AvoidCPSRPartialUpdate;
140 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
141 /// movs with shifter operand (i.e. asr, lsl, lsr).
142 bool AvoidMOVsShifterOperand;
144 /// HasRAS - Some processors perform return stack prediction. CodeGen should
145 /// avoid issue "normal" call instructions to callees which do not return.
148 /// HasMPExtension - True if the subtarget supports Multiprocessing
149 /// extension (ARMv7 only).
152 /// FPOnlySP - If true, the floating point unit only supports single
156 /// If true, the processor supports the Performance Monitor Extensions. These
157 /// include a generic cycle-counter as well as more fine-grained (often
158 /// implementation-specific) events.
161 /// HasTrustZone - if true, processor supports TrustZone security extensions
164 /// HasCrypto - if true, processor supports Cryptography extensions
167 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
168 /// accesses for some types. For details, see
169 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
170 bool AllowsUnalignedMem;
172 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
173 /// and such) instructions in Thumb2 code.
176 /// NaCl TRAP instruction is generated instead of the regular TRAP.
179 /// Target machine allowed unsafe FP math (such as use of NEON fp)
182 /// stackAlignment - The minimum alignment known to hold of the stack frame on
183 /// entry to the function and which must be maintained by every function.
184 unsigned stackAlignment;
186 /// CPUString - String name of used CPU.
187 std::string CPUString;
189 /// TargetTriple - What processor and OS we're targeting.
192 /// SchedModel - Processor specific instruction costs.
193 const MCSchedModel *SchedModel;
195 /// Selected instruction itineraries (one entry per itinerary class.)
196 InstrItineraryData InstrItins;
198 /// Options passed via command line that could influence the target
199 const TargetOptions &Options;
204 ARM_ABI_AAPCS // ARM EABI
207 /// This constructor initializes the data members to match that
208 /// of the specified triple.
210 ARMSubtarget(const std::string &TT, const std::string &CPU,
211 const std::string &FS, const TargetOptions &Options);
213 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
214 /// that still makes it profitable to inline the call.
215 unsigned getMaxInlineSizeThreshold() const {
216 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
217 // Change this once Thumb1 ldmia / stmia support is added.
218 return isThumb1Only() ? 0 : 64;
220 /// ParseSubtargetFeatures - Parses features string setting specified
221 /// subtarget options. Definition of function is auto generated by tblgen.
222 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
224 /// \brief Reset the features for the ARM target.
225 virtual void resetSubtargetFeatures(const MachineFunction *MF);
227 void initializeEnvironment();
228 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
230 void computeIssueWidth();
232 bool hasV4TOps() const { return HasV4TOps; }
233 bool hasV5TOps() const { return HasV5TOps; }
234 bool hasV5TEOps() const { return HasV5TEOps; }
235 bool hasV6Ops() const { return HasV6Ops; }
236 bool hasV6T2Ops() const { return HasV6T2Ops; }
237 bool hasV7Ops() const { return HasV7Ops; }
238 bool hasV8Ops() const { return HasV8Ops; }
240 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
241 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
242 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
243 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
244 bool isSwift() const { return ARMProcFamily == Swift; }
245 bool isCortexM3() const { return CPUString == "cortex-m3"; }
246 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
247 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
249 bool hasARMOps() const { return !NoARM; }
251 bool hasVFP2() const { return HasVFPv2; }
252 bool hasVFP3() const { return HasVFPv3; }
253 bool hasVFP4() const { return HasVFPv4; }
254 bool hasFPARMv8() const { return HasFPARMv8; }
255 bool hasNEON() const { return HasNEON; }
256 bool hasCrypto() const { return HasCrypto; }
257 bool useNEONForSinglePrecisionFP() const {
258 return hasNEON() && UseNEONForSinglePrecisionFP; }
260 bool hasDivide() const { return HasHardwareDivide; }
261 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
262 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
263 bool hasDataBarrier() const { return HasDataBarrier; }
264 bool useMulOps() const { return UseMulOps; }
265 bool useFPVMLx() const { return !SlowFPVMLx; }
266 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
267 bool isFPBrccSlow() const { return SlowFPBrcc; }
268 bool isFPOnlySP() const { return FPOnlySP; }
269 bool hasPerfMon() const { return HasPerfMon; }
270 bool hasTrustZone() const { return HasTrustZone; }
271 bool prefers32BitThumb() const { return Pref32BitThumb; }
272 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
273 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
274 bool hasRAS() const { return HasRAS; }
275 bool hasMPExtension() const { return HasMPExtension; }
276 bool hasThumb2DSP() const { return Thumb2DSP; }
277 bool useNaClTrap() const { return UseNaClTrap; }
279 bool hasFP16() const { return HasFP16; }
280 bool hasD16() const { return HasD16; }
282 const Triple &getTargetTriple() const { return TargetTriple; }
284 bool isTargetIOS() const { return TargetTriple.isiOS(); }
285 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
286 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
287 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
288 bool isTargetELF() const { return !isTargetDarwin(); }
289 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
290 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
291 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
292 // even for GNUEABI, so we can make a distinction here and still conform to
293 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
294 bool isTargetAEABI() const {
295 return TargetTriple.getEnvironment() == Triple::EABI;
298 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
299 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
301 bool isThumb() const { return InThumbMode; }
302 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
303 bool isThumb2() const { return InThumbMode && HasThumb2; }
304 bool hasThumb2() const { return HasThumb2; }
305 bool isMClass() const { return ARMProcClass == MClass; }
306 bool isRClass() const { return ARMProcClass == RClass; }
307 bool isAClass() const { return ARMProcClass == AClass; }
309 bool isR9Reserved() const { return IsR9Reserved; }
311 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
312 bool supportsTailCall() const { return SupportsTailCall; }
314 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
316 const std::string & getCPUString() const { return CPUString; }
318 unsigned getMispredictionPenalty() const;
320 /// enablePostRAScheduler - True at 'More' optimization.
321 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
322 TargetSubtargetInfo::AntiDepBreakMode& Mode,
323 RegClassVector& CriticalPathRCs) const;
325 /// getInstrItins - Return the instruction itineraies based on subtarget
327 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
329 /// getStackAlignment - Returns the minimum alignment known to hold of the
330 /// stack frame on entry to the function and which must be maintained by every
331 /// function for this subtarget.
332 unsigned getStackAlignment() const { return stackAlignment; }
334 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
336 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
338 } // End llvm namespace
340 #endif // ARMSUBTARGET_H