1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMJITInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #define DEBUG_TYPE "arm-subtarget"
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #define GET_SUBTARGETINFO_CTOR
40 #include "ARMGenSubtargetInfo.inc"
43 ReserveR9("arm-reserve-r9", cl::Hidden,
44 cl::desc("Reserve R9, making it unavailable as GPR"));
47 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
50 UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
59 static cl::opt<AlignMode>
60 Align(cl::desc("Load/store alignment support"),
61 cl::Hidden, cl::init(DefaultAlign),
63 clEnumValN(DefaultAlign, "arm-default-align",
64 "Generate unaligned accesses only on hardware/OS "
65 "combinations that are known to support them"),
66 clEnumValN(StrictAlign, "arm-strict-align",
67 "Disallow all unaligned memory accesses"),
68 clEnumValN(NoStrictAlign, "arm-no-strict-align",
69 "Allow unaligned memory accesses"),
78 static cl::opt<ITMode>
79 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
81 cl::values(clEnumValN(DefaultIT, "arm-default-it",
82 "Generate IT block based on arch"),
83 clEnumValN(RestrictedIT, "arm-restrict-it",
84 "Disallow deprecated IT based on ARMv8"),
85 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
86 "Allow IT blocks based on ARMv7"),
89 static std::string computeDataLayout(ARMSubtarget &ST) {
99 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
101 // Pointers are 32 bits and aligned to 32 bits.
104 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
107 Ret += "-i1:8:32-i8:8:32-i16:16:32";
109 // ABIs other than APCS have 64 bit integers with natural alignment.
110 if (!ST.isAPCS_ABI())
113 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
114 // bits, others to 64 bits. We always try to align to 64 bits.
118 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
119 // to 64. We always ty to give them natural alignment.
121 Ret += "-v64:32:64-v128:32:128";
123 Ret += "-v128:64:128";
125 // On thumb and APCS, only try to align aggregates to 32 bits (the default is
127 if (ST.isThumb() || ST.isAPCS_ABI())
130 // Integer registers are 32 bits.
133 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
134 // aligned everywhere else.
135 if (ST.isTargetNaCl())
137 else if (ST.isAAPCS_ABI())
145 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
146 /// so that we can use initializer lists for subtarget initialization.
147 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
149 initializeEnvironment();
150 resetSubtargetFeatures(CPU, FS);
154 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
155 const std::string &FS, TargetMachine &TM,
156 bool IsLittle, const TargetOptions &Options)
157 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
158 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
159 TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
160 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
161 TSInfo(DL), JITInfo(),
162 InstrInfo(isThumb1Only()
163 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
165 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
166 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
168 FrameLowering(!isThumb1Only()
169 ? new ARMFrameLowering(*this)
170 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
172 void ARMSubtarget::initializeEnvironment() {
186 UseNEONForSinglePrecisionFP = false;
187 UseMulOps = UseFusedMulOps;
189 HasVMLxForwarding = false;
194 IsR9Reserved = ReserveR9;
196 SupportsTailCall = false;
199 HasHardwareDivide = false;
200 HasHardwareDivideInARM = false;
201 HasT2ExtractPack = false;
202 HasDataBarrier = false;
203 Pref32BitThumb = false;
204 AvoidCPSRPartialUpdate = false;
205 AvoidMOVsShifterOperand = false;
207 HasMPExtension = false;
208 HasVirtualization = false;
211 HasTrustZone = false;
214 HasZeroCycleZeroing = false;
215 AllowsUnalignedMem = false;
218 UnsafeFPMath = false;
221 void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
222 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
223 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
225 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
228 !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
230 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
232 initializeEnvironment();
233 resetSubtargetFeatures(CPU, FS);
237 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
238 if (CPUString.empty()) {
239 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
240 // Default to the Swift CPU when targeting armv7s/thumbv7s.
243 CPUString = "generic";
246 // Insert the architecture feature derived from the target triple into the
247 // feature string. This is important for setting features that are implied
248 // based on the architecture version.
249 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
253 ArchFS = ArchFS + "," + FS.str();
257 ParseSubtargetFeatures(CPUString, ArchFS);
259 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
260 // Assert this for now to make the change obvious.
261 assert(hasV6T2Ops() || !hasThumb2());
263 // Keep a pointer to static instruction cost data for the specified CPU.
264 SchedModel = getSchedModelForCPU(CPUString);
266 // Initialize scheduling itinerary for the specified CPU.
267 InstrItins = getInstrItineraryForCPU(CPUString);
269 if (TargetABI == ARM_ABI_UNKNOWN) {
270 switch (TargetTriple.getEnvironment()) {
271 case Triple::Android:
274 case Triple::GNUEABI:
275 case Triple::GNUEABIHF:
276 TargetABI = ARM_ABI_AAPCS;
279 if ((isTargetIOS() && isMClass()) ||
280 (TargetTriple.isOSBinFormatMachO() &&
281 TargetTriple.getOS() == Triple::UnknownOS))
282 TargetABI = ARM_ABI_AAPCS;
284 TargetABI = ARM_ABI_APCS;
289 // FIXME: this is invalid for WindowsCE
290 if (isTargetWindows()) {
291 TargetABI = ARM_ABI_AAPCS;
300 UseMovt = hasV6T2Ops() && ArmUseMOVT;
302 if (isTargetMachO()) {
303 IsR9Reserved = ReserveR9 | !HasV6Ops;
304 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
306 IsR9Reserved = ReserveR9;
307 SupportsTailCall = !isThumb1Only();
312 // Assume pre-ARMv6 doesn't support unaligned accesses.
314 // ARMv6 may or may not support unaligned accesses depending on the
315 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
316 // Darwin and NetBSD targets support unaligned accesses, and others don't.
318 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
319 // which raises an alignment fault on unaligned accesses. Linux
320 // defaults this bit to 0 and handles it as a system-wide (not
321 // per-process) setting. It is therefore safe to assume that ARMv7+
322 // Linux targets support unaligned accesses. The same goes for NaCl.
324 // The above behavior is consistent with GCC.
326 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
327 isTargetNetBSD())) ||
328 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
329 // The one exception is cortex-m0, which despite being v6, does not
330 // support unaligned accesses. Rather than make the above boolean
331 // expression even more obtuse, just override the value here.
332 if (isThumb1Only() && isMClass())
333 AllowsUnalignedMem = false;
336 AllowsUnalignedMem = false;
339 AllowsUnalignedMem = true;
345 RestrictIT = hasV8Ops() ? true : false;
355 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
356 uint64_t Bits = getFeatureBits();
357 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
358 (Options.UnsafeFPMath || isTargetDarwin()))
359 UseNEONForSinglePrecisionFP = true;
362 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
364 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
365 Reloc::Model RelocM) const {
366 if (RelocM == Reloc::Static)
369 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
371 bool isDecl = GV->hasAvailableExternallyLinkage();
372 if (GV->isDeclaration() && !GV->isMaterializable())
375 if (!isTargetMachO()) {
376 // Extra load is needed for all externally visible.
377 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
381 if (RelocM == Reloc::PIC_) {
382 // If this is a strong reference to a definition, it is definitely not
384 if (!isDecl && !GV->isWeakForLinker())
387 // Unless we have a symbol with hidden visibility, we have to go through a
388 // normal $non_lazy_ptr stub because this symbol might be resolved late.
389 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
392 // If symbol visibility is hidden, we have a stub for common symbol
393 // references and external declarations.
394 if (isDecl || GV->hasCommonLinkage())
395 // Hidden $non_lazy_ptr reference.
400 // If this is a strong reference to a definition, it is definitely not
402 if (!isDecl && !GV->isWeakForLinker())
405 // Unless we have a symbol with hidden visibility, we have to go through a
406 // normal $non_lazy_ptr stub because this symbol might be resolved late.
407 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
415 unsigned ARMSubtarget::getMispredictionPenalty() const {
416 return SchedModel->MispredictPenalty;
419 bool ARMSubtarget::hasSinCos() const {
420 return getTargetTriple().getOS() == Triple::IOS &&
421 !getTargetTriple().isOSVersionLT(7, 0);
424 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
425 bool ARMSubtarget::enablePostMachineScheduler() const {
426 return (!isThumb() || hasThumb2());
429 bool ARMSubtarget::enableAtomicExpandLoadLinked() const {
430 return hasAnyDataBarrier() && !isThumb1Only();
433 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
434 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
435 // immediates as it is inherently position independent, and may be out of
437 return UseMovt && (isTargetWindows() ||
438 !MF.getFunction()->getAttributes().hasAttribute(
439 AttributeSet::FunctionIndex, Attribute::MinSize));
442 bool ARMSubtarget::shouldCoalesce(MachineInstr *MI,
443 const TargetRegisterClass *SrcRC,
445 const TargetRegisterClass *DstRC,
447 const TargetRegisterClass *NewRC) const {
448 auto MBB = MI->getParent();
449 auto MF = MBB->getParent();
450 const MachineRegisterInfo &MRI = MF->getRegInfo();
451 // If not copying into a sub-register this should be ok because we shouldn't
452 // need to split the reg.
455 // Small registers don't frequently cause a problem, so we can coalesce them.
456 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
460 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
462 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
464 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
465 // If the source register class is more expensive than the destination, the
466 // coalescing is probably profitable.
467 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
469 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
472 // If the register allocator isn't constrained, we can always allow coalescing
473 // unfortunately we don't know yet if we will be constrained.
474 // The goal of this heuristic is to restrict how many expensive registers
475 // we allow to coalesce in a given basic block.
476 auto AFI = MF->getInfo<ARMFunctionInfo>();
477 auto It = AFI->getCoalescedWeight(MBB);
479 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
480 << It->second << "\n");
481 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
482 << NewRCWeight.RegWeight << "\n");
484 // This number is the largest round number that which meets the criteria:
485 // (1) addresses PR18825
486 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
487 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
488 // In practice the SizeMultiplier will only factor in for straight line code
489 // that uses a lot of NEON vectors, which isn't terribly common.
490 unsigned SizeMultiplier = MBB->size()/100;
491 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
492 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
493 It->second += NewRCWeight.RegWeight;