1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
227 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
229 // These instruction are deprecated so we don't want them to get selected.
230 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
235 let Inst{24-23} = 0b01; // Increment After
236 let Inst{21} = 0; // No writeback
237 let Inst{20} = L_bit;
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
242 let Inst{24-23} = 0b01; // Increment After
243 let Inst{21} = 1; // Writeback
244 let Inst{20} = L_bit;
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
249 let Inst{24-23} = 0b10; // Decrement Before
251 let Inst{20} = L_bit;
255 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
256 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
258 //===----------------------------------------------------------------------===//
259 // FP Binary Operations.
262 let TwoOperandAliasConstraint = "$Dn = $Dd" in
263 def VADDD : ADbI<0b11100, 0b11, 0, 0,
264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
268 let TwoOperandAliasConstraint = "$Sn = $Sd" in
269 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
273 // Some single precision VFP instructions may be executed on both NEON and
274 // VFP pipelines on A8.
275 let D = VFPNeonA8Domain;
278 let TwoOperandAliasConstraint = "$Dn = $Dd" in
279 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
284 let TwoOperandAliasConstraint = "$Sn = $Sd" in
285 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
289 // Some single precision VFP instructions may be executed on both NEON and
290 // VFP pipelines on A8.
291 let D = VFPNeonA8Domain;
294 let TwoOperandAliasConstraint = "$Dn = $Dd" in
295 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
300 let TwoOperandAliasConstraint = "$Sn = $Sd" in
301 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
306 let TwoOperandAliasConstraint = "$Dn = $Dd" in
307 def VMULD : ADbI<0b11100, 0b10, 0, 0,
308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
312 let TwoOperandAliasConstraint = "$Sn = $Sd" in
313 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
327 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
331 // Some single precision VFP instructions may be executed on both NEON and
332 // VFP pipelines on A8.
333 let D = VFPNeonA8Domain;
336 multiclass vsel_inst<string op, bits<2> opc, int CC> {
337 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
338 Uses = [CPSR], AddedComplexity = 4 in {
339 def S : ASbInp<0b11100, opc, 0,
340 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
341 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
342 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
343 Requires<[HasFPARMv8]>;
345 def D : ADbInp<0b11100, opc, 0,
346 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
347 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
348 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
349 Requires<[HasFPARMv8]>;
353 // The CC constants here match ARMCC::CondCodes.
354 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
355 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
356 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
357 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
359 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
360 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
361 def S : ASbInp<0b11101, 0b00, opc,
362 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
363 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
364 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
365 Requires<[HasFPARMv8]>;
367 def D : ADbInp<0b11101, 0b00, opc,
368 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
369 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
370 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
371 Requires<[HasFPARMv8]>;
375 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
376 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
378 // Match reassociated forms only if not sign dependent rounding.
379 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
380 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
381 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
382 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
384 // These are encoded as unary instructions.
385 let Defs = [FPSCR_NZCV] in {
386 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
387 (outs), (ins DPR:$Dd, DPR:$Dm),
388 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
389 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
391 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
392 (outs), (ins SPR:$Sd, SPR:$Sm),
393 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
394 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
395 // Some single precision VFP instructions may be executed on both NEON and
396 // VFP pipelines on A8.
397 let D = VFPNeonA8Domain;
400 // FIXME: Verify encoding after integrated assembler is working.
401 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
402 (outs), (ins DPR:$Dd, DPR:$Dm),
403 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
404 [/* For disassembly only; pattern left blank */]>;
406 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
407 (outs), (ins SPR:$Sd, SPR:$Sm),
408 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
409 [/* For disassembly only; pattern left blank */]> {
410 // Some single precision VFP instructions may be executed on both NEON and
411 // VFP pipelines on A8.
412 let D = VFPNeonA8Domain;
414 } // Defs = [FPSCR_NZCV]
416 //===----------------------------------------------------------------------===//
417 // FP Unary Operations.
420 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
421 (outs DPR:$Dd), (ins DPR:$Dm),
422 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
423 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
425 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
426 (outs SPR:$Sd), (ins SPR:$Sm),
427 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
428 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
429 // Some single precision VFP instructions may be executed on both NEON and
430 // VFP pipelines on A8.
431 let D = VFPNeonA8Domain;
434 let Defs = [FPSCR_NZCV] in {
435 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
436 (outs), (ins DPR:$Dd),
437 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
438 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
439 let Inst{3-0} = 0b0000;
443 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
444 (outs), (ins SPR:$Sd),
445 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
446 [(arm_cmpfp0 SPR:$Sd)]> {
447 let Inst{3-0} = 0b0000;
450 // Some single precision VFP instructions may be executed on both NEON and
451 // VFP pipelines on A8.
452 let D = VFPNeonA8Domain;
455 // FIXME: Verify encoding after integrated assembler is working.
456 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
457 (outs), (ins DPR:$Dd),
458 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
459 [/* For disassembly only; pattern left blank */]> {
460 let Inst{3-0} = 0b0000;
464 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
465 (outs), (ins SPR:$Sd),
466 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
467 [/* For disassembly only; pattern left blank */]> {
468 let Inst{3-0} = 0b0000;
471 // Some single precision VFP instructions may be executed on both NEON and
472 // VFP pipelines on A8.
473 let D = VFPNeonA8Domain;
475 } // Defs = [FPSCR_NZCV]
477 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
478 (outs DPR:$Dd), (ins SPR:$Sm),
479 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
480 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
481 // Instruction operands.
485 // Encode instruction operands.
486 let Inst{3-0} = Sm{4-1};
488 let Inst{15-12} = Dd{3-0};
489 let Inst{22} = Dd{4};
492 // Special case encoding: bits 11-8 is 0b1011.
493 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
494 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
495 [(set SPR:$Sd, (fround DPR:$Dm))]> {
496 // Instruction operands.
500 // Encode instruction operands.
501 let Inst{3-0} = Dm{3-0};
503 let Inst{15-12} = Sd{4-1};
504 let Inst{22} = Sd{0};
506 let Inst{27-23} = 0b11101;
507 let Inst{21-16} = 0b110111;
508 let Inst{11-8} = 0b1011;
509 let Inst{7-6} = 0b11;
513 // Between half, single and double-precision. For disassembly only.
515 // FIXME: Verify encoding after integrated assembler is working.
516 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
517 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
518 [/* For disassembly only; pattern left blank */]>;
520 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
521 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
522 [/* For disassembly only; pattern left blank */]>;
524 def : Pat<(f32_to_f16 SPR:$a),
525 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
527 def : Pat<(f16_to_f32 GPR:$a),
528 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
530 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
531 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
532 [/* For disassembly only; pattern left blank */]>;
534 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
535 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
536 [/* For disassembly only; pattern left blank */]>;
538 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
539 (outs DPR:$Dd), (ins SPR:$Sm),
540 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
541 []>, Requires<[HasFPARMv8]> {
542 // Instruction operands.
545 // Encode instruction operands.
546 let Inst{3-0} = Sm{4-1};
550 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
551 (outs SPR:$Sd), (ins DPR:$Dm),
552 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
553 []>, Requires<[HasFPARMv8]> {
554 // Instruction operands.
558 // Encode instruction operands.
559 let Inst{3-0} = Dm{3-0};
561 let Inst{15-12} = Sd{4-1};
562 let Inst{22} = Sd{0};
565 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
566 (outs DPR:$Dd), (ins SPR:$Sm),
567 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
568 []>, Requires<[HasFPARMv8]> {
569 // Instruction operands.
572 // Encode instruction operands.
573 let Inst{3-0} = Sm{4-1};
577 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
578 (outs SPR:$Sd), (ins DPR:$Dm),
579 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
580 []>, Requires<[HasFPARMv8]> {
581 // Instruction operands.
585 // Encode instruction operands.
586 let Inst{15-12} = Sd{4-1};
587 let Inst{22} = Sd{0};
588 let Inst{3-0} = Dm{3-0};
592 multiclass vcvt_inst<string opc, bits<2> rm> {
593 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
594 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
595 (outs SPR:$Sd), (ins SPR:$Sm),
596 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
597 []>, Requires<[HasFPARMv8]> {
598 let Inst{17-16} = rm;
601 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
602 (outs SPR:$Sd), (ins SPR:$Sm),
603 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
604 []>, Requires<[HasFPARMv8]> {
605 let Inst{17-16} = rm;
608 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
609 (outs SPR:$Sd), (ins DPR:$Dm),
610 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
611 []>, Requires<[HasFPARMv8]> {
614 let Inst{17-16} = rm;
616 // Encode instruction operands
617 let Inst{3-0} = Dm{3-0};
622 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
623 (outs SPR:$Sd), (ins DPR:$Dm),
624 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
625 []>, Requires<[HasFPARMv8]> {
628 let Inst{17-16} = rm;
630 // Encode instruction operands
631 let Inst{3-0} = Dm{3-0};
638 defm VCVTA : vcvt_inst<"a", 0b00>;
639 defm VCVTN : vcvt_inst<"n", 0b01>;
640 defm VCVTP : vcvt_inst<"p", 0b10>;
641 defm VCVTM : vcvt_inst<"m", 0b11>;
643 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
644 (outs DPR:$Dd), (ins DPR:$Dm),
645 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
646 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
648 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
649 (outs SPR:$Sd), (ins SPR:$Sm),
650 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
651 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
652 // Some single precision VFP instructions may be executed on both NEON and
653 // VFP pipelines on A8.
654 let D = VFPNeonA8Domain;
657 multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
658 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
659 (outs SPR:$Sd), (ins SPR:$Sm),
660 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
661 []>, Requires<[HasFPARMv8]> {
665 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
666 (outs DPR:$Dd), (ins DPR:$Dm),
667 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
668 []>, Requires<[HasFPARMv8]> {
673 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
674 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
675 Requires<[HasFPARMv8]>;
676 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
677 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
678 Requires<[HasFPARMv8]>;
681 defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
682 defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
683 defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
685 multiclass vrint_inst_anpm<string opc, bits<2> rm> {
686 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
687 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
688 (outs SPR:$Sd), (ins SPR:$Sm),
689 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
690 []>, Requires<[HasFPARMv8]> {
691 let Inst{17-16} = rm;
693 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
694 (outs DPR:$Dd), (ins DPR:$Dm),
695 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
696 []>, Requires<[HasFPARMv8]> {
697 let Inst{17-16} = rm;
701 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
702 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
703 Requires<[HasFPARMv8]>;
704 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
705 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
706 Requires<[HasFPARMv8]>;
709 defm VRINTA : vrint_inst_anpm<"a", 0b00>;
710 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
711 defm VRINTP : vrint_inst_anpm<"p", 0b10>;
712 defm VRINTM : vrint_inst_anpm<"m", 0b11>;
714 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
715 (outs DPR:$Dd), (ins DPR:$Dm),
716 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
717 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
719 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
720 (outs SPR:$Sd), (ins SPR:$Sm),
721 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
722 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
724 let neverHasSideEffects = 1 in {
725 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
726 (outs DPR:$Dd), (ins DPR:$Dm),
727 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
729 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
730 (outs SPR:$Sd), (ins SPR:$Sm),
731 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
732 } // neverHasSideEffects
734 //===----------------------------------------------------------------------===//
735 // FP <-> GPR Copies. Int <-> FP Conversions.
738 def VMOVRS : AVConv2I<0b11100001, 0b1010,
739 (outs GPR:$Rt), (ins SPR:$Sn),
740 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
741 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
742 // Instruction operands.
746 // Encode instruction operands.
747 let Inst{19-16} = Sn{4-1};
749 let Inst{15-12} = Rt;
751 let Inst{6-5} = 0b00;
752 let Inst{3-0} = 0b0000;
754 // Some single precision VFP instructions may be executed on both NEON and VFP
756 let D = VFPNeonDomain;
759 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
760 def VMOVSR : AVConv4I<0b11100000, 0b1010,
761 (outs SPR:$Sn), (ins GPR:$Rt),
762 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
763 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
764 Requires<[HasVFP2, UseVMOVSR]> {
765 // Instruction operands.
769 // Encode instruction operands.
770 let Inst{19-16} = Sn{4-1};
772 let Inst{15-12} = Rt;
774 let Inst{6-5} = 0b00;
775 let Inst{3-0} = 0b0000;
777 // Some single precision VFP instructions may be executed on both NEON and VFP
779 let D = VFPNeonDomain;
782 let neverHasSideEffects = 1 in {
783 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
784 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
785 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
786 [/* FIXME: Can't write pattern for multiple result instr*/]> {
787 // Instruction operands.
792 // Encode instruction operands.
793 let Inst{3-0} = Dm{3-0};
795 let Inst{15-12} = Rt;
796 let Inst{19-16} = Rt2;
798 let Inst{7-6} = 0b00;
800 // Some single precision VFP instructions may be executed on both NEON and VFP
802 let D = VFPNeonDomain;
805 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
806 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
807 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
808 [/* For disassembly only; pattern left blank */]> {
813 // Encode instruction operands.
814 let Inst{3-0} = src1{4-1};
815 let Inst{5} = src1{0};
816 let Inst{15-12} = Rt;
817 let Inst{19-16} = Rt2;
819 let Inst{7-6} = 0b00;
821 // Some single precision VFP instructions may be executed on both NEON and VFP
823 let D = VFPNeonDomain;
824 let DecoderMethod = "DecodeVMOVRRS";
826 } // neverHasSideEffects
831 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
832 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
833 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
834 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
835 // Instruction operands.
840 // Encode instruction operands.
841 let Inst{3-0} = Dm{3-0};
843 let Inst{15-12} = Rt;
844 let Inst{19-16} = Rt2;
846 let Inst{7-6} = 0b00;
848 // Some single precision VFP instructions may be executed on both NEON and VFP
850 let D = VFPNeonDomain;
853 let neverHasSideEffects = 1 in
854 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
855 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
856 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
857 [/* For disassembly only; pattern left blank */]> {
858 // Instruction operands.
863 // Encode instruction operands.
864 let Inst{3-0} = dst1{4-1};
865 let Inst{5} = dst1{0};
866 let Inst{15-12} = src1;
867 let Inst{19-16} = src2;
869 let Inst{7-6} = 0b00;
871 // Some single precision VFP instructions may be executed on both NEON and VFP
873 let D = VFPNeonDomain;
875 let DecoderMethod = "DecodeVMOVSRR";
881 // FMRX: SPR system reg -> GPR
883 // FMXR: GPR -> VFP system reg
888 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
889 bits<4> opcod4, dag oops, dag iops,
890 InstrItinClass itin, string opc, string asm,
892 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
894 // Instruction operands.
898 // Encode instruction operands.
899 let Inst{3-0} = Sm{4-1};
901 let Inst{15-12} = Dd{3-0};
902 let Inst{22} = Dd{4};
905 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
906 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
907 string opc, string asm, list<dag> pattern>
908 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
910 // Instruction operands.
914 // Encode instruction operands.
915 let Inst{3-0} = Sm{4-1};
917 let Inst{15-12} = Sd{4-1};
918 let Inst{22} = Sd{0};
921 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
922 (outs DPR:$Dd), (ins SPR:$Sm),
923 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
924 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
925 let Inst{7} = 1; // s32
928 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
929 (outs SPR:$Sd),(ins SPR:$Sm),
930 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
931 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
932 let Inst{7} = 1; // s32
934 // Some single precision VFP instructions may be executed on both NEON and
935 // VFP pipelines on A8.
936 let D = VFPNeonA8Domain;
939 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
940 (outs DPR:$Dd), (ins SPR:$Sm),
941 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
942 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
943 let Inst{7} = 0; // u32
946 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
947 (outs SPR:$Sd), (ins SPR:$Sm),
948 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
949 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
950 let Inst{7} = 0; // u32
952 // Some single precision VFP instructions may be executed on both NEON and
953 // VFP pipelines on A8.
954 let D = VFPNeonA8Domain;
959 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
960 bits<4> opcod4, dag oops, dag iops,
961 InstrItinClass itin, string opc, string asm,
963 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
965 // Instruction operands.
969 // Encode instruction operands.
970 let Inst{3-0} = Dm{3-0};
972 let Inst{15-12} = Sd{4-1};
973 let Inst{22} = Sd{0};
976 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
977 bits<4> opcod4, dag oops, dag iops,
978 InstrItinClass itin, string opc, string asm,
980 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
982 // Instruction operands.
986 // Encode instruction operands.
987 let Inst{3-0} = Sm{4-1};
989 let Inst{15-12} = Sd{4-1};
990 let Inst{22} = Sd{0};
993 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
994 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
995 (outs SPR:$Sd), (ins DPR:$Dm),
996 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
997 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
998 let Inst{7} = 1; // Z bit
1001 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1002 (outs SPR:$Sd), (ins SPR:$Sm),
1003 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1004 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
1005 let Inst{7} = 1; // Z bit
1007 // Some single precision VFP instructions may be executed on both NEON and
1008 // VFP pipelines on A8.
1009 let D = VFPNeonA8Domain;
1012 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1013 (outs SPR:$Sd), (ins DPR:$Dm),
1014 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1015 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
1016 let Inst{7} = 1; // Z bit
1019 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1020 (outs SPR:$Sd), (ins SPR:$Sm),
1021 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1022 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
1023 let Inst{7} = 1; // Z bit
1025 // Some single precision VFP instructions may be executed on both NEON and
1026 // VFP pipelines on A8.
1027 let D = VFPNeonA8Domain;
1030 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1031 let Uses = [FPSCR] in {
1032 // FIXME: Verify encoding after integrated assembler is working.
1033 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1034 (outs SPR:$Sd), (ins DPR:$Dm),
1035 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1036 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1037 let Inst{7} = 0; // Z bit
1040 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1041 (outs SPR:$Sd), (ins SPR:$Sm),
1042 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1043 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1044 let Inst{7} = 0; // Z bit
1047 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1048 (outs SPR:$Sd), (ins DPR:$Dm),
1049 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1050 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1051 let Inst{7} = 0; // Z bit
1054 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1055 (outs SPR:$Sd), (ins SPR:$Sm),
1056 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1057 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1058 let Inst{7} = 0; // Z bit
1062 // Convert between floating-point and fixed-point
1063 // Data type for fixed-point naming convention:
1064 // S16 (U=0, sx=0) -> SH
1065 // U16 (U=1, sx=0) -> UH
1066 // S32 (U=0, sx=1) -> SL
1067 // U32 (U=1, sx=1) -> UL
1069 let Constraints = "$a = $dst" in {
1071 // FP to Fixed-Point:
1073 // Single Precision register
1074 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1075 bit op5, dag oops, dag iops, InstrItinClass itin,
1076 string opc, string asm, list<dag> pattern>
1077 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1078 Sched<[WriteCvtFP]> {
1080 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1081 let Inst{22} = dst{0};
1082 let Inst{15-12} = dst{4-1};
1085 // Double Precision register
1086 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1087 bit op5, dag oops, dag iops, InstrItinClass itin,
1088 string opc, string asm, list<dag> pattern>
1089 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1090 Sched<[WriteCvtFP]> {
1092 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1093 let Inst{22} = dst{4};
1094 let Inst{15-12} = dst{3-0};
1097 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1098 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1099 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1100 // Some single precision VFP instructions may be executed on both NEON and
1101 // VFP pipelines on A8.
1102 let D = VFPNeonA8Domain;
1105 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1106 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1107 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1108 // Some single precision VFP instructions may be executed on both NEON and
1109 // VFP pipelines on A8.
1110 let D = VFPNeonA8Domain;
1113 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1114 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1115 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1116 // Some single precision VFP instructions may be executed on both NEON and
1117 // VFP pipelines on A8.
1118 let D = VFPNeonA8Domain;
1121 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1122 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1123 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1124 // Some single precision VFP instructions may be executed on both NEON and
1125 // VFP pipelines on A8.
1126 let D = VFPNeonA8Domain;
1129 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1130 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1131 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1133 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1134 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1135 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1137 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1138 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1139 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1141 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1142 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1143 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1145 // Fixed-Point to FP:
1147 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1148 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1149 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1150 // Some single precision VFP instructions may be executed on both NEON and
1151 // VFP pipelines on A8.
1152 let D = VFPNeonA8Domain;
1155 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1156 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1157 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1158 // Some single precision VFP instructions may be executed on both NEON and
1159 // VFP pipelines on A8.
1160 let D = VFPNeonA8Domain;
1163 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1164 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1165 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1166 // Some single precision VFP instructions may be executed on both NEON and
1167 // VFP pipelines on A8.
1168 let D = VFPNeonA8Domain;
1171 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1172 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1173 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1174 // Some single precision VFP instructions may be executed on both NEON and
1175 // VFP pipelines on A8.
1176 let D = VFPNeonA8Domain;
1179 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1180 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1181 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1183 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1184 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1185 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1187 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1188 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1189 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1191 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1192 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1193 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1195 } // End of 'let Constraints = "$a = $dst" in'
1197 //===----------------------------------------------------------------------===//
1198 // FP Multiply-Accumulate Operations.
1201 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1202 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1203 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1204 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1205 (f64 DPR:$Ddin)))]>,
1206 RegConstraint<"$Ddin = $Dd">,
1207 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1209 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1210 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1211 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1212 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1214 RegConstraint<"$Sdin = $Sd">,
1215 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1216 // Some single precision VFP instructions may be executed on both NEON and
1217 // VFP pipelines on A8.
1218 let D = VFPNeonA8Domain;
1221 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1222 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1223 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1224 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1225 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1226 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1228 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1229 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1230 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1231 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1232 (f64 DPR:$Ddin)))]>,
1233 RegConstraint<"$Ddin = $Dd">,
1234 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1236 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1237 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1238 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1239 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1241 RegConstraint<"$Sdin = $Sd">,
1242 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1243 // Some single precision VFP instructions may be executed on both NEON and
1244 // VFP pipelines on A8.
1245 let D = VFPNeonA8Domain;
1248 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1249 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1250 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1251 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1252 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1253 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1255 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1256 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1257 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1258 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1259 (f64 DPR:$Ddin)))]>,
1260 RegConstraint<"$Ddin = $Dd">,
1261 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1263 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1264 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1265 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1266 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1268 RegConstraint<"$Sdin = $Sd">,
1269 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1270 // Some single precision VFP instructions may be executed on both NEON and
1271 // VFP pipelines on A8.
1272 let D = VFPNeonA8Domain;
1275 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1276 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1277 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1278 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1279 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1280 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1282 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1283 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1284 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1285 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1286 (f64 DPR:$Ddin)))]>,
1287 RegConstraint<"$Ddin = $Dd">,
1288 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1290 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1291 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1292 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1293 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1294 RegConstraint<"$Sdin = $Sd">,
1295 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1296 // Some single precision VFP instructions may be executed on both NEON and
1297 // VFP pipelines on A8.
1298 let D = VFPNeonA8Domain;
1301 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1302 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1303 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1304 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1305 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1306 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1308 //===----------------------------------------------------------------------===//
1309 // Fused FP Multiply-Accumulate Operations.
1311 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1312 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1313 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1314 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1315 (f64 DPR:$Ddin)))]>,
1316 RegConstraint<"$Ddin = $Dd">,
1317 Requires<[HasVFP4,UseFusedMAC]>;
1319 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1320 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1321 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1322 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1324 RegConstraint<"$Sdin = $Sd">,
1325 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1326 // Some single precision VFP instructions may be executed on both NEON and
1330 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1331 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1332 Requires<[HasVFP4,UseFusedMAC]>;
1333 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1334 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1335 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1337 // Match @llvm.fma.* intrinsics
1338 // (fma x, y, z) -> (vfms z, x, y)
1339 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1340 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1341 Requires<[HasVFP4]>;
1342 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1343 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1344 Requires<[HasVFP4]>;
1346 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1347 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1348 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1349 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1350 (f64 DPR:$Ddin)))]>,
1351 RegConstraint<"$Ddin = $Dd">,
1352 Requires<[HasVFP4,UseFusedMAC]>;
1354 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1355 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1356 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1357 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1359 RegConstraint<"$Sdin = $Sd">,
1360 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1361 // Some single precision VFP instructions may be executed on both NEON and
1365 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1366 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1367 Requires<[HasVFP4,UseFusedMAC]>;
1368 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1369 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1370 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1372 // Match @llvm.fma.* intrinsics
1373 // (fma (fneg x), y, z) -> (vfms z, x, y)
1374 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1375 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1376 Requires<[HasVFP4]>;
1377 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1378 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1379 Requires<[HasVFP4]>;
1380 // (fma x, (fneg y), z) -> (vfms z, x, y)
1381 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1382 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1383 Requires<[HasVFP4]>;
1384 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1385 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1386 Requires<[HasVFP4]>;
1388 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1389 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1390 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1391 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1392 (f64 DPR:$Ddin)))]>,
1393 RegConstraint<"$Ddin = $Dd">,
1394 Requires<[HasVFP4,UseFusedMAC]>;
1396 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1397 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1398 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1399 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1401 RegConstraint<"$Sdin = $Sd">,
1402 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1403 // Some single precision VFP instructions may be executed on both NEON and
1407 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1408 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1409 Requires<[HasVFP4,UseFusedMAC]>;
1410 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1411 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1412 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1414 // Match @llvm.fma.* intrinsics
1415 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1416 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1417 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1418 Requires<[HasVFP4]>;
1419 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1420 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1421 Requires<[HasVFP4]>;
1422 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1423 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1424 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1425 Requires<[HasVFP4]>;
1426 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1427 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1428 Requires<[HasVFP4]>;
1430 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1431 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1432 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1433 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1434 (f64 DPR:$Ddin)))]>,
1435 RegConstraint<"$Ddin = $Dd">,
1436 Requires<[HasVFP4,UseFusedMAC]>;
1438 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1439 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1440 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1441 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1442 RegConstraint<"$Sdin = $Sd">,
1443 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1444 // Some single precision VFP instructions may be executed on both NEON and
1448 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1449 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1450 Requires<[HasVFP4,UseFusedMAC]>;
1451 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1452 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1453 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1455 // Match @llvm.fma.* intrinsics
1457 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1458 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1459 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1460 Requires<[HasVFP4]>;
1461 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1462 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1463 Requires<[HasVFP4]>;
1464 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1465 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1466 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1467 Requires<[HasVFP4]>;
1468 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1469 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1470 Requires<[HasVFP4]>;
1471 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1472 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1473 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1474 Requires<[HasVFP4]>;
1475 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1476 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1477 Requires<[HasVFP4]>;
1479 //===----------------------------------------------------------------------===//
1480 // FP Conditional moves.
1483 let neverHasSideEffects = 1 in {
1484 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1486 [(set (f64 DPR:$Dd),
1487 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1488 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2]>;
1490 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1492 [(set (f32 SPR:$Sd),
1493 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1494 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1495 } // neverHasSideEffects
1497 //===----------------------------------------------------------------------===//
1498 // Move from VFP System Register to ARM core register.
1501 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1503 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1505 // Instruction operand.
1508 let Inst{27-20} = 0b11101111;
1509 let Inst{19-16} = opc19_16;
1510 let Inst{15-12} = Rt;
1511 let Inst{11-8} = 0b1010;
1513 let Inst{6-5} = 0b00;
1515 let Inst{3-0} = 0b0000;
1518 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1520 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1521 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1522 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1524 // Application level FPSCR -> GPR
1525 let hasSideEffects = 1, Uses = [FPSCR] in
1526 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1527 "vmrs", "\t$Rt, fpscr",
1528 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1530 // System level FPEXC, FPSID -> GPR
1531 let Uses = [FPSCR] in {
1532 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1533 "vmrs", "\t$Rt, fpexc", []>;
1534 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1535 "vmrs", "\t$Rt, fpsid", []>;
1536 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1537 "vmrs", "\t$Rt, mvfr0", []>;
1538 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1539 "vmrs", "\t$Rt, mvfr1", []>;
1540 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1541 "vmrs", "\t$Rt, fpinst", []>;
1542 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1543 "vmrs", "\t$Rt, fpinst2", []>;
1546 //===----------------------------------------------------------------------===//
1547 // Move from ARM core register to VFP System Register.
1550 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1552 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1554 // Instruction operand.
1557 // Encode instruction operand.
1558 let Inst{15-12} = src;
1560 let Inst{27-20} = 0b11101110;
1561 let Inst{19-16} = opc19_16;
1562 let Inst{11-8} = 0b1010;
1567 let Defs = [FPSCR] in {
1568 // Application level GPR -> FPSCR
1569 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1570 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1571 // System level GPR -> FPEXC
1572 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1573 "vmsr", "\tfpexc, $src", []>;
1574 // System level GPR -> FPSID
1575 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1576 "vmsr", "\tfpsid, $src", []>;
1578 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1579 "vmsr", "\tfpinst, $src", []>;
1580 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1581 "vmsr", "\tfpinst2, $src", []>;
1584 //===----------------------------------------------------------------------===//
1588 // Materialize FP immediates. VFP3 only.
1589 let isReMaterializable = 1 in {
1590 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1591 VFPMiscFrm, IIC_fpUNA64,
1592 "vmov", ".f64\t$Dd, $imm",
1593 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1597 let Inst{27-23} = 0b11101;
1598 let Inst{22} = Dd{4};
1599 let Inst{21-20} = 0b11;
1600 let Inst{19-16} = imm{7-4};
1601 let Inst{15-12} = Dd{3-0};
1602 let Inst{11-9} = 0b101;
1603 let Inst{8} = 1; // Double precision.
1604 let Inst{7-4} = 0b0000;
1605 let Inst{3-0} = imm{3-0};
1608 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1609 VFPMiscFrm, IIC_fpUNA32,
1610 "vmov", ".f32\t$Sd, $imm",
1611 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1615 let Inst{27-23} = 0b11101;
1616 let Inst{22} = Sd{0};
1617 let Inst{21-20} = 0b11;
1618 let Inst{19-16} = imm{7-4};
1619 let Inst{15-12} = Sd{4-1};
1620 let Inst{11-9} = 0b101;
1621 let Inst{8} = 0; // Single precision.
1622 let Inst{7-4} = 0b0000;
1623 let Inst{3-0} = imm{3-0};
1627 //===----------------------------------------------------------------------===//
1628 // Assembler aliases.
1630 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1631 // support them all, but supporting at least some of the basics is
1632 // good to be friendly.
1633 def : VFP2MnemonicAlias<"flds", "vldr">;
1634 def : VFP2MnemonicAlias<"fldd", "vldr">;
1635 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1636 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1637 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1638 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1639 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1640 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1641 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1642 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1643 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1644 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1645 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1646 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1647 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1648 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1649 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1650 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1651 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1652 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1653 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1654 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1655 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1656 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1657 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1658 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1659 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1660 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1661 def : VFP2MnemonicAlias<"fsts", "vstr">;
1662 def : VFP2MnemonicAlias<"fstd", "vstr">;
1663 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1664 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1665 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1666 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1667 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1668 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1669 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1670 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1671 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1672 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1674 // Be friendly and accept the old form of zero-compare
1675 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1676 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1679 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1680 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1681 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1682 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1683 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1684 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1685 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1686 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1687 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1689 // No need for the size suffix on VSQRT. It's implied by the register classes.
1690 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1691 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1693 // VLDR/VSTR accept an optional type suffix.
1694 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1695 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1696 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1697 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1698 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1699 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1700 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1701 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1703 // VMOV can accept optional 32-bit or less data type suffix suffix.
1704 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1705 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1706 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1707 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1708 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1709 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1710 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1711 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1712 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1713 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1714 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1715 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1717 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1718 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1719 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1720 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1722 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1724 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1725 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;