1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
15 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
18 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
19 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
20 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
21 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
24 //===----------------------------------------------------------------------===//
25 // Operand Definitions.
28 // 8-bit floating-point immediate encodings.
29 def FPImmOperand : AsmOperandClass {
31 let ParserMethod = "parseFPImm";
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
37 }], SDNodeXForm<fpimm, [{
38 APFloat InVal = N->getValueAPF();
39 uint32_t enc = ARM_AM::getFP32Imm(InVal);
40 return CurDAG->getTargetConstant(enc, MVT::i32);
42 let PrintMethod = "printFPImmOperand";
43 let ParserMatchClass = FPImmOperand;
46 def vfp_f64imm : Operand<f64>,
47 PatLeaf<(f64 fpimm), [{
48 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
49 }], SDNodeXForm<fpimm, [{
50 APFloat InVal = N->getValueAPF();
51 uint32_t enc = ARM_AM::getFP64Imm(InVal);
52 return CurDAG->getTargetConstant(enc, MVT::i32);
54 let PrintMethod = "printFPImmOperand";
55 let ParserMatchClass = FPImmOperand;
58 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
59 return cast<LoadSDNode>(N)->getAlignment() >= 4;
62 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
63 (store node:$val, node:$ptr), [{
64 return cast<StoreSDNode>(N)->getAlignment() >= 4;
67 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
68 // (the number of fixed bits) differently than it appears in the assembly
69 // source. It's encoded as "Size - fbits" where Size is the size of the
70 // fixed-point representation (32 or 16) and fbits is the value appearing
71 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
72 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
73 def fbits32 : Operand<i32> {
74 let PrintMethod = "printFBits32";
75 let ParserMatchClass = fbits32_asm_operand;
78 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
79 def fbits16 : Operand<i32> {
80 let PrintMethod = "printFBits16";
81 let ParserMatchClass = fbits16_asm_operand;
84 //===----------------------------------------------------------------------===//
85 // Load / store Instructions.
88 let canFoldAsLoad = 1, isReMaterializable = 1 in {
90 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
91 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
92 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
94 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
95 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
96 [(set SPR:$Sd, (load addrmode5:$addr))]> {
97 // Some single precision VFP instructions may be executed on both NEON and VFP
99 let D = VFPNeonDomain;
102 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
104 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
105 IIC_fpStore64, "vstr", "\t$Dd, $addr",
106 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
108 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
109 IIC_fpStore32, "vstr", "\t$Sd, $addr",
110 [(store SPR:$Sd, addrmode5:$addr)]> {
111 // Some single precision VFP instructions may be executed on both NEON and VFP
113 let D = VFPNeonDomain;
116 //===----------------------------------------------------------------------===//
117 // Load / store multiple Instructions.
120 multiclass vfp_ldst_mult<string asm, bit L_bit,
121 InstrItinClass itin, InstrItinClass itin_upd> {
124 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
126 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
127 let Inst{24-23} = 0b01; // Increment After
128 let Inst{21} = 0; // No writeback
129 let Inst{20} = L_bit;
132 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
134 IndexModeUpd, itin_upd,
135 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
136 let Inst{24-23} = 0b01; // Increment After
137 let Inst{21} = 1; // Writeback
138 let Inst{20} = L_bit;
141 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
143 IndexModeUpd, itin_upd,
144 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
145 let Inst{24-23} = 0b10; // Decrement Before
146 let Inst{21} = 1; // Writeback
147 let Inst{20} = L_bit;
152 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
154 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
155 let Inst{24-23} = 0b01; // Increment After
156 let Inst{21} = 0; // No writeback
157 let Inst{20} = L_bit;
159 // Some single precision VFP instructions may be executed on both NEON and
161 let D = VFPNeonDomain;
164 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
166 IndexModeUpd, itin_upd,
167 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
168 let Inst{24-23} = 0b01; // Increment After
169 let Inst{21} = 1; // Writeback
170 let Inst{20} = L_bit;
172 // Some single precision VFP instructions may be executed on both NEON and
174 let D = VFPNeonDomain;
177 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
179 IndexModeUpd, itin_upd,
180 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
181 let Inst{24-23} = 0b10; // Decrement Before
182 let Inst{21} = 1; // Writeback
183 let Inst{20} = L_bit;
185 // Some single precision VFP instructions may be executed on both NEON and
187 let D = VFPNeonDomain;
191 let hasSideEffects = 0 in {
193 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
194 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
196 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
197 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
201 def : MnemonicAlias<"vldm", "vldmia">;
202 def : MnemonicAlias<"vstm", "vstmia">;
204 // FLDM/FSTM - Load / Store multiple single / double precision registers for
206 // These instructions are deprecated!
207 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
208 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
209 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
210 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
211 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
212 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
213 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
214 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
216 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
217 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
218 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
219 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
220 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
221 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
222 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
223 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
225 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
227 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
229 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
231 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
233 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
234 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
235 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
236 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
237 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
238 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
239 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
240 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
242 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
244 // These instruction are deprecated so we don't want them to get selected.
245 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
248 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
249 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
250 let Inst{24-23} = 0b01; // Increment After
251 let Inst{21} = 0; // No writeback
252 let Inst{20} = L_bit;
255 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
256 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
257 let Inst{24-23} = 0b01; // Increment After
258 let Inst{21} = 1; // Writeback
259 let Inst{20} = L_bit;
262 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
263 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
264 let Inst{24-23} = 0b10; // Decrement Before
265 let Inst{21} = 1; // Writeback
266 let Inst{20} = L_bit;
270 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
271 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
273 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
274 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
276 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
277 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
279 //===----------------------------------------------------------------------===//
280 // FP Binary Operations.
283 let TwoOperandAliasConstraint = "$Dn = $Dd" in
284 def VADDD : ADbI<0b11100, 0b11, 0, 0,
285 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
286 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
287 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
289 let TwoOperandAliasConstraint = "$Sn = $Sd" in
290 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
291 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
292 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
293 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
294 // Some single precision VFP instructions may be executed on both NEON and
295 // VFP pipelines on A8.
296 let D = VFPNeonA8Domain;
299 let TwoOperandAliasConstraint = "$Dn = $Dd" in
300 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
301 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
302 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
303 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
305 let TwoOperandAliasConstraint = "$Sn = $Sd" in
306 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
307 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
308 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
309 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
310 // Some single precision VFP instructions may be executed on both NEON and
311 // VFP pipelines on A8.
312 let D = VFPNeonA8Domain;
315 let TwoOperandAliasConstraint = "$Dn = $Dd" in
316 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
317 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
318 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
319 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
321 let TwoOperandAliasConstraint = "$Sn = $Sd" in
322 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
323 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
324 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
325 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
327 let TwoOperandAliasConstraint = "$Dn = $Dd" in
328 def VMULD : ADbI<0b11100, 0b10, 0, 0,
329 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
330 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
331 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
333 let TwoOperandAliasConstraint = "$Sn = $Sd" in
334 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
335 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
336 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
337 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
338 // Some single precision VFP instructions may be executed on both NEON and
339 // VFP pipelines on A8.
340 let D = VFPNeonA8Domain;
343 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
344 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
345 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
346 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
348 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
349 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
350 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
351 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
352 // Some single precision VFP instructions may be executed on both NEON and
353 // VFP pipelines on A8.
354 let D = VFPNeonA8Domain;
357 multiclass vsel_inst<string op, bits<2> opc, int CC> {
358 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
359 Uses = [CPSR], AddedComplexity = 4 in {
360 def S : ASbInp<0b11100, opc, 0,
361 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
362 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
363 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
364 Requires<[HasFPARMv8]>;
366 def D : ADbInp<0b11100, opc, 0,
367 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
368 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
369 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
370 Requires<[HasFPARMv8, HasDPVFP]>;
374 // The CC constants here match ARMCC::CondCodes.
375 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
376 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
377 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
378 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
380 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
381 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
382 def S : ASbInp<0b11101, 0b00, opc,
383 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
384 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
385 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
386 Requires<[HasFPARMv8]>;
388 def D : ADbInp<0b11101, 0b00, opc,
389 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
390 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
391 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
392 Requires<[HasFPARMv8, HasDPVFP]>;
396 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
397 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
399 // Match reassociated forms only if not sign dependent rounding.
400 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
401 (VNMULD DPR:$a, DPR:$b)>,
402 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
403 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
404 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
406 // These are encoded as unary instructions.
407 let Defs = [FPSCR_NZCV] in {
408 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
409 (outs), (ins DPR:$Dd, DPR:$Dm),
410 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
411 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
413 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
414 (outs), (ins SPR:$Sd, SPR:$Sm),
415 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
416 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
417 // Some single precision VFP instructions may be executed on both NEON and
418 // VFP pipelines on A8.
419 let D = VFPNeonA8Domain;
422 // FIXME: Verify encoding after integrated assembler is working.
423 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
424 (outs), (ins DPR:$Dd, DPR:$Dm),
425 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
426 [/* For disassembly only; pattern left blank */]>;
428 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
429 (outs), (ins SPR:$Sd, SPR:$Sm),
430 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
431 [/* For disassembly only; pattern left blank */]> {
432 // Some single precision VFP instructions may be executed on both NEON and
433 // VFP pipelines on A8.
434 let D = VFPNeonA8Domain;
436 } // Defs = [FPSCR_NZCV]
438 //===----------------------------------------------------------------------===//
439 // FP Unary Operations.
442 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
443 (outs DPR:$Dd), (ins DPR:$Dm),
444 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
445 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
447 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
448 (outs SPR:$Sd), (ins SPR:$Sm),
449 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
450 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
451 // Some single precision VFP instructions may be executed on both NEON and
452 // VFP pipelines on A8.
453 let D = VFPNeonA8Domain;
456 let Defs = [FPSCR_NZCV] in {
457 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
458 (outs), (ins DPR:$Dd),
459 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
460 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
461 let Inst{3-0} = 0b0000;
465 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
466 (outs), (ins SPR:$Sd),
467 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
468 [(arm_cmpfp0 SPR:$Sd)]> {
469 let Inst{3-0} = 0b0000;
472 // Some single precision VFP instructions may be executed on both NEON and
473 // VFP pipelines on A8.
474 let D = VFPNeonA8Domain;
477 // FIXME: Verify encoding after integrated assembler is working.
478 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
479 (outs), (ins DPR:$Dd),
480 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
481 [/* For disassembly only; pattern left blank */]> {
482 let Inst{3-0} = 0b0000;
486 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
487 (outs), (ins SPR:$Sd),
488 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
489 [/* For disassembly only; pattern left blank */]> {
490 let Inst{3-0} = 0b0000;
493 // Some single precision VFP instructions may be executed on both NEON and
494 // VFP pipelines on A8.
495 let D = VFPNeonA8Domain;
497 } // Defs = [FPSCR_NZCV]
499 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
500 (outs DPR:$Dd), (ins SPR:$Sm),
501 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
502 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
503 // Instruction operands.
507 // Encode instruction operands.
508 let Inst{3-0} = Sm{4-1};
510 let Inst{15-12} = Dd{3-0};
511 let Inst{22} = Dd{4};
513 let Predicates = [HasVFP2, HasDPVFP];
516 // Special case encoding: bits 11-8 is 0b1011.
517 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
518 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
519 [(set SPR:$Sd, (fround DPR:$Dm))]> {
520 // Instruction operands.
524 // Encode instruction operands.
525 let Inst{3-0} = Dm{3-0};
527 let Inst{15-12} = Sd{4-1};
528 let Inst{22} = Sd{0};
530 let Inst{27-23} = 0b11101;
531 let Inst{21-16} = 0b110111;
532 let Inst{11-8} = 0b1011;
533 let Inst{7-6} = 0b11;
536 let Predicates = [HasVFP2, HasDPVFP];
539 // Between half, single and double-precision. For disassembly only.
541 // FIXME: Verify encoding after integrated assembler is working.
542 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
543 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
544 [/* For disassembly only; pattern left blank */]>;
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
547 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
548 [/* For disassembly only; pattern left blank */]>;
550 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
551 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
552 [/* For disassembly only; pattern left blank */]>;
554 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
555 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
556 [/* For disassembly only; pattern left blank */]>;
558 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
559 (outs DPR:$Dd), (ins SPR:$Sm),
560 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
561 []>, Requires<[HasFPARMv8, HasDPVFP]> {
562 // Instruction operands.
565 // Encode instruction operands.
566 let Inst{3-0} = Sm{4-1};
570 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
571 (outs SPR:$Sd), (ins DPR:$Dm),
572 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
573 []>, Requires<[HasFPARMv8, HasDPVFP]> {
574 // Instruction operands.
578 // Encode instruction operands.
579 let Inst{3-0} = Dm{3-0};
581 let Inst{15-12} = Sd{4-1};
582 let Inst{22} = Sd{0};
585 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
586 (outs DPR:$Dd), (ins SPR:$Sm),
587 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
588 []>, Requires<[HasFPARMv8, HasDPVFP]> {
589 // Instruction operands.
592 // Encode instruction operands.
593 let Inst{3-0} = Sm{4-1};
597 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
598 (outs SPR:$Sd), (ins DPR:$Dm),
599 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
600 []>, Requires<[HasFPARMv8, HasDPVFP]> {
601 // Instruction operands.
605 // Encode instruction operands.
606 let Inst{15-12} = Sd{4-1};
607 let Inst{22} = Sd{0};
608 let Inst{3-0} = Dm{3-0};
612 def : Pat<(fp_to_f16 SPR:$a),
613 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
615 def : Pat<(fp_to_f16 (f64 DPR:$a)),
616 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
618 def : Pat<(f16_to_fp GPR:$a),
619 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
621 def : Pat<(f64 (f16_to_fp GPR:$a)),
622 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
624 def : Pat<(f64 (fextend (f16_to_fp GPR:$a))),
625 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
626 Requires<[HasFPARMv8, HasDPVFP]>;
628 def : Pat<(fp_to_f16 (fround (f64 DPR:$a))),
629 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
630 Requires<[HasFPARMv8, HasDPVFP]>;
632 multiclass vcvt_inst<string opc, bits<2> rm,
633 SDPatternOperator node = null_frag> {
634 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
635 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
636 (outs SPR:$Sd), (ins SPR:$Sm),
637 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
639 Requires<[HasFPARMv8]> {
640 let Inst{17-16} = rm;
643 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
644 (outs SPR:$Sd), (ins SPR:$Sm),
645 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
647 Requires<[HasFPARMv8]> {
648 let Inst{17-16} = rm;
651 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
652 (outs SPR:$Sd), (ins DPR:$Dm),
653 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
655 Requires<[HasFPARMv8, HasDPVFP]> {
658 let Inst{17-16} = rm;
660 // Encode instruction operands
661 let Inst{3-0} = Dm{3-0};
666 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
667 (outs SPR:$Sd), (ins DPR:$Dm),
668 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
670 Requires<[HasFPARMv8, HasDPVFP]> {
673 let Inst{17-16} = rm;
675 // Encode instruction operands
676 let Inst{3-0} = Dm{3-0};
682 let Predicates = [HasFPARMv8] in {
683 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
685 (!cast<Instruction>(NAME#"SS") SPR:$a),
687 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
689 (!cast<Instruction>(NAME#"US") SPR:$a),
692 let Predicates = [HasFPARMv8, HasDPVFP] in {
693 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))),
695 (!cast<Instruction>(NAME#"SD") DPR:$a),
697 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))),
699 (!cast<Instruction>(NAME#"UD") DPR:$a),
704 defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
705 defm VCVTN : vcvt_inst<"n", 0b01>;
706 defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
707 defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
709 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
710 (outs DPR:$Dd), (ins DPR:$Dm),
711 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
712 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
714 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
715 (outs SPR:$Sd), (ins SPR:$Sm),
716 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
717 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
718 // Some single precision VFP instructions may be executed on both NEON and
719 // VFP pipelines on A8.
720 let D = VFPNeonA8Domain;
723 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
724 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
725 (outs SPR:$Sd), (ins SPR:$Sm),
726 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
727 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
728 Requires<[HasFPARMv8]> {
732 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
733 (outs DPR:$Dd), (ins DPR:$Dm),
734 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
735 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
736 Requires<[HasFPARMv8, HasDPVFP]> {
741 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
742 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
743 Requires<[HasFPARMv8]>;
744 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
745 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
746 Requires<[HasFPARMv8,HasDPVFP]>;
749 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
750 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
751 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
753 multiclass vrint_inst_anpm<string opc, bits<2> rm,
754 SDPatternOperator node = null_frag> {
755 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
756 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
757 (outs SPR:$Sd), (ins SPR:$Sm),
758 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
759 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
760 Requires<[HasFPARMv8]> {
761 let Inst{17-16} = rm;
763 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
764 (outs DPR:$Dd), (ins DPR:$Dm),
765 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
766 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
767 Requires<[HasFPARMv8, HasDPVFP]> {
768 let Inst{17-16} = rm;
772 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
773 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
774 Requires<[HasFPARMv8]>;
775 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
776 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
777 Requires<[HasFPARMv8,HasDPVFP]>;
780 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
781 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
782 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
783 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
785 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
786 (outs DPR:$Dd), (ins DPR:$Dm),
787 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
788 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
790 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
791 (outs SPR:$Sd), (ins SPR:$Sm),
792 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
793 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
795 let hasSideEffects = 0 in {
796 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
797 (outs DPR:$Dd), (ins DPR:$Dm),
798 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
800 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
801 (outs SPR:$Sd), (ins SPR:$Sm),
802 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
805 //===----------------------------------------------------------------------===//
806 // FP <-> GPR Copies. Int <-> FP Conversions.
809 def VMOVRS : AVConv2I<0b11100001, 0b1010,
810 (outs GPR:$Rt), (ins SPR:$Sn),
811 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
812 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
813 // Instruction operands.
817 // Encode instruction operands.
818 let Inst{19-16} = Sn{4-1};
820 let Inst{15-12} = Rt;
822 let Inst{6-5} = 0b00;
823 let Inst{3-0} = 0b0000;
825 // Some single precision VFP instructions may be executed on both NEON and VFP
827 let D = VFPNeonDomain;
830 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
831 def VMOVSR : AVConv4I<0b11100000, 0b1010,
832 (outs SPR:$Sn), (ins GPR:$Rt),
833 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
834 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
835 Requires<[HasVFP2, UseVMOVSR]> {
836 // Instruction operands.
840 // Encode instruction operands.
841 let Inst{19-16} = Sn{4-1};
843 let Inst{15-12} = Rt;
845 let Inst{6-5} = 0b00;
846 let Inst{3-0} = 0b0000;
848 // Some single precision VFP instructions may be executed on both NEON and VFP
850 let D = VFPNeonDomain;
853 let hasSideEffects = 0 in {
854 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
855 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
856 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
857 [/* FIXME: Can't write pattern for multiple result instr*/]> {
858 // Instruction operands.
863 // Encode instruction operands.
864 let Inst{3-0} = Dm{3-0};
866 let Inst{15-12} = Rt;
867 let Inst{19-16} = Rt2;
869 let Inst{7-6} = 0b00;
871 // Some single precision VFP instructions may be executed on both NEON and VFP
873 let D = VFPNeonDomain;
875 // This instruction is equivalent to
876 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
877 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
878 let isExtractSubreg = 1;
881 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
882 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
883 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
884 [/* For disassembly only; pattern left blank */]> {
889 // Encode instruction operands.
890 let Inst{3-0} = src1{4-1};
891 let Inst{5} = src1{0};
892 let Inst{15-12} = Rt;
893 let Inst{19-16} = Rt2;
895 let Inst{7-6} = 0b00;
897 // Some single precision VFP instructions may be executed on both NEON and VFP
899 let D = VFPNeonDomain;
900 let DecoderMethod = "DecodeVMOVRRS";
907 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
908 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
909 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
910 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
911 // Instruction operands.
916 // Encode instruction operands.
917 let Inst{3-0} = Dm{3-0};
919 let Inst{15-12} = Rt;
920 let Inst{19-16} = Rt2;
922 let Inst{7-6} = 0b00;
924 // Some single precision VFP instructions may be executed on both NEON and VFP
926 let D = VFPNeonDomain;
928 // This instruction is equivalent to
929 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
930 let isRegSequence = 1;
933 let hasSideEffects = 0 in
934 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
935 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
936 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
937 [/* For disassembly only; pattern left blank */]> {
938 // Instruction operands.
943 // Encode instruction operands.
944 let Inst{3-0} = dst1{4-1};
945 let Inst{5} = dst1{0};
946 let Inst{15-12} = src1;
947 let Inst{19-16} = src2;
949 let Inst{7-6} = 0b00;
951 // Some single precision VFP instructions may be executed on both NEON and VFP
953 let D = VFPNeonDomain;
955 let DecoderMethod = "DecodeVMOVSRR";
961 // FMRX: SPR system reg -> GPR
963 // FMXR: GPR -> VFP system reg
968 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
969 bits<4> opcod4, dag oops, dag iops,
970 InstrItinClass itin, string opc, string asm,
972 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
974 // Instruction operands.
978 // Encode instruction operands.
979 let Inst{3-0} = Sm{4-1};
981 let Inst{15-12} = Dd{3-0};
982 let Inst{22} = Dd{4};
984 let Predicates = [HasVFP2, HasDPVFP];
987 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
988 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
989 string opc, string asm, list<dag> pattern>
990 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
992 // Instruction operands.
996 // Encode instruction operands.
997 let Inst{3-0} = Sm{4-1};
999 let Inst{15-12} = Sd{4-1};
1000 let Inst{22} = Sd{0};
1003 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1004 (outs DPR:$Dd), (ins SPR:$Sm),
1005 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
1007 let Inst{7} = 1; // s32
1010 let Predicates=[HasVFP2, HasDPVFP] in {
1011 def : VFPPat<(f64 (sint_to_fp GPR:$a)),
1012 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1014 def : VFPPat<(f64 (sint_to_fp (i32 (load addrmode5:$a)))),
1015 (VSITOD (VLDRS addrmode5:$a))>;
1018 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1019 (outs SPR:$Sd),(ins SPR:$Sm),
1020 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1022 let Inst{7} = 1; // s32
1024 // Some single precision VFP instructions may be executed on both NEON and
1025 // VFP pipelines on A8.
1026 let D = VFPNeonA8Domain;
1029 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
1030 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1032 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (load addrmode5:$a)))),
1033 (VSITOS (VLDRS addrmode5:$a))>;
1035 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1036 (outs DPR:$Dd), (ins SPR:$Sm),
1037 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
1039 let Inst{7} = 0; // u32
1042 let Predicates=[HasVFP2, HasDPVFP] in {
1043 def : VFPPat<(f64 (uint_to_fp GPR:$a)),
1044 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1046 def : VFPPat<(f64 (uint_to_fp (i32 (load addrmode5:$a)))),
1047 (VUITOD (VLDRS addrmode5:$a))>;
1050 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1051 (outs SPR:$Sd), (ins SPR:$Sm),
1052 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1054 let Inst{7} = 0; // u32
1056 // Some single precision VFP instructions may be executed on both NEON and
1057 // VFP pipelines on A8.
1058 let D = VFPNeonA8Domain;
1061 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
1062 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1064 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (load addrmode5:$a)))),
1065 (VUITOS (VLDRS addrmode5:$a))>;
1069 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1070 bits<4> opcod4, dag oops, dag iops,
1071 InstrItinClass itin, string opc, string asm,
1073 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1075 // Instruction operands.
1079 // Encode instruction operands.
1080 let Inst{3-0} = Dm{3-0};
1081 let Inst{5} = Dm{4};
1082 let Inst{15-12} = Sd{4-1};
1083 let Inst{22} = Sd{0};
1085 let Predicates = [HasVFP2, HasDPVFP];
1088 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1089 bits<4> opcod4, dag oops, dag iops,
1090 InstrItinClass itin, string opc, string asm,
1092 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1094 // Instruction operands.
1098 // Encode instruction operands.
1099 let Inst{3-0} = Sm{4-1};
1100 let Inst{5} = Sm{0};
1101 let Inst{15-12} = Sd{4-1};
1102 let Inst{22} = Sd{0};
1105 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1106 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1107 (outs SPR:$Sd), (ins DPR:$Dm),
1108 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1110 let Inst{7} = 1; // Z bit
1113 let Predicates=[HasVFP2, HasDPVFP] in {
1114 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
1115 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
1117 def : VFPPat<(store (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
1118 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
1121 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1122 (outs SPR:$Sd), (ins SPR:$Sm),
1123 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1125 let Inst{7} = 1; // Z bit
1127 // Some single precision VFP instructions may be executed on both NEON and
1128 // VFP pipelines on A8.
1129 let D = VFPNeonA8Domain;
1132 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1133 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1135 def : VFPNoNEONPat<(store (i32 (fp_to_sint (f32 SPR:$a))), addrmode5:$ptr),
1136 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1138 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1139 (outs SPR:$Sd), (ins DPR:$Dm),
1140 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1142 let Inst{7} = 1; // Z bit
1145 let Predicates=[HasVFP2, HasDPVFP] in {
1146 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
1147 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
1149 def : VFPPat<(store (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
1150 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
1153 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1154 (outs SPR:$Sd), (ins SPR:$Sm),
1155 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1157 let Inst{7} = 1; // Z bit
1159 // Some single precision VFP instructions may be executed on both NEON and
1160 // VFP pipelines on A8.
1161 let D = VFPNeonA8Domain;
1164 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1165 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1167 def : VFPNoNEONPat<(store (i32 (fp_to_uint (f32 SPR:$a))), addrmode5:$ptr),
1168 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1170 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1171 let Uses = [FPSCR] in {
1172 // FIXME: Verify encoding after integrated assembler is working.
1173 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1174 (outs SPR:$Sd), (ins DPR:$Dm),
1175 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1176 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1177 let Inst{7} = 0; // Z bit
1180 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1181 (outs SPR:$Sd), (ins SPR:$Sm),
1182 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1183 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1184 let Inst{7} = 0; // Z bit
1187 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1188 (outs SPR:$Sd), (ins DPR:$Dm),
1189 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1190 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1191 let Inst{7} = 0; // Z bit
1194 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1195 (outs SPR:$Sd), (ins SPR:$Sm),
1196 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1197 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1198 let Inst{7} = 0; // Z bit
1202 // Convert between floating-point and fixed-point
1203 // Data type for fixed-point naming convention:
1204 // S16 (U=0, sx=0) -> SH
1205 // U16 (U=1, sx=0) -> UH
1206 // S32 (U=0, sx=1) -> SL
1207 // U32 (U=1, sx=1) -> UL
1209 let Constraints = "$a = $dst" in {
1211 // FP to Fixed-Point:
1213 // Single Precision register
1214 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1215 bit op5, dag oops, dag iops, InstrItinClass itin,
1216 string opc, string asm, list<dag> pattern>
1217 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1218 Sched<[WriteCvtFP]> {
1220 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1221 let Inst{22} = dst{0};
1222 let Inst{15-12} = dst{4-1};
1225 // Double Precision register
1226 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1227 bit op5, dag oops, dag iops, InstrItinClass itin,
1228 string opc, string asm, list<dag> pattern>
1229 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1230 Sched<[WriteCvtFP]> {
1232 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1233 let Inst{22} = dst{4};
1234 let Inst{15-12} = dst{3-0};
1236 let Predicates = [HasVFP2, HasDPVFP];
1239 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1240 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1241 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1242 // Some single precision VFP instructions may be executed on both NEON and
1243 // VFP pipelines on A8.
1244 let D = VFPNeonA8Domain;
1247 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1248 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1249 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1250 // Some single precision VFP instructions may be executed on both NEON and
1251 // VFP pipelines on A8.
1252 let D = VFPNeonA8Domain;
1255 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1256 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1257 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1258 // Some single precision VFP instructions may be executed on both NEON and
1259 // VFP pipelines on A8.
1260 let D = VFPNeonA8Domain;
1263 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1264 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1265 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1266 // Some single precision VFP instructions may be executed on both NEON and
1267 // VFP pipelines on A8.
1268 let D = VFPNeonA8Domain;
1271 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1272 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1273 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1275 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1276 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1277 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1279 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1280 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1281 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1283 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1284 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1285 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1287 // Fixed-Point to FP:
1289 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1290 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1291 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1292 // Some single precision VFP instructions may be executed on both NEON and
1293 // VFP pipelines on A8.
1294 let D = VFPNeonA8Domain;
1297 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1298 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1299 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1300 // Some single precision VFP instructions may be executed on both NEON and
1301 // VFP pipelines on A8.
1302 let D = VFPNeonA8Domain;
1305 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1306 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1307 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1308 // Some single precision VFP instructions may be executed on both NEON and
1309 // VFP pipelines on A8.
1310 let D = VFPNeonA8Domain;
1313 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1314 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1315 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1316 // Some single precision VFP instructions may be executed on both NEON and
1317 // VFP pipelines on A8.
1318 let D = VFPNeonA8Domain;
1321 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1322 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1323 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1325 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1326 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1327 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1329 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1330 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1331 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1333 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1334 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1335 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1337 } // End of 'let Constraints = "$a = $dst" in'
1339 //===----------------------------------------------------------------------===//
1340 // FP Multiply-Accumulate Operations.
1343 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1344 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1345 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1346 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1347 (f64 DPR:$Ddin)))]>,
1348 RegConstraint<"$Ddin = $Dd">,
1349 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1351 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1352 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1353 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1354 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1356 RegConstraint<"$Sdin = $Sd">,
1357 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1358 // Some single precision VFP instructions may be executed on both NEON and
1359 // VFP pipelines on A8.
1360 let D = VFPNeonA8Domain;
1363 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1364 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1365 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1366 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1367 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1368 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1370 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1371 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1372 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1373 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1374 (f64 DPR:$Ddin)))]>,
1375 RegConstraint<"$Ddin = $Dd">,
1376 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1378 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1379 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1380 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1381 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1383 RegConstraint<"$Sdin = $Sd">,
1384 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1385 // Some single precision VFP instructions may be executed on both NEON and
1386 // VFP pipelines on A8.
1387 let D = VFPNeonA8Domain;
1390 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1391 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1392 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1393 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1394 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1395 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1397 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1398 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1399 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1400 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1401 (f64 DPR:$Ddin)))]>,
1402 RegConstraint<"$Ddin = $Dd">,
1403 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1405 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1406 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1407 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1408 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1410 RegConstraint<"$Sdin = $Sd">,
1411 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1412 // Some single precision VFP instructions may be executed on both NEON and
1413 // VFP pipelines on A8.
1414 let D = VFPNeonA8Domain;
1417 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1418 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1419 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1420 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1421 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1422 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1424 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1425 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1426 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1427 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1428 (f64 DPR:$Ddin)))]>,
1429 RegConstraint<"$Ddin = $Dd">,
1430 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1432 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1433 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1434 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1435 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1436 RegConstraint<"$Sdin = $Sd">,
1437 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1438 // Some single precision VFP instructions may be executed on both NEON and
1439 // VFP pipelines on A8.
1440 let D = VFPNeonA8Domain;
1443 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1444 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1445 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1446 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1447 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1448 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1450 //===----------------------------------------------------------------------===//
1451 // Fused FP Multiply-Accumulate Operations.
1453 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1454 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1455 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1456 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1457 (f64 DPR:$Ddin)))]>,
1458 RegConstraint<"$Ddin = $Dd">,
1459 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1461 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1462 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1463 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1464 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1466 RegConstraint<"$Sdin = $Sd">,
1467 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1468 // Some single precision VFP instructions may be executed on both NEON and
1472 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1473 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1474 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1475 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1476 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1477 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1479 // Match @llvm.fma.* intrinsics
1480 // (fma x, y, z) -> (vfms z, x, y)
1481 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1482 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1483 Requires<[HasVFP4,HasDPVFP]>;
1484 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1485 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1486 Requires<[HasVFP4]>;
1488 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1489 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1490 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1491 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1492 (f64 DPR:$Ddin)))]>,
1493 RegConstraint<"$Ddin = $Dd">,
1494 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1496 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1497 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1498 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1499 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1501 RegConstraint<"$Sdin = $Sd">,
1502 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1503 // Some single precision VFP instructions may be executed on both NEON and
1507 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1508 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1509 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1510 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1511 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1512 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1514 // Match @llvm.fma.* intrinsics
1515 // (fma (fneg x), y, z) -> (vfms z, x, y)
1516 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1517 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1518 Requires<[HasVFP4,HasDPVFP]>;
1519 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1520 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1521 Requires<[HasVFP4]>;
1522 // (fma x, (fneg y), z) -> (vfms z, x, y)
1523 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1524 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1525 Requires<[HasVFP4,HasDPVFP]>;
1526 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1527 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1528 Requires<[HasVFP4]>;
1530 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1531 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1532 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1533 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1534 (f64 DPR:$Ddin)))]>,
1535 RegConstraint<"$Ddin = $Dd">,
1536 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1538 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1539 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1540 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1541 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1543 RegConstraint<"$Sdin = $Sd">,
1544 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1545 // Some single precision VFP instructions may be executed on both NEON and
1549 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1550 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1551 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1552 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1553 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1554 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1556 // Match @llvm.fma.* intrinsics
1557 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1558 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1559 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1560 Requires<[HasVFP4,HasDPVFP]>;
1561 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1562 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1563 Requires<[HasVFP4]>;
1564 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1565 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1566 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1567 Requires<[HasVFP4,HasDPVFP]>;
1568 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1569 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1570 Requires<[HasVFP4]>;
1572 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1573 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1574 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1575 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1576 (f64 DPR:$Ddin)))]>,
1577 RegConstraint<"$Ddin = $Dd">,
1578 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1580 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1581 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1582 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1583 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1584 RegConstraint<"$Sdin = $Sd">,
1585 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1586 // Some single precision VFP instructions may be executed on both NEON and
1590 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1591 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1592 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1593 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1594 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1595 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1597 // Match @llvm.fma.* intrinsics
1599 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1600 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1601 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1602 Requires<[HasVFP4,HasDPVFP]>;
1603 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1604 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1605 Requires<[HasVFP4]>;
1606 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1607 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1608 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1609 Requires<[HasVFP4,HasDPVFP]>;
1610 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1611 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1612 Requires<[HasVFP4]>;
1613 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1614 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1615 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1616 Requires<[HasVFP4,HasDPVFP]>;
1617 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1618 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1619 Requires<[HasVFP4]>;
1621 //===----------------------------------------------------------------------===//
1622 // FP Conditional moves.
1625 let hasSideEffects = 0 in {
1626 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1628 [(set (f64 DPR:$Dd),
1629 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1630 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1632 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1634 [(set (f32 SPR:$Sd),
1635 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1636 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1639 //===----------------------------------------------------------------------===//
1640 // Move from VFP System Register to ARM core register.
1643 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1645 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1647 // Instruction operand.
1650 let Inst{27-20} = 0b11101111;
1651 let Inst{19-16} = opc19_16;
1652 let Inst{15-12} = Rt;
1653 let Inst{11-8} = 0b1010;
1655 let Inst{6-5} = 0b00;
1657 let Inst{3-0} = 0b0000;
1660 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1662 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1663 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1664 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1666 // Application level FPSCR -> GPR
1667 let hasSideEffects = 1, Uses = [FPSCR] in
1668 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1669 "vmrs", "\t$Rt, fpscr",
1670 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1672 // System level FPEXC, FPSID -> GPR
1673 let Uses = [FPSCR] in {
1674 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1675 "vmrs", "\t$Rt, fpexc", []>;
1676 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1677 "vmrs", "\t$Rt, fpsid", []>;
1678 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1679 "vmrs", "\t$Rt, mvfr0", []>;
1680 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1681 "vmrs", "\t$Rt, mvfr1", []>;
1682 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1683 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1684 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1685 "vmrs", "\t$Rt, fpinst", []>;
1686 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1687 "vmrs", "\t$Rt, fpinst2", []>;
1690 //===----------------------------------------------------------------------===//
1691 // Move from ARM core register to VFP System Register.
1694 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1696 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1698 // Instruction operand.
1701 // Encode instruction operand.
1702 let Inst{15-12} = src;
1704 let Inst{27-20} = 0b11101110;
1705 let Inst{19-16} = opc19_16;
1706 let Inst{11-8} = 0b1010;
1711 let Defs = [FPSCR] in {
1712 // Application level GPR -> FPSCR
1713 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1714 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1715 // System level GPR -> FPEXC
1716 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1717 "vmsr", "\tfpexc, $src", []>;
1718 // System level GPR -> FPSID
1719 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1720 "vmsr", "\tfpsid, $src", []>;
1722 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1723 "vmsr", "\tfpinst, $src", []>;
1724 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1725 "vmsr", "\tfpinst2, $src", []>;
1728 //===----------------------------------------------------------------------===//
1732 // Materialize FP immediates. VFP3 only.
1733 let isReMaterializable = 1 in {
1734 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1735 VFPMiscFrm, IIC_fpUNA64,
1736 "vmov", ".f64\t$Dd, $imm",
1737 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1738 Requires<[HasVFP3,HasDPVFP]> {
1742 let Inst{27-23} = 0b11101;
1743 let Inst{22} = Dd{4};
1744 let Inst{21-20} = 0b11;
1745 let Inst{19-16} = imm{7-4};
1746 let Inst{15-12} = Dd{3-0};
1747 let Inst{11-9} = 0b101;
1748 let Inst{8} = 1; // Double precision.
1749 let Inst{7-4} = 0b0000;
1750 let Inst{3-0} = imm{3-0};
1753 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1754 VFPMiscFrm, IIC_fpUNA32,
1755 "vmov", ".f32\t$Sd, $imm",
1756 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1760 let Inst{27-23} = 0b11101;
1761 let Inst{22} = Sd{0};
1762 let Inst{21-20} = 0b11;
1763 let Inst{19-16} = imm{7-4};
1764 let Inst{15-12} = Sd{4-1};
1765 let Inst{11-9} = 0b101;
1766 let Inst{8} = 0; // Single precision.
1767 let Inst{7-4} = 0b0000;
1768 let Inst{3-0} = imm{3-0};
1772 //===----------------------------------------------------------------------===//
1773 // Assembler aliases.
1775 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1776 // support them all, but supporting at least some of the basics is
1777 // good to be friendly.
1778 def : VFP2MnemonicAlias<"flds", "vldr">;
1779 def : VFP2MnemonicAlias<"fldd", "vldr">;
1780 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1781 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1782 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1783 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1784 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1785 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1786 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1787 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1788 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1789 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1790 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1791 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1792 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1793 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1794 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1795 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1796 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1797 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1798 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1799 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1800 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1801 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1802 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1803 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1804 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1805 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1806 def : VFP2MnemonicAlias<"fsts", "vstr">;
1807 def : VFP2MnemonicAlias<"fstd", "vstr">;
1808 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1809 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1810 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1811 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1812 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1813 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1814 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1815 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1816 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1817 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1819 // Be friendly and accept the old form of zero-compare
1820 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1821 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1824 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1825 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1826 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1827 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1828 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1829 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1830 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1831 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1832 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1834 // No need for the size suffix on VSQRT. It's implied by the register classes.
1835 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1836 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1838 // VLDR/VSTR accept an optional type suffix.
1839 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1840 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1841 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1842 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1843 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1844 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1845 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1846 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1848 // VMOV can accept optional 32-bit or less data type suffix suffix.
1849 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1850 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1851 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1852 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1853 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1854 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1855 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1856 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1857 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1858 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1859 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1860 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1862 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1863 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1864 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1865 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1867 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1869 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1870 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1872 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1873 // These aliases provide added functionality over vmov.f instructions by
1874 // allowing users to write assembly containing encoded floating point constants
1875 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1876 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1877 // accepted directly by vmovf).
1878 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1879 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1880 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1881 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;