1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
51 DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52 cl::desc("Enable / disable ARM integer abs transform"),
55 //===--------------------------------------------------------------------===//
56 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
57 /// instructions for SelectionDAG operations.
62 AM2_BASE, // Simple AM2 (+-imm12)
63 AM2_SHOP // Shifter-op AM2
66 class ARMDAGToDAGISel : public SelectionDAGISel {
67 ARMBaseTargetMachine &TM;
68 const ARMBaseInstrInfo *TII;
70 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71 /// make the right decision when generating code for different targets.
72 const ARMSubtarget *Subtarget;
75 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76 CodeGenOpt::Level OptLevel)
77 : SelectionDAGISel(tm, OptLevel), TM(tm),
78 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
82 virtual const char *getPassName() const {
83 return "ARM Instruction Selection";
86 /// getI32Imm - Return a target constant of type i32 with the specified
88 inline SDValue getI32Imm(unsigned Imm) {
89 return CurDAG->getTargetConstant(Imm, MVT::i32);
92 SDNode *Select(SDNode *N);
95 bool hasNoVMLxHazardUse(SDNode *N) const;
96 bool isShifterOpProfitable(const SDValue &Shift,
97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98 bool SelectRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C,
100 bool CheckProfitability = true);
101 bool SelectImmShifterOperand(SDValue N, SDValue &A,
102 SDValue &B, bool CheckProfitability = true);
103 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104 SDValue &B, SDValue &C) {
105 // Don't apply the profitability check
106 return SelectRegShifterOperand(N, A, B, C, false);
108 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
110 // Don't apply the profitability check
111 return SelectImmShifterOperand(N, A, B, false);
114 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
117 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118 SDValue &Offset, SDValue &Opc);
119 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
124 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
126 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
129 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
131 SelectAddrMode2Worker(N, Base, Offset, Opc);
132 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133 // This always matches one way or another.
137 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138 SDValue &Offset, SDValue &Opc);
139 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140 SDValue &Offset, SDValue &Opc);
141 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142 SDValue &Offset, SDValue &Opc);
143 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144 bool SelectAddrMode3(SDValue N, SDValue &Base,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147 SDValue &Offset, SDValue &Opc);
148 bool SelectAddrMode5(SDValue N, SDValue &Base,
150 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
153 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
155 // Thumb Addressing Modes:
156 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
159 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
164 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
166 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
168 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
170 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
172 // Thumb 2 Addressing Modes:
173 bool SelectT2ShifterOperandReg(SDValue N,
174 SDValue &BaseReg, SDValue &Opc);
175 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
178 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
180 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181 SDValue &OffReg, SDValue &ShImm);
183 inline bool is_so_imm(unsigned Imm) const {
184 return ARM_AM::getSOImmVal(Imm) != -1;
187 inline bool is_so_imm_not(unsigned Imm) const {
188 return ARM_AM::getSOImmVal(~Imm) != -1;
191 inline bool is_t2_so_imm(unsigned Imm) const {
192 return ARM_AM::getT2SOImmVal(Imm) != -1;
195 inline bool is_t2_so_imm_not(unsigned Imm) const {
196 return ARM_AM::getT2SOImmVal(~Imm) != -1;
199 // Include the pieces autogenerated from the target description.
200 #include "ARMGenDAGISel.inc"
203 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
205 SDNode *SelectARMIndexedLoad(SDNode *N);
206 SDNode *SelectT2IndexedLoad(SDNode *N);
208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
210 /// loads of D registers and even subregs and odd subregs of Q registers.
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
214 unsigned *QOpcodes0, unsigned *QOpcodes1);
216 /// SelectVST - Select NEON store intrinsics. NumVecs should
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
218 /// stores of D registers and even subregs and odd subregs of Q registers.
219 /// For NumVecs <= 2, QOpcodes1 is not used.
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
222 unsigned *QOpcodes0, unsigned *QOpcodes1);
224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
226 /// load/store of D registers and Q registers.
227 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228 bool isUpdating, unsigned NumVecs,
229 unsigned *DOpcodes, unsigned *QOpcodes);
231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
233 /// for loading D registers. (Q registers are not supported.)
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
237 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
238 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
239 /// generated to force the table registers to be consecutive.
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
242 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
245 /// SelectCMOVOp - Select CMOV instructions for ARM.
246 SDNode *SelectCMOVOp(SDNode *N);
247 SDNode *SelectConditionalOp(SDNode *N);
248 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
249 ARMCC::CondCodes CCVal, SDValue CCR,
251 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
252 ARMCC::CondCodes CCVal, SDValue CCR,
254 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
255 ARMCC::CondCodes CCVal, SDValue CCR,
257 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
258 ARMCC::CondCodes CCVal, SDValue CCR,
261 // Select special operations if node forms integer ABS pattern
262 SDNode *SelectABSOp(SDNode *N);
264 SDNode *SelectConcatVector(SDNode *N);
266 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
268 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
269 /// inline asm expressions.
270 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
272 std::vector<SDValue> &OutOps);
274 // Form pairs of consecutive S, D, or Q registers.
275 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
276 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
277 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
279 // Form sequences of 4 consecutive S, D, or Q registers.
280 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
284 // Get the alignment operand for a NEON VLD or VST instruction.
285 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
289 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
290 /// operand. If so Imm will receive the 32-bit value.
291 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
292 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
293 Imm = cast<ConstantSDNode>(N)->getZExtValue();
299 // isInt32Immediate - This method tests to see if a constant operand.
300 // If so Imm will receive the 32 bit value.
301 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
302 return isInt32Immediate(N.getNode(), Imm);
305 // isOpcWithIntImmediate - This method tests to see if the node is a specific
306 // opcode and that it has a immediate integer right operand.
307 // If so Imm will receive the 32 bit value.
308 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
309 return N->getOpcode() == Opc &&
310 isInt32Immediate(N->getOperand(1).getNode(), Imm);
313 /// \brief Check whether a particular node is a constant value representable as
314 /// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
316 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
317 static bool isScaledConstantInRange(SDValue Node, int Scale,
318 int RangeMin, int RangeMax,
319 int &ScaledConstant) {
320 assert(Scale > 0 && "Invalid scale!");
322 // Check that this is a constant.
323 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
327 ScaledConstant = (int) C->getZExtValue();
328 if ((ScaledConstant % Scale) != 0)
331 ScaledConstant /= Scale;
332 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
335 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
336 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
337 /// least on current ARM implementations) which should be avoidded.
338 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
339 if (OptLevel == CodeGenOpt::None)
342 if (!CheckVMLxHazard)
345 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
351 SDNode *Use = *N->use_begin();
352 if (Use->getOpcode() == ISD::CopyToReg)
354 if (Use->isMachineOpcode()) {
355 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
358 unsigned Opcode = MCID.getOpcode();
359 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
361 // vmlx feeding into another vmlx. We actually want to unfold
362 // the use later in the MLxExpansion pass. e.g.
364 // vmla (stall 8 cycles)
369 // This adds up to about 18 - 19 cycles.
372 // vmul (stall 4 cycles)
373 // vadd adds up to about 14 cycles.
374 return TII->isFpMLxInstruction(Opcode);
380 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
381 ARM_AM::ShiftOpc ShOpcVal,
383 if (!Subtarget->isCortexA9())
385 if (Shift.hasOneUse())
388 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
391 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
394 bool CheckProfitability) {
395 if (DisableShifterOp)
398 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
400 // Don't match base register only case. That is matched to a separate
401 // lower complexity pattern with explicit register operand.
402 if (ShOpcVal == ARM_AM::no_shift) return false;
404 BaseReg = N.getOperand(0);
405 unsigned ShImmVal = 0;
406 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
407 if (!RHS) return false;
408 ShImmVal = RHS->getZExtValue() & 31;
409 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
414 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
418 bool CheckProfitability) {
419 if (DisableShifterOp)
422 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
424 // Don't match base register only case. That is matched to a separate
425 // lower complexity pattern with explicit register operand.
426 if (ShOpcVal == ARM_AM::no_shift) return false;
428 BaseReg = N.getOperand(0);
429 unsigned ShImmVal = 0;
430 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
431 if (RHS) return false;
433 ShReg = N.getOperand(1);
434 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
436 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
442 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
445 // Match simple R + imm12 operands.
448 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
449 !CurDAG->isBaseWithConstantOffset(N)) {
450 if (N.getOpcode() == ISD::FrameIndex) {
451 // Match frame index.
452 int FI = cast<FrameIndexSDNode>(N)->getIndex();
453 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
454 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
458 if (N.getOpcode() == ARMISD::Wrapper &&
459 !(Subtarget->useMovt() &&
460 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
461 Base = N.getOperand(0);
464 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
468 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
469 int RHSC = (int)RHS->getZExtValue();
470 if (N.getOpcode() == ISD::SUB)
473 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
474 Base = N.getOperand(0);
475 if (Base.getOpcode() == ISD::FrameIndex) {
476 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
477 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
479 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
486 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
492 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
494 if (N.getOpcode() == ISD::MUL &&
495 (!Subtarget->isCortexA9() || N.hasOneUse())) {
496 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
497 // X * [3,5,9] -> X + X * [2,4,8] etc.
498 int RHSC = (int)RHS->getZExtValue();
501 ARM_AM::AddrOpc AddSub = ARM_AM::add;
503 AddSub = ARM_AM::sub;
506 if (isPowerOf2_32(RHSC)) {
507 unsigned ShAmt = Log2_32(RHSC);
508 Base = Offset = N.getOperand(0);
509 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
518 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
519 // ISD::OR that is equivalent to an ISD::ADD.
520 !CurDAG->isBaseWithConstantOffset(N))
523 // Leave simple R +/- imm12 operands for LDRi12
524 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
526 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
527 -0x1000+1, 0x1000, RHSC)) // 12 bits.
531 // Otherwise this is R +/- [possibly shifted] R.
532 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
533 ARM_AM::ShiftOpc ShOpcVal =
534 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
537 Base = N.getOperand(0);
538 Offset = N.getOperand(1);
540 if (ShOpcVal != ARM_AM::no_shift) {
541 // Check to see if the RHS of the shift is a constant, if not, we can't fold
543 if (ConstantSDNode *Sh =
544 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
545 ShAmt = Sh->getZExtValue();
546 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
547 Offset = N.getOperand(1).getOperand(0);
550 ShOpcVal = ARM_AM::no_shift;
553 ShOpcVal = ARM_AM::no_shift;
557 // Try matching (R shl C) + (R).
558 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
559 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
560 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
561 if (ShOpcVal != ARM_AM::no_shift) {
562 // Check to see if the RHS of the shift is a constant, if not, we can't
564 if (ConstantSDNode *Sh =
565 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
566 ShAmt = Sh->getZExtValue();
567 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
568 Offset = N.getOperand(0).getOperand(0);
569 Base = N.getOperand(1);
572 ShOpcVal = ARM_AM::no_shift;
575 ShOpcVal = ARM_AM::no_shift;
580 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
590 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
594 if (N.getOpcode() == ISD::MUL &&
595 (!Subtarget->isCortexA9() || N.hasOneUse())) {
596 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
597 // X * [3,5,9] -> X + X * [2,4,8] etc.
598 int RHSC = (int)RHS->getZExtValue();
601 ARM_AM::AddrOpc AddSub = ARM_AM::add;
603 AddSub = ARM_AM::sub;
606 if (isPowerOf2_32(RHSC)) {
607 unsigned ShAmt = Log2_32(RHSC);
608 Base = Offset = N.getOperand(0);
609 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
618 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
619 // ISD::OR that is equivalent to an ADD.
620 !CurDAG->isBaseWithConstantOffset(N)) {
622 if (N.getOpcode() == ISD::FrameIndex) {
623 int FI = cast<FrameIndexSDNode>(N)->getIndex();
624 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
625 } else if (N.getOpcode() == ARMISD::Wrapper &&
626 !(Subtarget->useMovt() &&
627 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
628 Base = N.getOperand(0);
630 Offset = CurDAG->getRegister(0, MVT::i32);
631 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
637 // Match simple R +/- imm12 operands.
638 if (N.getOpcode() != ISD::SUB) {
640 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
641 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
642 Base = N.getOperand(0);
643 if (Base.getOpcode() == ISD::FrameIndex) {
644 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
645 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
647 Offset = CurDAG->getRegister(0, MVT::i32);
649 ARM_AM::AddrOpc AddSub = ARM_AM::add;
651 AddSub = ARM_AM::sub;
654 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
661 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
662 // Compute R +/- (R << N) and reuse it.
664 Offset = CurDAG->getRegister(0, MVT::i32);
665 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
671 // Otherwise this is R +/- [possibly shifted] R.
672 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
673 ARM_AM::ShiftOpc ShOpcVal =
674 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
677 Base = N.getOperand(0);
678 Offset = N.getOperand(1);
680 if (ShOpcVal != ARM_AM::no_shift) {
681 // Check to see if the RHS of the shift is a constant, if not, we can't fold
683 if (ConstantSDNode *Sh =
684 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
685 ShAmt = Sh->getZExtValue();
686 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
687 Offset = N.getOperand(1).getOperand(0);
690 ShOpcVal = ARM_AM::no_shift;
693 ShOpcVal = ARM_AM::no_shift;
697 // Try matching (R shl C) + (R).
698 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
699 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
700 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
701 if (ShOpcVal != ARM_AM::no_shift) {
702 // Check to see if the RHS of the shift is a constant, if not, we can't
704 if (ConstantSDNode *Sh =
705 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
706 ShAmt = Sh->getZExtValue();
707 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
708 Offset = N.getOperand(0).getOperand(0);
709 Base = N.getOperand(1);
712 ShOpcVal = ARM_AM::no_shift;
715 ShOpcVal = ARM_AM::no_shift;
720 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
725 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
726 SDValue &Offset, SDValue &Opc) {
727 unsigned Opcode = Op->getOpcode();
728 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
729 ? cast<LoadSDNode>(Op)->getAddressingMode()
730 : cast<StoreSDNode>(Op)->getAddressingMode();
731 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
732 ? ARM_AM::add : ARM_AM::sub;
734 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
738 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
740 if (ShOpcVal != ARM_AM::no_shift) {
741 // Check to see if the RHS of the shift is a constant, if not, we can't fold
743 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
744 ShAmt = Sh->getZExtValue();
745 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
746 Offset = N.getOperand(0);
749 ShOpcVal = ARM_AM::no_shift;
752 ShOpcVal = ARM_AM::no_shift;
756 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
761 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
762 SDValue &Offset, SDValue &Opc) {
763 unsigned Opcode = Op->getOpcode();
764 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
765 ? cast<LoadSDNode>(Op)->getAddressingMode()
766 : cast<StoreSDNode>(Op)->getAddressingMode();
767 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
768 ? ARM_AM::add : ARM_AM::sub;
770 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
771 if (AddSub == ARM_AM::sub) Val *= -1;
772 Offset = CurDAG->getRegister(0, MVT::i32);
773 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
781 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
782 SDValue &Offset, SDValue &Opc) {
783 unsigned Opcode = Op->getOpcode();
784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
785 ? cast<LoadSDNode>(Op)->getAddressingMode()
786 : cast<StoreSDNode>(Op)->getAddressingMode();
787 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
788 ? ARM_AM::add : ARM_AM::sub;
790 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
791 Offset = CurDAG->getRegister(0, MVT::i32);
792 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
801 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
806 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
807 SDValue &Base, SDValue &Offset,
809 if (N.getOpcode() == ISD::SUB) {
810 // X - C is canonicalize to X + -C, no need to handle it here.
811 Base = N.getOperand(0);
812 Offset = N.getOperand(1);
813 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
817 if (!CurDAG->isBaseWithConstantOffset(N)) {
819 if (N.getOpcode() == ISD::FrameIndex) {
820 int FI = cast<FrameIndexSDNode>(N)->getIndex();
821 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
823 Offset = CurDAG->getRegister(0, MVT::i32);
824 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
828 // If the RHS is +/- imm8, fold into addr mode.
830 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
831 -256 + 1, 256, RHSC)) { // 8 bits.
832 Base = N.getOperand(0);
833 if (Base.getOpcode() == ISD::FrameIndex) {
834 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
835 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
837 Offset = CurDAG->getRegister(0, MVT::i32);
839 ARM_AM::AddrOpc AddSub = ARM_AM::add;
841 AddSub = ARM_AM::sub;
844 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
848 Base = N.getOperand(0);
849 Offset = N.getOperand(1);
850 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
854 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
855 SDValue &Offset, SDValue &Opc) {
856 unsigned Opcode = Op->getOpcode();
857 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
858 ? cast<LoadSDNode>(Op)->getAddressingMode()
859 : cast<StoreSDNode>(Op)->getAddressingMode();
860 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
861 ? ARM_AM::add : ARM_AM::sub;
863 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
864 Offset = CurDAG->getRegister(0, MVT::i32);
865 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
870 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
874 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
875 SDValue &Base, SDValue &Offset) {
876 if (!CurDAG->isBaseWithConstantOffset(N)) {
878 if (N.getOpcode() == ISD::FrameIndex) {
879 int FI = cast<FrameIndexSDNode>(N)->getIndex();
880 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
881 } else if (N.getOpcode() == ARMISD::Wrapper &&
882 !(Subtarget->useMovt() &&
883 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
884 Base = N.getOperand(0);
886 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
891 // If the RHS is +/- imm8, fold into addr mode.
893 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
894 -256 + 1, 256, RHSC)) {
895 Base = N.getOperand(0);
896 if (Base.getOpcode() == ISD::FrameIndex) {
897 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
898 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
901 ARM_AM::AddrOpc AddSub = ARM_AM::add;
903 AddSub = ARM_AM::sub;
906 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
912 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
917 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
921 unsigned Alignment = 0;
922 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
923 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
924 // The maximum alignment is equal to the memory size being referenced.
925 unsigned LSNAlign = LSN->getAlignment();
926 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
927 if (LSNAlign >= MemSize && MemSize > 1)
930 // All other uses of addrmode6 are for intrinsics. For now just record
931 // the raw alignment value; it will be refined later based on the legal
932 // alignment operands for the intrinsic.
933 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
936 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
940 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
942 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
943 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
944 if (AM != ISD::POST_INC)
947 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
948 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
949 Offset = CurDAG->getRegister(0, MVT::i32);
954 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
955 SDValue &Offset, SDValue &Label) {
956 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
957 Offset = N.getOperand(0);
958 SDValue N1 = N.getOperand(1);
959 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
968 //===----------------------------------------------------------------------===//
969 // Thumb Addressing Modes
970 //===----------------------------------------------------------------------===//
972 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
973 SDValue &Base, SDValue &Offset){
974 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
975 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
976 if (!NC || !NC->isNullValue())
983 Base = N.getOperand(0);
984 Offset = N.getOperand(1);
989 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
990 SDValue &Offset, unsigned Scale) {
992 SDValue TmpBase, TmpOffImm;
993 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
994 return false; // We want to select tLDRspi / tSTRspi instead.
996 if (N.getOpcode() == ARMISD::Wrapper &&
997 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
998 return false; // We want to select tLDRpci instead.
1001 if (!CurDAG->isBaseWithConstantOffset(N))
1004 // Thumb does not have [sp, r] address mode.
1005 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1006 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1007 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1008 (RHSR && RHSR->getReg() == ARM::SP))
1011 // FIXME: Why do we explicitly check for a match here and then return false?
1012 // Presumably to allow something else to match, but shouldn't this be
1015 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1018 Base = N.getOperand(0);
1019 Offset = N.getOperand(1);
1024 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1027 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1031 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1034 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1038 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1041 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1045 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1046 SDValue &Base, SDValue &OffImm) {
1048 SDValue TmpBase, TmpOffImm;
1049 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1050 return false; // We want to select tLDRspi / tSTRspi instead.
1052 if (N.getOpcode() == ARMISD::Wrapper &&
1053 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1054 return false; // We want to select tLDRpci instead.
1057 if (!CurDAG->isBaseWithConstantOffset(N)) {
1058 if (N.getOpcode() == ARMISD::Wrapper &&
1059 !(Subtarget->useMovt() &&
1060 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1061 Base = N.getOperand(0);
1066 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1070 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1071 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1072 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1073 (RHSR && RHSR->getReg() == ARM::SP)) {
1074 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1075 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1076 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1077 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1079 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1080 if (LHSC != 0 || RHSC != 0) return false;
1083 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1087 // If the RHS is + imm5 * scale, fold into addr mode.
1089 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1090 Base = N.getOperand(0);
1091 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1095 Base = N.getOperand(0);
1096 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1101 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1103 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1107 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1109 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1113 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1115 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1118 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1119 SDValue &Base, SDValue &OffImm) {
1120 if (N.getOpcode() == ISD::FrameIndex) {
1121 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1122 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1123 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1127 if (!CurDAG->isBaseWithConstantOffset(N))
1130 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1131 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1132 (LHSR && LHSR->getReg() == ARM::SP)) {
1133 // If the RHS is + imm8 * scale, fold into addr mode.
1135 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1136 Base = N.getOperand(0);
1137 if (Base.getOpcode() == ISD::FrameIndex) {
1138 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1139 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1141 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1150 //===----------------------------------------------------------------------===//
1151 // Thumb 2 Addressing Modes
1152 //===----------------------------------------------------------------------===//
1155 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1157 if (DisableShifterOp)
1160 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1162 // Don't match base register only case. That is matched to a separate
1163 // lower complexity pattern with explicit register operand.
1164 if (ShOpcVal == ARM_AM::no_shift) return false;
1166 BaseReg = N.getOperand(0);
1167 unsigned ShImmVal = 0;
1168 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1169 ShImmVal = RHS->getZExtValue() & 31;
1170 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1177 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1178 SDValue &Base, SDValue &OffImm) {
1179 // Match simple R + imm12 operands.
1182 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1183 !CurDAG->isBaseWithConstantOffset(N)) {
1184 if (N.getOpcode() == ISD::FrameIndex) {
1185 // Match frame index.
1186 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1187 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1188 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1192 if (N.getOpcode() == ARMISD::Wrapper &&
1193 !(Subtarget->useMovt() &&
1194 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1195 Base = N.getOperand(0);
1196 if (Base.getOpcode() == ISD::TargetConstantPool)
1197 return false; // We want to select t2LDRpci instead.
1200 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1204 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1205 if (SelectT2AddrModeImm8(N, Base, OffImm))
1206 // Let t2LDRi8 handle (R - imm8).
1209 int RHSC = (int)RHS->getZExtValue();
1210 if (N.getOpcode() == ISD::SUB)
1213 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1214 Base = N.getOperand(0);
1215 if (Base.getOpcode() == ISD::FrameIndex) {
1216 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1217 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1219 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1226 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1230 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1231 SDValue &Base, SDValue &OffImm) {
1232 // Match simple R - imm8 operands.
1233 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1234 !CurDAG->isBaseWithConstantOffset(N))
1237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1238 int RHSC = (int)RHS->getSExtValue();
1239 if (N.getOpcode() == ISD::SUB)
1242 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1243 Base = N.getOperand(0);
1244 if (Base.getOpcode() == ISD::FrameIndex) {
1245 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1246 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1248 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1256 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1258 unsigned Opcode = Op->getOpcode();
1259 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1260 ? cast<LoadSDNode>(Op)->getAddressingMode()
1261 : cast<StoreSDNode>(Op)->getAddressingMode();
1263 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1264 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1265 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1266 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1273 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1275 SDValue &OffReg, SDValue &ShImm) {
1276 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1277 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1280 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1281 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1282 int RHSC = (int)RHS->getZExtValue();
1283 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1285 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1289 // Look for (R + R) or (R + (R << [1,2,3])).
1291 Base = N.getOperand(0);
1292 OffReg = N.getOperand(1);
1294 // Swap if it is ((R << c) + R).
1295 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1296 if (ShOpcVal != ARM_AM::lsl) {
1297 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1298 if (ShOpcVal == ARM_AM::lsl)
1299 std::swap(Base, OffReg);
1302 if (ShOpcVal == ARM_AM::lsl) {
1303 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1305 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1306 ShAmt = Sh->getZExtValue();
1307 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1308 OffReg = OffReg.getOperand(0);
1311 ShOpcVal = ARM_AM::no_shift;
1314 ShOpcVal = ARM_AM::no_shift;
1318 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1323 //===--------------------------------------------------------------------===//
1325 /// getAL - Returns a ARMCC::AL immediate node.
1326 static inline SDValue getAL(SelectionDAG *CurDAG) {
1327 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1330 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1331 LoadSDNode *LD = cast<LoadSDNode>(N);
1332 ISD::MemIndexedMode AM = LD->getAddressingMode();
1333 if (AM == ISD::UNINDEXED)
1336 EVT LoadedVT = LD->getMemoryVT();
1337 SDValue Offset, AMOpc;
1338 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1339 unsigned Opcode = 0;
1341 if (LoadedVT == MVT::i32 && isPre &&
1342 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1343 Opcode = ARM::LDR_PRE_IMM;
1345 } else if (LoadedVT == MVT::i32 && !isPre &&
1346 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1347 Opcode = ARM::LDR_POST_IMM;
1349 } else if (LoadedVT == MVT::i32 &&
1350 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1351 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1354 } else if (LoadedVT == MVT::i16 &&
1355 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1357 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1358 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1359 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1360 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1361 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1362 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1364 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1368 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1370 Opcode = ARM::LDRB_PRE_IMM;
1371 } else if (!isPre &&
1372 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1374 Opcode = ARM::LDRB_POST_IMM;
1375 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1377 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1383 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1384 SDValue Chain = LD->getChain();
1385 SDValue Base = LD->getBasePtr();
1386 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1387 CurDAG->getRegister(0, MVT::i32), Chain };
1388 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1389 MVT::i32, MVT::Other, Ops, 5);
1391 SDValue Chain = LD->getChain();
1392 SDValue Base = LD->getBasePtr();
1393 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1394 CurDAG->getRegister(0, MVT::i32), Chain };
1395 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1396 MVT::i32, MVT::Other, Ops, 6);
1403 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1404 LoadSDNode *LD = cast<LoadSDNode>(N);
1405 ISD::MemIndexedMode AM = LD->getAddressingMode();
1406 if (AM == ISD::UNINDEXED)
1409 EVT LoadedVT = LD->getMemoryVT();
1410 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1412 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1413 unsigned Opcode = 0;
1415 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1416 switch (LoadedVT.getSimpleVT().SimpleTy) {
1418 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1422 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1424 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1429 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1431 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1440 SDValue Chain = LD->getChain();
1441 SDValue Base = LD->getBasePtr();
1442 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1443 CurDAG->getRegister(0, MVT::i32), Chain };
1444 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1445 MVT::Other, Ops, 5);
1451 /// PairSRegs - Form a D register from a pair of S registers.
1453 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1454 DebugLoc dl = V0.getNode()->getDebugLoc();
1456 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1457 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1458 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1459 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1460 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1463 /// PairDRegs - Form a quad register from a pair of D registers.
1465 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1466 DebugLoc dl = V0.getNode()->getDebugLoc();
1467 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1468 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1469 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1470 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1471 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1474 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1476 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1477 DebugLoc dl = V0.getNode()->getDebugLoc();
1478 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1479 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1480 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1481 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1482 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1485 /// QuadSRegs - Form 4 consecutive S registers.
1487 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1488 SDValue V2, SDValue V3) {
1489 DebugLoc dl = V0.getNode()->getDebugLoc();
1491 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1492 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1493 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1494 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1495 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1496 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1497 V2, SubReg2, V3, SubReg3 };
1498 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1501 /// QuadDRegs - Form 4 consecutive D registers.
1503 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1504 SDValue V2, SDValue V3) {
1505 DebugLoc dl = V0.getNode()->getDebugLoc();
1506 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1507 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1508 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1509 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1510 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1511 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1512 V2, SubReg2, V3, SubReg3 };
1513 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1516 /// QuadQRegs - Form 4 consecutive Q registers.
1518 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1519 SDValue V2, SDValue V3) {
1520 DebugLoc dl = V0.getNode()->getDebugLoc();
1521 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1522 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1523 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1524 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1525 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1526 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1527 V2, SubReg2, V3, SubReg3 };
1528 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1531 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1532 /// of a NEON VLD or VST instruction. The supported values depend on the
1533 /// number of registers being loaded.
1534 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1535 bool is64BitVector) {
1536 unsigned NumRegs = NumVecs;
1537 if (!is64BitVector && NumVecs < 3)
1540 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1541 if (Alignment >= 32 && NumRegs == 4)
1543 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1545 else if (Alignment >= 8)
1550 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1553 // Get the register stride update opcode of a VLD/VST instruction that
1554 // is otherwise equivalent to the given fixed stride updating instruction.
1555 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1558 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1559 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1560 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1561 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1562 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1563 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1564 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1565 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1566 case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
1567 case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
1568 case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
1569 case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
1571 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1572 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1573 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1574 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1575 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1576 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1577 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1578 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1579 case ARM::VST1q8PseudoWB_fixed: return ARM::VST1q8PseudoWB_register;
1580 case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
1581 case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
1582 case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
1583 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1584 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1586 case ARM::VLD2d8PseudoWB_fixed: return ARM::VLD2d8PseudoWB_register;
1587 case ARM::VLD2d16PseudoWB_fixed: return ARM::VLD2d16PseudoWB_register;
1588 case ARM::VLD2d32PseudoWB_fixed: return ARM::VLD2d32PseudoWB_register;
1589 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1590 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1591 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1593 case ARM::VST2d8PseudoWB_fixed: return ARM::VST2d8PseudoWB_register;
1594 case ARM::VST2d16PseudoWB_fixed: return ARM::VST2d16PseudoWB_register;
1595 case ARM::VST2d32PseudoWB_fixed: return ARM::VST2d32PseudoWB_register;
1596 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1597 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1598 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1600 case ARM::VLD2DUPd8PseudoWB_fixed: return ARM::VLD2DUPd8PseudoWB_register;
1601 case ARM::VLD2DUPd16PseudoWB_fixed: return ARM::VLD2DUPd16PseudoWB_register;
1602 case ARM::VLD2DUPd32PseudoWB_fixed: return ARM::VLD2DUPd32PseudoWB_register;
1604 return Opc; // If not one we handle, return it unchanged.
1607 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1608 unsigned *DOpcodes, unsigned *QOpcodes0,
1609 unsigned *QOpcodes1) {
1610 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1611 DebugLoc dl = N->getDebugLoc();
1613 SDValue MemAddr, Align;
1614 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1615 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1618 SDValue Chain = N->getOperand(0);
1619 EVT VT = N->getValueType(0);
1620 bool is64BitVector = VT.is64BitVector();
1621 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1623 unsigned OpcodeIndex;
1624 switch (VT.getSimpleVT().SimpleTy) {
1625 default: llvm_unreachable("unhandled vld type");
1626 // Double-register operations:
1627 case MVT::v8i8: OpcodeIndex = 0; break;
1628 case MVT::v4i16: OpcodeIndex = 1; break;
1630 case MVT::v2i32: OpcodeIndex = 2; break;
1631 case MVT::v1i64: OpcodeIndex = 3; break;
1632 // Quad-register operations:
1633 case MVT::v16i8: OpcodeIndex = 0; break;
1634 case MVT::v8i16: OpcodeIndex = 1; break;
1636 case MVT::v4i32: OpcodeIndex = 2; break;
1637 case MVT::v2i64: OpcodeIndex = 3;
1638 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1646 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1649 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1651 std::vector<EVT> ResTys;
1652 ResTys.push_back(ResTy);
1654 ResTys.push_back(MVT::i32);
1655 ResTys.push_back(MVT::Other);
1657 SDValue Pred = getAL(CurDAG);
1658 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1660 SmallVector<SDValue, 7> Ops;
1662 // Double registers and VLD1/VLD2 quad registers are directly supported.
1663 if (is64BitVector || NumVecs <= 2) {
1664 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1665 QOpcodes0[OpcodeIndex]);
1666 Ops.push_back(MemAddr);
1667 Ops.push_back(Align);
1669 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1670 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1671 // case entirely when the rest are updated to that form, too.
1672 if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1673 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1674 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1675 // check for that explicitly too. Horribly hacky, but temporary.
1676 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64PseudoWB_fixed) ||
1677 !isa<ConstantSDNode>(Inc.getNode()))
1678 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1680 Ops.push_back(Pred);
1681 Ops.push_back(Reg0);
1682 Ops.push_back(Chain);
1683 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1686 // Otherwise, quad registers are loaded with two separate instructions,
1687 // where one loads the even registers and the other loads the odd registers.
1688 EVT AddrTy = MemAddr.getValueType();
1690 // Load the even subregs. This is always an updating load, so that it
1691 // provides the address to the second load for the odd subregs.
1693 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1694 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1695 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1696 ResTy, AddrTy, MVT::Other, OpsA, 7);
1697 Chain = SDValue(VLdA, 2);
1699 // Load the odd subregs.
1700 Ops.push_back(SDValue(VLdA, 1));
1701 Ops.push_back(Align);
1703 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1704 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1705 "only constant post-increment update allowed for VLD3/4");
1707 Ops.push_back(Reg0);
1709 Ops.push_back(SDValue(VLdA, 0));
1710 Ops.push_back(Pred);
1711 Ops.push_back(Reg0);
1712 Ops.push_back(Chain);
1713 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1714 Ops.data(), Ops.size());
1717 // Transfer memoperands.
1718 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1719 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1720 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1725 // Extract out the subregisters.
1726 SDValue SuperReg = SDValue(VLd, 0);
1727 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1728 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1729 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1730 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1731 ReplaceUses(SDValue(N, Vec),
1732 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1733 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1735 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1739 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1740 unsigned *DOpcodes, unsigned *QOpcodes0,
1741 unsigned *QOpcodes1) {
1742 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1743 DebugLoc dl = N->getDebugLoc();
1745 SDValue MemAddr, Align;
1746 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1747 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1748 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1751 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1752 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1754 SDValue Chain = N->getOperand(0);
1755 EVT VT = N->getOperand(Vec0Idx).getValueType();
1756 bool is64BitVector = VT.is64BitVector();
1757 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1759 unsigned OpcodeIndex;
1760 switch (VT.getSimpleVT().SimpleTy) {
1761 default: llvm_unreachable("unhandled vst type");
1762 // Double-register operations:
1763 case MVT::v8i8: OpcodeIndex = 0; break;
1764 case MVT::v4i16: OpcodeIndex = 1; break;
1766 case MVT::v2i32: OpcodeIndex = 2; break;
1767 case MVT::v1i64: OpcodeIndex = 3; break;
1768 // Quad-register operations:
1769 case MVT::v16i8: OpcodeIndex = 0; break;
1770 case MVT::v8i16: OpcodeIndex = 1; break;
1772 case MVT::v4i32: OpcodeIndex = 2; break;
1773 case MVT::v2i64: OpcodeIndex = 3;
1774 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1778 std::vector<EVT> ResTys;
1780 ResTys.push_back(MVT::i32);
1781 ResTys.push_back(MVT::Other);
1783 SDValue Pred = getAL(CurDAG);
1784 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1785 SmallVector<SDValue, 7> Ops;
1787 // Double registers and VST1/VST2 quad registers are directly supported.
1788 if (is64BitVector || NumVecs <= 2) {
1791 SrcReg = N->getOperand(Vec0Idx);
1792 } else if (is64BitVector) {
1793 // Form a REG_SEQUENCE to force register allocation.
1794 SDValue V0 = N->getOperand(Vec0Idx + 0);
1795 SDValue V1 = N->getOperand(Vec0Idx + 1);
1797 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1799 SDValue V2 = N->getOperand(Vec0Idx + 2);
1800 // If it's a vst3, form a quad D-register and leave the last part as
1802 SDValue V3 = (NumVecs == 3)
1803 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1804 : N->getOperand(Vec0Idx + 3);
1805 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1808 // Form a QQ register.
1809 SDValue Q0 = N->getOperand(Vec0Idx);
1810 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1811 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1814 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1815 QOpcodes0[OpcodeIndex]);
1816 Ops.push_back(MemAddr);
1817 Ops.push_back(Align);
1819 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1820 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1821 // case entirely when the rest are updated to that form, too.
1822 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1823 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1824 // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1825 // check for that explicitly too. Horribly hacky, but temporary.
1826 if ((NumVecs > 2 && Opc != ARM::VST1q64PseudoWB_fixed) ||
1827 !isa<ConstantSDNode>(Inc.getNode()))
1828 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1830 Ops.push_back(SrcReg);
1831 Ops.push_back(Pred);
1832 Ops.push_back(Reg0);
1833 Ops.push_back(Chain);
1835 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1837 // Transfer memoperands.
1838 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1843 // Otherwise, quad registers are stored with two separate instructions,
1844 // where one stores the even registers and the other stores the odd registers.
1846 // Form the QQQQ REG_SEQUENCE.
1847 SDValue V0 = N->getOperand(Vec0Idx + 0);
1848 SDValue V1 = N->getOperand(Vec0Idx + 1);
1849 SDValue V2 = N->getOperand(Vec0Idx + 2);
1850 SDValue V3 = (NumVecs == 3)
1851 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1852 : N->getOperand(Vec0Idx + 3);
1853 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1855 // Store the even D registers. This is always an updating store, so that it
1856 // provides the address to the second store for the odd subregs.
1857 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1858 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1859 MemAddr.getValueType(),
1860 MVT::Other, OpsA, 7);
1861 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1862 Chain = SDValue(VStA, 1);
1864 // Store the odd D registers.
1865 Ops.push_back(SDValue(VStA, 0));
1866 Ops.push_back(Align);
1868 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1869 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1870 "only constant post-increment update allowed for VST3/4");
1872 Ops.push_back(Reg0);
1874 Ops.push_back(RegSeq);
1875 Ops.push_back(Pred);
1876 Ops.push_back(Reg0);
1877 Ops.push_back(Chain);
1878 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1879 Ops.data(), Ops.size());
1880 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1884 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1885 bool isUpdating, unsigned NumVecs,
1887 unsigned *QOpcodes) {
1888 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1889 DebugLoc dl = N->getDebugLoc();
1891 SDValue MemAddr, Align;
1892 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1893 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1894 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1897 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1898 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1900 SDValue Chain = N->getOperand(0);
1902 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1903 EVT VT = N->getOperand(Vec0Idx).getValueType();
1904 bool is64BitVector = VT.is64BitVector();
1906 unsigned Alignment = 0;
1908 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1909 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1910 if (Alignment > NumBytes)
1911 Alignment = NumBytes;
1912 if (Alignment < 8 && Alignment < NumBytes)
1914 // Alignment must be a power of two; make sure of that.
1915 Alignment = (Alignment & -Alignment);
1919 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1921 unsigned OpcodeIndex;
1922 switch (VT.getSimpleVT().SimpleTy) {
1923 default: llvm_unreachable("unhandled vld/vst lane type");
1924 // Double-register operations:
1925 case MVT::v8i8: OpcodeIndex = 0; break;
1926 case MVT::v4i16: OpcodeIndex = 1; break;
1928 case MVT::v2i32: OpcodeIndex = 2; break;
1929 // Quad-register operations:
1930 case MVT::v8i16: OpcodeIndex = 0; break;
1932 case MVT::v4i32: OpcodeIndex = 1; break;
1935 std::vector<EVT> ResTys;
1937 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1940 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1941 MVT::i64, ResTyElts));
1944 ResTys.push_back(MVT::i32);
1945 ResTys.push_back(MVT::Other);
1947 SDValue Pred = getAL(CurDAG);
1948 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1950 SmallVector<SDValue, 8> Ops;
1951 Ops.push_back(MemAddr);
1952 Ops.push_back(Align);
1954 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1955 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1959 SDValue V0 = N->getOperand(Vec0Idx + 0);
1960 SDValue V1 = N->getOperand(Vec0Idx + 1);
1963 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1965 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1967 SDValue V2 = N->getOperand(Vec0Idx + 2);
1968 SDValue V3 = (NumVecs == 3)
1969 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1970 : N->getOperand(Vec0Idx + 3);
1972 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1974 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1976 Ops.push_back(SuperReg);
1977 Ops.push_back(getI32Imm(Lane));
1978 Ops.push_back(Pred);
1979 Ops.push_back(Reg0);
1980 Ops.push_back(Chain);
1982 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1983 QOpcodes[OpcodeIndex]);
1984 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1985 Ops.data(), Ops.size());
1986 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1990 // Extract the subregisters.
1991 SuperReg = SDValue(VLdLn, 0);
1992 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1993 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1994 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1995 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1996 ReplaceUses(SDValue(N, Vec),
1997 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1998 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2000 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2004 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2005 unsigned NumVecs, unsigned *Opcodes) {
2006 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2007 DebugLoc dl = N->getDebugLoc();
2009 SDValue MemAddr, Align;
2010 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2013 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2014 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2016 SDValue Chain = N->getOperand(0);
2017 EVT VT = N->getValueType(0);
2019 unsigned Alignment = 0;
2021 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2022 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2023 if (Alignment > NumBytes)
2024 Alignment = NumBytes;
2025 if (Alignment < 8 && Alignment < NumBytes)
2027 // Alignment must be a power of two; make sure of that.
2028 Alignment = (Alignment & -Alignment);
2032 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2034 unsigned OpcodeIndex;
2035 switch (VT.getSimpleVT().SimpleTy) {
2036 default: llvm_unreachable("unhandled vld-dup type");
2037 case MVT::v8i8: OpcodeIndex = 0; break;
2038 case MVT::v4i16: OpcodeIndex = 1; break;
2040 case MVT::v2i32: OpcodeIndex = 2; break;
2043 SDValue Pred = getAL(CurDAG);
2044 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2046 unsigned Opc = Opcodes[OpcodeIndex];
2047 SmallVector<SDValue, 6> Ops;
2048 Ops.push_back(MemAddr);
2049 Ops.push_back(Align);
2051 // fixed-stride update instructions don't have an explicit writeback
2052 // operand. It's implicit in the opcode itself.
2053 SDValue Inc = N->getOperand(2);
2054 if (!isa<ConstantSDNode>(Inc.getNode()))
2056 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2057 else if (NumVecs > 2)
2058 Ops.push_back(Reg0);
2060 Ops.push_back(Pred);
2061 Ops.push_back(Reg0);
2062 Ops.push_back(Chain);
2064 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2065 std::vector<EVT> ResTys;
2066 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2068 ResTys.push_back(MVT::i32);
2069 ResTys.push_back(MVT::Other);
2071 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2072 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2073 SuperReg = SDValue(VLdDup, 0);
2075 // Extract the subregisters.
2076 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2077 unsigned SubIdx = ARM::dsub_0;
2078 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2079 ReplaceUses(SDValue(N, Vec),
2080 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2081 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2083 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2087 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2089 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2090 DebugLoc dl = N->getDebugLoc();
2091 EVT VT = N->getValueType(0);
2092 unsigned FirstTblReg = IsExt ? 2 : 1;
2094 // Form a REG_SEQUENCE to force register allocation.
2096 SDValue V0 = N->getOperand(FirstTblReg + 0);
2097 SDValue V1 = N->getOperand(FirstTblReg + 1);
2099 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2101 SDValue V2 = N->getOperand(FirstTblReg + 2);
2102 // If it's a vtbl3, form a quad D-register and leave the last part as
2104 SDValue V3 = (NumVecs == 3)
2105 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2106 : N->getOperand(FirstTblReg + 3);
2107 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2110 SmallVector<SDValue, 6> Ops;
2112 Ops.push_back(N->getOperand(1));
2113 Ops.push_back(RegSeq);
2114 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2115 Ops.push_back(getAL(CurDAG)); // predicate
2116 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2117 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2120 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2122 if (!Subtarget->hasV6T2Ops())
2125 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2126 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2129 // For unsigned extracts, check for a shift right and mask
2130 unsigned And_imm = 0;
2131 if (N->getOpcode() == ISD::AND) {
2132 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2134 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2135 if (And_imm & (And_imm + 1))
2138 unsigned Srl_imm = 0;
2139 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2141 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2143 // Note: The width operand is encoded as width-1.
2144 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2145 unsigned LSB = Srl_imm;
2146 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2147 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2148 CurDAG->getTargetConstant(LSB, MVT::i32),
2149 CurDAG->getTargetConstant(Width, MVT::i32),
2150 getAL(CurDAG), Reg0 };
2151 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2157 // Otherwise, we're looking for a shift of a shift
2158 unsigned Shl_imm = 0;
2159 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2160 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2161 unsigned Srl_imm = 0;
2162 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2163 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2164 // Note: The width operand is encoded as width-1.
2165 unsigned Width = 32 - Srl_imm - 1;
2166 int LSB = Srl_imm - Shl_imm;
2169 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2170 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2171 CurDAG->getTargetConstant(LSB, MVT::i32),
2172 CurDAG->getTargetConstant(Width, MVT::i32),
2173 getAL(CurDAG), Reg0 };
2174 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2180 SDNode *ARMDAGToDAGISel::
2181 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2182 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2185 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2186 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2187 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2190 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2191 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2192 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2193 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2195 llvm_unreachable("Unknown so_reg opcode!");
2198 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2199 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2200 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2201 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2206 SDNode *ARMDAGToDAGISel::
2207 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2208 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2212 if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2213 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2214 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2215 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2218 if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2219 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2220 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2221 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2226 SDNode *ARMDAGToDAGISel::
2227 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2228 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2229 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2234 unsigned TrueImm = T->getZExtValue();
2235 if (is_t2_so_imm(TrueImm)) {
2236 Opc = ARM::t2MOVCCi;
2237 } else if (TrueImm <= 0xffff) {
2238 Opc = ARM::t2MOVCCi16;
2239 } else if (is_t2_so_imm_not(TrueImm)) {
2241 Opc = ARM::t2MVNCCi;
2242 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2244 Opc = ARM::t2MOVCCi32imm;
2248 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2249 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2250 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2251 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2257 SDNode *ARMDAGToDAGISel::
2258 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2259 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2260 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2265 unsigned TrueImm = T->getZExtValue();
2266 bool isSoImm = is_so_imm(TrueImm);
2269 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2270 Opc = ARM::MOVCCi16;
2271 } else if (is_so_imm_not(TrueImm)) {
2274 } else if (TrueVal.getNode()->hasOneUse() &&
2275 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2277 Opc = ARM::MOVCCi32imm;
2281 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2282 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2283 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2284 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2290 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2291 EVT VT = N->getValueType(0);
2292 SDValue FalseVal = N->getOperand(0);
2293 SDValue TrueVal = N->getOperand(1);
2294 SDValue CC = N->getOperand(2);
2295 SDValue CCR = N->getOperand(3);
2296 SDValue InFlag = N->getOperand(4);
2297 assert(CC.getOpcode() == ISD::Constant);
2298 assert(CCR.getOpcode() == ISD::Register);
2299 ARMCC::CondCodes CCVal =
2300 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2302 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2303 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2304 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2305 // Pattern complexity = 18 cost = 1 size = 0
2306 if (Subtarget->isThumb()) {
2307 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2308 CCVal, CCR, InFlag);
2310 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2311 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2315 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2316 CCVal, CCR, InFlag);
2318 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2319 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2324 // Pattern: (ARMcmov:i32 GPR:i32:$false,
2325 // (imm:i32)<<P:Pred_so_imm>>:$true,
2327 // Emits: (MOVCCi:i32 GPR:i32:$false,
2328 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2329 // Pattern complexity = 10 cost = 1 size = 0
2330 if (Subtarget->isThumb()) {
2331 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2332 CCVal, CCR, InFlag);
2334 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2335 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2339 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2340 CCVal, CCR, InFlag);
2342 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2343 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2349 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2350 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2351 // Pattern complexity = 6 cost = 1 size = 0
2353 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2354 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2355 // Pattern complexity = 6 cost = 11 size = 0
2357 // Also VMOVScc and VMOVDcc.
2358 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2359 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2361 switch (VT.getSimpleVT().SimpleTy) {
2362 default: llvm_unreachable("Illegal conditional move type!");
2364 Opc = Subtarget->isThumb()
2365 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2375 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2378 SDNode *ARMDAGToDAGISel::SelectConditionalOp(SDNode *N) {
2379 EVT VT = N->getValueType(0);
2380 SDValue FalseVal = N->getOperand(0);
2381 SDValue TrueVal = N->getOperand(1);
2382 ARMCC::CondCodes CCVal =
2383 (ARMCC::CondCodes)cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
2384 SDValue CCR = N->getOperand(3);
2385 assert(CCR.getOpcode() == ISD::Register);
2386 SDValue InFlag = N->getOperand(4);
2387 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2388 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2390 if (Subtarget->isThumb()) {
2393 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2395 switch (N->getOpcode()) {
2396 default: llvm_unreachable("Unexpected node");
2397 case ARMISD::CAND: Opc = ARM::t2ANDCCrs; break;
2398 case ARMISD::COR: Opc = ARM::t2ORRCCrs; break;
2399 case ARMISD::CXOR: Opc = ARM::t2EORCCrs; break;
2401 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CC, CCR, Reg0, InFlag };
2402 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
2405 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2407 unsigned TrueImm = T->getZExtValue();
2408 if (is_t2_so_imm(TrueImm)) {
2410 switch (N->getOpcode()) {
2411 default: llvm_unreachable("Unexpected node");
2412 case ARMISD::CAND: Opc = ARM::t2ANDCCri; break;
2413 case ARMISD::COR: Opc = ARM::t2ORRCCri; break;
2414 case ARMISD::CXOR: Opc = ARM::t2EORCCri; break;
2416 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2417 SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
2418 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2423 switch (N->getOpcode()) {
2424 default: llvm_unreachable("Unexpected node");
2425 case ARMISD::CAND: Opc = ARM::t2ANDCCrr; break;
2426 case ARMISD::COR: Opc = ARM::t2ORRCCrr; break;
2427 case ARMISD::CXOR: Opc = ARM::t2EORCCrr; break;
2429 SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
2430 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2436 if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2438 switch (N->getOpcode()) {
2439 default: llvm_unreachable("Unexpected node");
2440 case ARMISD::CAND: Opc = ARM::ANDCCrsi; break;
2441 case ARMISD::COR: Opc = ARM::ORRCCrsi; break;
2442 case ARMISD::CXOR: Opc = ARM::EORCCrsi; break;
2444 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, Reg0, InFlag };
2445 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
2448 if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2450 switch (N->getOpcode()) {
2451 default: llvm_unreachable("Unexpected node");
2452 case ARMISD::CAND: Opc = ARM::ANDCCrsr; break;
2453 case ARMISD::COR: Opc = ARM::ORRCCrsr; break;
2454 case ARMISD::CXOR: Opc = ARM::EORCCrsr; break;
2456 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, Reg0, InFlag };
2457 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 8);
2460 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2462 unsigned TrueImm = T->getZExtValue();
2463 if (is_so_imm(TrueImm)) {
2465 switch (N->getOpcode()) {
2466 default: llvm_unreachable("Unexpected node");
2467 case ARMISD::CAND: Opc = ARM::ANDCCri; break;
2468 case ARMISD::COR: Opc = ARM::ORRCCri; break;
2469 case ARMISD::CXOR: Opc = ARM::EORCCri; break;
2471 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2472 SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
2473 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2478 switch (N->getOpcode()) {
2479 default: llvm_unreachable("Unexpected node");
2480 case ARMISD::CAND: Opc = ARM::ANDCCrr; break;
2481 case ARMISD::COR: Opc = ARM::ORRCCrr; break;
2482 case ARMISD::CXOR: Opc = ARM::EORCCrr; break;
2484 SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
2485 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2488 /// Target-specific DAG combining for ISD::XOR.
2489 /// Target-independent combining lowers SELECT_CC nodes of the form
2490 /// select_cc setg[ge] X, 0, X, -X
2491 /// select_cc setgt X, -1, X, -X
2492 /// select_cc setl[te] X, 0, -X, X
2493 /// select_cc setlt X, 1, -X, X
2494 /// which represent Integer ABS into:
2495 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2496 /// ARM instruction selection detects the latter and matches it to
2497 /// ARM::ABS or ARM::t2ABS machine node.
2498 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2499 SDValue XORSrc0 = N->getOperand(0);
2500 SDValue XORSrc1 = N->getOperand(1);
2501 EVT VT = N->getValueType(0);
2503 if (DisableARMIntABS)
2506 if (Subtarget->isThumb1Only())
2509 if (XORSrc0.getOpcode() != ISD::ADD ||
2510 XORSrc1.getOpcode() != ISD::SRA)
2513 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2514 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2515 SDValue SRASrc0 = XORSrc1.getOperand(0);
2516 SDValue SRASrc1 = XORSrc1.getOperand(1);
2517 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2518 EVT XType = SRASrc0.getValueType();
2519 unsigned Size = XType.getSizeInBits() - 1;
2521 if (ADDSrc1 == XORSrc1 &&
2522 ADDSrc0 == SRASrc0 &&
2523 XType.isInteger() &&
2524 SRAConstant != NULL &&
2525 Size == SRAConstant->getZExtValue()) {
2527 unsigned Opcode = ARM::ABS;
2528 if (Subtarget->isThumb2())
2529 Opcode = ARM::t2ABS;
2531 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2537 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2538 // The only time a CONCAT_VECTORS operation can have legal types is when
2539 // two 64-bit vectors are concatenated to a 128-bit vector.
2540 EVT VT = N->getValueType(0);
2541 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2542 llvm_unreachable("unexpected CONCAT_VECTORS");
2543 return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2546 SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2547 SmallVector<SDValue, 6> Ops;
2548 Ops.push_back(Node->getOperand(1)); // Ptr
2549 Ops.push_back(Node->getOperand(2)); // Low part of Val1
2550 Ops.push_back(Node->getOperand(3)); // High part of Val1
2551 if (Opc == ARM::ATOMCMPXCHG6432) {
2552 Ops.push_back(Node->getOperand(4)); // Low part of Val2
2553 Ops.push_back(Node->getOperand(5)); // High part of Val2
2555 Ops.push_back(Node->getOperand(0)); // Chain
2556 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2557 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2558 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2559 MVT::i32, MVT::i32, MVT::Other,
2560 Ops.data() ,Ops.size());
2561 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2565 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2566 DebugLoc dl = N->getDebugLoc();
2568 if (N->isMachineOpcode())
2569 return NULL; // Already selected.
2571 switch (N->getOpcode()) {
2574 // Select special operations if XOR node forms integer ABS pattern
2575 SDNode *ResNode = SelectABSOp(N);
2578 // Other cases are autogenerated.
2581 case ISD::Constant: {
2582 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2584 if (Subtarget->hasThumb2())
2585 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2586 // be done with MOV + MOVT, at worst.
2589 if (Subtarget->isThumb()) {
2590 UseCP = (Val > 255 && // MOV
2591 ~Val > 255 && // MOV + MVN
2592 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2594 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2595 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2596 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2601 CurDAG->getTargetConstantPool(ConstantInt::get(
2602 Type::getInt32Ty(*CurDAG->getContext()), Val),
2603 TLI.getPointerTy());
2606 if (Subtarget->isThumb1Only()) {
2607 SDValue Pred = getAL(CurDAG);
2608 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2609 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2610 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2615 CurDAG->getTargetConstant(0, MVT::i32),
2617 CurDAG->getRegister(0, MVT::i32),
2618 CurDAG->getEntryNode()
2620 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2623 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2627 // Other cases are autogenerated.
2630 case ISD::FrameIndex: {
2631 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2632 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2633 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2634 if (Subtarget->isThumb1Only()) {
2635 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2636 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2637 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2639 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2640 ARM::t2ADDri : ARM::ADDri);
2641 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2642 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2643 CurDAG->getRegister(0, MVT::i32) };
2644 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2648 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2652 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2656 if (Subtarget->isThumb1Only())
2658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2659 unsigned RHSV = C->getZExtValue();
2661 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2662 unsigned ShImm = Log2_32(RHSV-1);
2665 SDValue V = N->getOperand(0);
2666 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2667 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2668 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2669 if (Subtarget->isThumb()) {
2670 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2671 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2673 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2674 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2677 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2678 unsigned ShImm = Log2_32(RHSV+1);
2681 SDValue V = N->getOperand(0);
2682 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2683 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2684 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2685 if (Subtarget->isThumb()) {
2686 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2687 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2689 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2690 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2696 // Check for unsigned bitfield extract
2697 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2700 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2701 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2702 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2703 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2704 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2705 EVT VT = N->getValueType(0);
2708 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2710 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2713 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2714 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2717 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2718 SDValue N2 = N0.getOperand(1);
2719 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2722 unsigned N1CVal = N1C->getZExtValue();
2723 unsigned N2CVal = N2C->getZExtValue();
2724 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2725 (N1CVal & 0xffffU) == 0xffffU &&
2726 (N2CVal & 0xffffU) == 0x0U) {
2727 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2729 SDValue Ops[] = { N0.getOperand(0), Imm16,
2730 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2731 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2736 case ARMISD::VMOVRRD:
2737 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2738 N->getOperand(0), getAL(CurDAG),
2739 CurDAG->getRegister(0, MVT::i32));
2740 case ISD::UMUL_LOHI: {
2741 if (Subtarget->isThumb1Only())
2743 if (Subtarget->isThumb()) {
2744 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2745 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2746 CurDAG->getRegister(0, MVT::i32) };
2747 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2749 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2750 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2751 CurDAG->getRegister(0, MVT::i32) };
2752 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2753 ARM::UMULL : ARM::UMULLv5,
2754 dl, MVT::i32, MVT::i32, Ops, 5);
2757 case ISD::SMUL_LOHI: {
2758 if (Subtarget->isThumb1Only())
2760 if (Subtarget->isThumb()) {
2761 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2762 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2763 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2765 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2766 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2767 CurDAG->getRegister(0, MVT::i32) };
2768 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2769 ARM::SMULL : ARM::SMULLv5,
2770 dl, MVT::i32, MVT::i32, Ops, 5);
2774 SDNode *ResNode = 0;
2775 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2776 ResNode = SelectT2IndexedLoad(N);
2778 ResNode = SelectARMIndexedLoad(N);
2781 // Other cases are autogenerated.
2784 case ARMISD::BRCOND: {
2785 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2786 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2787 // Pattern complexity = 6 cost = 1 size = 0
2789 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2790 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2791 // Pattern complexity = 6 cost = 1 size = 0
2793 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2794 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2795 // Pattern complexity = 6 cost = 1 size = 0
2797 unsigned Opc = Subtarget->isThumb() ?
2798 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2799 SDValue Chain = N->getOperand(0);
2800 SDValue N1 = N->getOperand(1);
2801 SDValue N2 = N->getOperand(2);
2802 SDValue N3 = N->getOperand(3);
2803 SDValue InFlag = N->getOperand(4);
2804 assert(N1.getOpcode() == ISD::BasicBlock);
2805 assert(N2.getOpcode() == ISD::Constant);
2806 assert(N3.getOpcode() == ISD::Register);
2808 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2809 cast<ConstantSDNode>(N2)->getZExtValue()),
2811 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2812 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2814 Chain = SDValue(ResNode, 0);
2815 if (N->getNumValues() == 2) {
2816 InFlag = SDValue(ResNode, 1);
2817 ReplaceUses(SDValue(N, 1), InFlag);
2819 ReplaceUses(SDValue(N, 0),
2820 SDValue(Chain.getNode(), Chain.getResNo()));
2824 return SelectCMOVOp(N);
2828 return SelectConditionalOp(N);
2829 case ARMISD::VZIP: {
2831 EVT VT = N->getValueType(0);
2832 switch (VT.getSimpleVT().SimpleTy) {
2833 default: return NULL;
2834 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2835 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2837 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2838 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2839 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2841 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2843 SDValue Pred = getAL(CurDAG);
2844 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2845 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2846 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2848 case ARMISD::VUZP: {
2850 EVT VT = N->getValueType(0);
2851 switch (VT.getSimpleVT().SimpleTy) {
2852 default: return NULL;
2853 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2854 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2856 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2857 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2858 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2860 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2862 SDValue Pred = getAL(CurDAG);
2863 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2864 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2865 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2867 case ARMISD::VTRN: {
2869 EVT VT = N->getValueType(0);
2870 switch (VT.getSimpleVT().SimpleTy) {
2871 default: return NULL;
2872 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2873 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2875 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2876 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2877 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2879 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2881 SDValue Pred = getAL(CurDAG);
2882 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2883 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2884 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2886 case ARMISD::BUILD_VECTOR: {
2887 EVT VecVT = N->getValueType(0);
2888 EVT EltVT = VecVT.getVectorElementType();
2889 unsigned NumElts = VecVT.getVectorNumElements();
2890 if (EltVT == MVT::f64) {
2891 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2892 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2894 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2896 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2897 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2898 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2899 N->getOperand(2), N->getOperand(3));
2902 case ARMISD::VLD2DUP: {
2903 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2904 ARM::VLD2DUPd32Pseudo };
2905 return SelectVLDDup(N, false, 2, Opcodes);
2908 case ARMISD::VLD3DUP: {
2909 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2910 ARM::VLD3DUPd32Pseudo };
2911 return SelectVLDDup(N, false, 3, Opcodes);
2914 case ARMISD::VLD4DUP: {
2915 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2916 ARM::VLD4DUPd32Pseudo };
2917 return SelectVLDDup(N, false, 4, Opcodes);
2920 case ARMISD::VLD2DUP_UPD: {
2921 unsigned Opcodes[] = { ARM::VLD2DUPd8PseudoWB_fixed,
2922 ARM::VLD2DUPd16PseudoWB_fixed,
2923 ARM::VLD2DUPd32PseudoWB_fixed };
2924 return SelectVLDDup(N, true, 2, Opcodes);
2927 case ARMISD::VLD3DUP_UPD: {
2928 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2929 ARM::VLD3DUPd32Pseudo_UPD };
2930 return SelectVLDDup(N, true, 3, Opcodes);
2933 case ARMISD::VLD4DUP_UPD: {
2934 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2935 ARM::VLD4DUPd32Pseudo_UPD };
2936 return SelectVLDDup(N, true, 4, Opcodes);
2939 case ARMISD::VLD1_UPD: {
2940 unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
2941 ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2942 unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
2943 ARM::VLD1q16PseudoWB_fixed,
2944 ARM::VLD1q32PseudoWB_fixed,
2945 ARM::VLD1q64PseudoWB_fixed };
2946 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2949 case ARMISD::VLD2_UPD: {
2950 unsigned DOpcodes[] = { ARM::VLD2d8PseudoWB_fixed,
2951 ARM::VLD2d16PseudoWB_fixed,
2952 ARM::VLD2d32PseudoWB_fixed,
2953 ARM::VLD1q64PseudoWB_fixed};
2954 unsigned QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2955 ARM::VLD2q16PseudoWB_fixed,
2956 ARM::VLD2q32PseudoWB_fixed };
2957 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2960 case ARMISD::VLD3_UPD: {
2961 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2962 ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2963 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2964 ARM::VLD3q16Pseudo_UPD,
2965 ARM::VLD3q32Pseudo_UPD };
2966 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2967 ARM::VLD3q16oddPseudo_UPD,
2968 ARM::VLD3q32oddPseudo_UPD };
2969 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2972 case ARMISD::VLD4_UPD: {
2973 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2974 ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2975 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2976 ARM::VLD4q16Pseudo_UPD,
2977 ARM::VLD4q32Pseudo_UPD };
2978 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2979 ARM::VLD4q16oddPseudo_UPD,
2980 ARM::VLD4q32oddPseudo_UPD };
2981 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2984 case ARMISD::VLD2LN_UPD: {
2985 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2986 ARM::VLD2LNd32Pseudo_UPD };
2987 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2988 ARM::VLD2LNq32Pseudo_UPD };
2989 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2992 case ARMISD::VLD3LN_UPD: {
2993 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2994 ARM::VLD3LNd32Pseudo_UPD };
2995 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2996 ARM::VLD3LNq32Pseudo_UPD };
2997 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
3000 case ARMISD::VLD4LN_UPD: {
3001 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
3002 ARM::VLD4LNd32Pseudo_UPD };
3003 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
3004 ARM::VLD4LNq32Pseudo_UPD };
3005 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
3008 case ARMISD::VST1_UPD: {
3009 unsigned DOpcodes[] = { ARM::VST1d8wb_fixed, ARM::VST1d16wb_fixed,
3010 ARM::VST1d32wb_fixed, ARM::VST1d64wb_fixed };
3011 unsigned QOpcodes[] = { ARM::VST1q8PseudoWB_fixed,
3012 ARM::VST1q16PseudoWB_fixed,
3013 ARM::VST1q32PseudoWB_fixed,
3014 ARM::VST1q64PseudoWB_fixed };
3015 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
3018 case ARMISD::VST2_UPD: {
3019 unsigned DOpcodes[] = { ARM::VST2d8PseudoWB_fixed,
3020 ARM::VST2d16PseudoWB_fixed,
3021 ARM::VST2d32PseudoWB_fixed,
3022 ARM::VST1q64PseudoWB_fixed};
3023 unsigned QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
3024 ARM::VST2q16PseudoWB_fixed,
3025 ARM::VST2q32PseudoWB_fixed };
3026 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
3029 case ARMISD::VST3_UPD: {
3030 unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
3031 ARM::VST3d32Pseudo_UPD,ARM::VST1d64TPseudoWB_fixed};
3032 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3033 ARM::VST3q16Pseudo_UPD,
3034 ARM::VST3q32Pseudo_UPD };
3035 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
3036 ARM::VST3q16oddPseudo_UPD,
3037 ARM::VST3q32oddPseudo_UPD };
3038 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3041 case ARMISD::VST4_UPD: {
3042 unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
3043 ARM::VST4d32Pseudo_UPD,ARM::VST1d64QPseudoWB_fixed};
3044 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3045 ARM::VST4q16Pseudo_UPD,
3046 ARM::VST4q32Pseudo_UPD };
3047 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
3048 ARM::VST4q16oddPseudo_UPD,
3049 ARM::VST4q32oddPseudo_UPD };
3050 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3053 case ARMISD::VST2LN_UPD: {
3054 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
3055 ARM::VST2LNd32Pseudo_UPD };
3056 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3057 ARM::VST2LNq32Pseudo_UPD };
3058 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
3061 case ARMISD::VST3LN_UPD: {
3062 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
3063 ARM::VST3LNd32Pseudo_UPD };
3064 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3065 ARM::VST3LNq32Pseudo_UPD };
3066 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
3069 case ARMISD::VST4LN_UPD: {
3070 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
3071 ARM::VST4LNd32Pseudo_UPD };
3072 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3073 ARM::VST4LNq32Pseudo_UPD };
3074 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3077 case ISD::INTRINSIC_VOID:
3078 case ISD::INTRINSIC_W_CHAIN: {
3079 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3084 case Intrinsic::arm_ldrexd: {
3085 SDValue MemAddr = N->getOperand(2);
3086 DebugLoc dl = N->getDebugLoc();
3087 SDValue Chain = N->getOperand(0);
3089 unsigned NewOpc = ARM::LDREXD;
3090 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3091 NewOpc = ARM::t2LDREXD;
3093 // arm_ldrexd returns a i64 value in {i32, i32}
3094 std::vector<EVT> ResTys;
3095 ResTys.push_back(MVT::i32);
3096 ResTys.push_back(MVT::i32);
3097 ResTys.push_back(MVT::Other);
3099 // place arguments in the right order
3100 SmallVector<SDValue, 7> Ops;
3101 Ops.push_back(MemAddr);
3102 Ops.push_back(getAL(CurDAG));
3103 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3104 Ops.push_back(Chain);
3105 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3107 // Transfer memoperands.
3108 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3109 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3110 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3112 // Until there's support for specifing explicit register constraints
3113 // like the use of even/odd register pair, hardcode ldrexd to always
3114 // use the pair [R0, R1] to hold the load result.
3115 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
3116 SDValue(Ld, 0), SDValue(0,0));
3117 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
3118 SDValue(Ld, 1), Chain.getValue(1));
3121 SDValue Glue = Chain.getValue(1);
3122 if (!SDValue(N, 0).use_empty()) {
3123 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3124 ARM::R0, MVT::i32, Glue);
3125 Glue = Result.getValue(2);
3126 ReplaceUses(SDValue(N, 0), Result);
3128 if (!SDValue(N, 1).use_empty()) {
3129 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3130 ARM::R1, MVT::i32, Glue);
3131 Glue = Result.getValue(2);
3132 ReplaceUses(SDValue(N, 1), Result);
3135 ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
3139 case Intrinsic::arm_strexd: {
3140 DebugLoc dl = N->getDebugLoc();
3141 SDValue Chain = N->getOperand(0);
3142 SDValue Val0 = N->getOperand(2);
3143 SDValue Val1 = N->getOperand(3);
3144 SDValue MemAddr = N->getOperand(4);
3146 // Until there's support for specifing explicit register constraints
3147 // like the use of even/odd register pair, hardcode strexd to always
3148 // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
3149 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
3151 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
3153 SDValue Glue = Chain.getValue(1);
3154 Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3155 ARM::R2, MVT::i32, Glue);
3156 Glue = Val0.getValue(1);
3157 Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3158 ARM::R3, MVT::i32, Glue);
3160 // Store exclusive double return a i32 value which is the return status
3161 // of the issued store.
3162 std::vector<EVT> ResTys;
3163 ResTys.push_back(MVT::i32);
3164 ResTys.push_back(MVT::Other);
3166 // place arguments in the right order
3167 SmallVector<SDValue, 7> Ops;
3168 Ops.push_back(Val0);
3169 Ops.push_back(Val1);
3170 Ops.push_back(MemAddr);
3171 Ops.push_back(getAL(CurDAG));
3172 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3173 Ops.push_back(Chain);
3175 unsigned NewOpc = ARM::STREXD;
3176 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3177 NewOpc = ARM::t2STREXD;
3179 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3181 // Transfer memoperands.
3182 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3183 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3184 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3189 case Intrinsic::arm_neon_vld1: {
3190 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3191 ARM::VLD1d32, ARM::VLD1d64 };
3192 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
3193 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
3194 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3197 case Intrinsic::arm_neon_vld2: {
3198 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3199 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3200 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3201 ARM::VLD2q32Pseudo };
3202 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3205 case Intrinsic::arm_neon_vld3: {
3206 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3207 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3208 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3209 ARM::VLD3q16Pseudo_UPD,
3210 ARM::VLD3q32Pseudo_UPD };
3211 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3212 ARM::VLD3q16oddPseudo,
3213 ARM::VLD3q32oddPseudo };
3214 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3217 case Intrinsic::arm_neon_vld4: {
3218 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3219 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3220 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3221 ARM::VLD4q16Pseudo_UPD,
3222 ARM::VLD4q32Pseudo_UPD };
3223 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3224 ARM::VLD4q16oddPseudo,
3225 ARM::VLD4q32oddPseudo };
3226 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3229 case Intrinsic::arm_neon_vld2lane: {
3230 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3231 ARM::VLD2LNd32Pseudo };
3232 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3233 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3236 case Intrinsic::arm_neon_vld3lane: {
3237 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3238 ARM::VLD3LNd32Pseudo };
3239 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3240 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3243 case Intrinsic::arm_neon_vld4lane: {
3244 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3245 ARM::VLD4LNd32Pseudo };
3246 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3247 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3250 case Intrinsic::arm_neon_vst1: {
3251 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3252 ARM::VST1d32, ARM::VST1d64 };
3253 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3254 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3255 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3258 case Intrinsic::arm_neon_vst2: {
3259 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3260 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3261 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3262 ARM::VST2q32Pseudo };
3263 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3266 case Intrinsic::arm_neon_vst3: {
3267 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3268 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3269 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3270 ARM::VST3q16Pseudo_UPD,
3271 ARM::VST3q32Pseudo_UPD };
3272 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3273 ARM::VST3q16oddPseudo,
3274 ARM::VST3q32oddPseudo };
3275 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3278 case Intrinsic::arm_neon_vst4: {
3279 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3280 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3281 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3282 ARM::VST4q16Pseudo_UPD,
3283 ARM::VST4q32Pseudo_UPD };
3284 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3285 ARM::VST4q16oddPseudo,
3286 ARM::VST4q32oddPseudo };
3287 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3290 case Intrinsic::arm_neon_vst2lane: {
3291 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3292 ARM::VST2LNd32Pseudo };
3293 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3294 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3297 case Intrinsic::arm_neon_vst3lane: {
3298 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3299 ARM::VST3LNd32Pseudo };
3300 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3301 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3304 case Intrinsic::arm_neon_vst4lane: {
3305 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3306 ARM::VST4LNd32Pseudo };
3307 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3308 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3314 case ISD::INTRINSIC_WO_CHAIN: {
3315 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3320 case Intrinsic::arm_neon_vtbl2:
3321 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3322 case Intrinsic::arm_neon_vtbl3:
3323 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3324 case Intrinsic::arm_neon_vtbl4:
3325 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3327 case Intrinsic::arm_neon_vtbx2:
3328 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3329 case Intrinsic::arm_neon_vtbx3:
3330 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3331 case Intrinsic::arm_neon_vtbx4:
3332 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3337 case ARMISD::VTBL1: {
3338 DebugLoc dl = N->getDebugLoc();
3339 EVT VT = N->getValueType(0);
3340 SmallVector<SDValue, 6> Ops;
3342 Ops.push_back(N->getOperand(0));
3343 Ops.push_back(N->getOperand(1));
3344 Ops.push_back(getAL(CurDAG)); // Predicate
3345 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3346 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3348 case ARMISD::VTBL2: {
3349 DebugLoc dl = N->getDebugLoc();
3350 EVT VT = N->getValueType(0);
3352 // Form a REG_SEQUENCE to force register allocation.
3353 SDValue V0 = N->getOperand(0);
3354 SDValue V1 = N->getOperand(1);
3355 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3357 SmallVector<SDValue, 6> Ops;
3358 Ops.push_back(RegSeq);
3359 Ops.push_back(N->getOperand(2));
3360 Ops.push_back(getAL(CurDAG)); // Predicate
3361 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3362 return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3363 Ops.data(), Ops.size());
3366 case ISD::CONCAT_VECTORS:
3367 return SelectConcatVector(N);
3369 case ARMISD::ATOMOR64_DAG:
3370 return SelectAtomic64(N, ARM::ATOMOR6432);
3371 case ARMISD::ATOMXOR64_DAG:
3372 return SelectAtomic64(N, ARM::ATOMXOR6432);
3373 case ARMISD::ATOMADD64_DAG:
3374 return SelectAtomic64(N, ARM::ATOMADD6432);
3375 case ARMISD::ATOMSUB64_DAG:
3376 return SelectAtomic64(N, ARM::ATOMSUB6432);
3377 case ARMISD::ATOMNAND64_DAG:
3378 return SelectAtomic64(N, ARM::ATOMNAND6432);
3379 case ARMISD::ATOMAND64_DAG:
3380 return SelectAtomic64(N, ARM::ATOMAND6432);
3381 case ARMISD::ATOMSWAP64_DAG:
3382 return SelectAtomic64(N, ARM::ATOMSWAP6432);
3383 case ARMISD::ATOMCMPXCHG64_DAG:
3384 return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3387 return SelectCode(N);
3390 bool ARMDAGToDAGISel::
3391 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3392 std::vector<SDValue> &OutOps) {
3393 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3394 // Require the address to be in a register. That is safe for all ARM
3395 // variants and it is hard to do anything much smarter without knowing
3396 // how the operand is used.
3397 OutOps.push_back(Op);
3401 /// createARMISelDag - This pass converts a legalized DAG into a
3402 /// ARM-specific DAG, ready for instruction scheduling.
3404 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3405 CodeGenOpt::Level OptLevel) {
3406 return new ARMDAGToDAGISel(TM, OptLevel);