1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59 public ARMCodeEmitter {
61 const ARMInstrInfo *II;
65 const std::vector<MachineConstantPoolEntry> *MCPEs;
66 const std::vector<MachineJumpTableEntry> *MJTEs;
71 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
72 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
73 MCE(mce), MCPEs(0), MJTEs(0),
74 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
75 Emitter(TargetMachine &tm, CodeEmitter &mce,
76 const ARMInstrInfo &ii, const TargetData &td)
77 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
78 MCE(mce), MCPEs(0), MJTEs(0),
79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
81 bool runOnMachineFunction(MachineFunction &MF);
83 virtual const char *getPassName() const {
84 return "ARM Machine Code Emitter";
87 void emitInstruction(const MachineInstr &MI);
91 void emitWordLE(unsigned Binary);
93 void emitDWordLE(uint64_t Binary);
95 void emitConstPoolInstruction(const MachineInstr &MI);
97 void emitMOVi2piecesInstruction(const MachineInstr &MI);
99 void emitLEApcrelJTInstruction(const MachineInstr &MI);
101 void emitPseudoMoveInstruction(const MachineInstr &MI);
103 void addPCLabel(unsigned LabelID);
105 void emitPseudoInstruction(const MachineInstr &MI);
107 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
108 const TargetInstrDesc &TID,
109 const MachineOperand &MO,
112 unsigned getMachineSoImmOpValue(unsigned SoImm);
114 unsigned getAddrModeSBit(const MachineInstr &MI,
115 const TargetInstrDesc &TID) const;
117 void emitDataProcessingInstruction(const MachineInstr &MI,
118 unsigned ImplicitRd = 0,
119 unsigned ImplicitRn = 0);
121 void emitLoadStoreInstruction(const MachineInstr &MI,
122 unsigned ImplicitRd = 0,
123 unsigned ImplicitRn = 0);
125 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
126 unsigned ImplicitRn = 0);
128 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
130 void emitMulFrmInstruction(const MachineInstr &MI);
132 void emitExtendInstruction(const MachineInstr &MI);
134 void emitMiscArithInstruction(const MachineInstr &MI);
136 void emitBranchInstruction(const MachineInstr &MI);
138 void emitInlineJumpTable(unsigned JTIndex);
140 void emitMiscBranchInstruction(const MachineInstr &MI);
142 void emitVFPArithInstruction(const MachineInstr &MI);
144 void emitVFPConversionInstruction(const MachineInstr &MI);
146 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
148 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
150 void emitMiscInstruction(const MachineInstr &MI);
152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
154 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
161 unsigned getShiftOp(unsigned Imm) const ;
163 /// Routines that handle operands which add machine relocations which are
164 /// fixed up by the relocation stage.
165 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166 bool NeedStub, intptr_t ACPV = 0);
167 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171 intptr_t JTBase = 0);
173 template <class CodeEmitter>
174 char Emitter<CodeEmitter>::ID = 0;
177 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
178 /// to the specified MCE object.
180 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
181 MachineCodeEmitter &MCE) {
182 return new Emitter<MachineCodeEmitter>(TM, MCE);
184 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
185 JITCodeEmitter &JCE) {
186 return new Emitter<JITCodeEmitter>(TM, JCE);
188 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
189 ObjectCodeEmitter &OCE) {
190 return new Emitter<ObjectCodeEmitter>(TM, OCE);
193 template<class CodeEmitter>
194 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
195 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196 MF.getTarget().getRelocationModel() != Reloc::Static) &&
197 "JIT relocation model must be set to static or default!");
198 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
199 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
200 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
201 MCPEs = &MF.getConstantPool()->getConstants();
202 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204 JTI->Initialize(MF, IsPIC);
207 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
208 MCE.startFunction(MF);
209 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211 MCE.StartMachineBasicBlock(MBB);
212 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
216 } while (MCE.finishFunction(MF));
221 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223 template<class CodeEmitter>
224 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
225 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
226 default: LLVM_UNREACHABLE("Unknown shift opc!");
227 case ARM_AM::asr: return 2;
228 case ARM_AM::lsl: return 0;
229 case ARM_AM::lsr: return 1;
231 case ARM_AM::rrx: return 3;
236 /// getMachineOpValue - Return binary encoding of operand. If the machine
237 /// operand requires relocation, record the relocation and return zero.
238 template<class CodeEmitter>
239 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
240 const MachineOperand &MO) {
242 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
244 return static_cast<unsigned>(MO.getImm());
245 else if (MO.isGlobal())
246 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
247 else if (MO.isSymbol())
248 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
249 else if (MO.isCPI()) {
250 const TargetInstrDesc &TID = MI.getDesc();
251 // For VFP load, the immediate offset is multiplied by 4.
252 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
253 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
254 emitConstPoolAddress(MO.getIndex(), Reloc);
255 } else if (MO.isJTI())
256 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
258 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
261 raw_string_ostream Msg(msg);
262 Msg << "ERROR: Unknown type of MachineOperand: " << MO;
263 llvm_report_error(Msg.str());
268 /// emitGlobalAddress - Emit the specified address to the code stream.
270 template<class CodeEmitter>
271 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
272 bool NeedStub, intptr_t ACPV) {
273 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
274 GV, ACPV, NeedStub));
277 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
278 /// be emitted to the current location in the function, and allow it to be PC
280 template<class CodeEmitter>
281 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
283 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
287 /// emitConstPoolAddress - Arrange for the address of an constant pool
288 /// to be emitted to the current location in the function, and allow it to be PC
290 template<class CodeEmitter>
291 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
293 // Tell JIT emitter we'll resolve the address.
294 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
295 Reloc, CPI, 0, true));
298 /// emitJumpTableAddress - Arrange for the address of a jump table to
299 /// be emitted to the current location in the function, and allow it to be PC
301 template<class CodeEmitter>
302 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
304 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
305 Reloc, JTIndex, 0, true));
308 /// emitMachineBasicBlock - Emit the specified address basic block.
309 template<class CodeEmitter>
310 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
311 unsigned Reloc, intptr_t JTBase) {
312 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
316 template<class CodeEmitter>
317 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
319 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
320 << Binary << std::dec << "\n";
322 MCE.emitWordLE(Binary);
325 template<class CodeEmitter>
326 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
328 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
329 << (unsigned)Binary << std::dec << "\n";
330 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
331 << (unsigned)(Binary >> 32) << std::dec << "\n";
333 MCE.emitDWordLE(Binary);
336 template<class CodeEmitter>
337 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
338 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
340 NumEmitted++; // Keep track of the # of mi's emitted
341 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
343 LLVM_UNREACHABLE("Unhandled instruction encoding format!");
347 emitPseudoInstruction(MI);
350 case ARMII::DPSoRegFrm:
351 emitDataProcessingInstruction(MI);
355 emitLoadStoreInstruction(MI);
357 case ARMII::LdMiscFrm:
358 case ARMII::StMiscFrm:
359 emitMiscLoadStoreInstruction(MI);
361 case ARMII::LdStMulFrm:
362 emitLoadStoreMultipleInstruction(MI);
365 emitMulFrmInstruction(MI);
368 emitExtendInstruction(MI);
370 case ARMII::ArithMiscFrm:
371 emitMiscArithInstruction(MI);
374 emitBranchInstruction(MI);
376 case ARMII::BrMiscFrm:
377 emitMiscBranchInstruction(MI);
380 case ARMII::VFPUnaryFrm:
381 case ARMII::VFPBinaryFrm:
382 emitVFPArithInstruction(MI);
384 case ARMII::VFPConv1Frm:
385 case ARMII::VFPConv2Frm:
386 case ARMII::VFPConv3Frm:
387 case ARMII::VFPConv4Frm:
388 case ARMII::VFPConv5Frm:
389 emitVFPConversionInstruction(MI);
391 case ARMII::VFPLdStFrm:
392 emitVFPLoadStoreInstruction(MI);
394 case ARMII::VFPLdStMulFrm:
395 emitVFPLoadStoreMultipleInstruction(MI);
397 case ARMII::VFPMiscFrm:
398 emitMiscInstruction(MI);
403 template<class CodeEmitter>
404 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
405 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
406 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
407 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
409 // Remember the CONSTPOOL_ENTRY address for later relocation.
410 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
412 // Emit constpool island entry. In most cases, the actual values will be
413 // resolved and relocated after code emission.
414 if (MCPE.isMachineConstantPoolEntry()) {
415 ARMConstantPoolValue *ACPV =
416 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
418 DOUT << " ** ARM constant pool #" << CPI << " @ "
419 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
421 GlobalValue *GV = ACPV->getGV();
423 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
424 if (ACPV->isNonLazyPointer())
425 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
426 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
427 (intptr_t)ACPV, false));
429 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
430 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
432 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
433 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
437 Constant *CV = MCPE.Val.ConstVal;
440 DOUT << " ** Constant pool #" << CPI << " @ "
441 << (void*)MCE.getCurrentPCValue() << " ";
442 if (const Function *F = dyn_cast<Function>(CV))
443 DOUT << F->getName();
449 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
450 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
452 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
453 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
455 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
456 if (CFP->getType() == Type::FloatTy)
457 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
458 else if (CFP->getType() == Type::DoubleTy)
459 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
461 LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
464 LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
469 template<class CodeEmitter>
470 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
471 const MachineOperand &MO0 = MI.getOperand(0);
472 const MachineOperand &MO1 = MI.getOperand(1);
473 assert(MO1.isImm() && "Not a valid so_imm value!");
474 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
475 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
477 // Emit the 'mov' instruction.
478 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
480 // Set the conditional execution predicate.
481 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
484 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
487 // Set bit I(25) to identify this is the immediate form of <shifter_op>
488 Binary |= 1 << ARMII::I_BitShift;
489 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
492 // Now the 'orr' instruction.
493 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
495 // Set the conditional execution predicate.
496 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
499 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
502 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
505 // Set bit I(25) to identify this is the immediate form of <shifter_op>
506 Binary |= 1 << ARMII::I_BitShift;
507 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
511 template<class CodeEmitter>
512 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
513 // It's basically add r, pc, (LJTI - $+8)
515 const TargetInstrDesc &TID = MI.getDesc();
517 // Emit the 'add' instruction.
518 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
520 // Set the conditional execution predicate
521 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
523 // Encode S bit if MI modifies CPSR.
524 Binary |= getAddrModeSBit(MI, TID);
527 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
529 // Encode Rn which is PC.
530 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
532 // Encode the displacement.
533 Binary |= 1 << ARMII::I_BitShift;
534 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
539 template<class CodeEmitter>
540 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
541 unsigned Opcode = MI.getDesc().Opcode;
543 // Part of binary is determined by TableGn.
544 unsigned Binary = getBinaryCodeForInstr(MI);
546 // Set the conditional execution predicate
547 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
549 // Encode S bit if MI modifies CPSR.
550 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
551 Binary |= 1 << ARMII::S_BitShift;
553 // Encode register def if there is one.
554 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
556 // Encode the shift operation.
563 case ARM::MOVsrl_flag:
565 Binary |= (0x2 << 4) | (1 << 7);
567 case ARM::MOVsra_flag:
569 Binary |= (0x4 << 4) | (1 << 7);
573 // Encode register Rm.
574 Binary |= getMachineOpValue(MI, 1);
579 template<class CodeEmitter>
580 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
581 DOUT << " ** LPC" << LabelID << " @ "
582 << (void*)MCE.getCurrentPCValue() << '\n';
583 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
586 template<class CodeEmitter>
587 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
588 unsigned Opcode = MI.getDesc().Opcode;
591 llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
592 case TargetInstrInfo::INLINEASM: {
593 // We allow inline assembler nodes with empty bodies - they can
594 // implicitly define registers, which is ok for JIT.
595 if (MI.getOperand(0).getSymbolName()[0]) {
596 llvm_report_error("JIT does not support inline asm!\n");
600 case TargetInstrInfo::DBG_LABEL:
601 case TargetInstrInfo::EH_LABEL:
602 MCE.emitLabel(MI.getOperand(0).getImm());
604 case TargetInstrInfo::IMPLICIT_DEF:
605 case TargetInstrInfo::DECLARE:
609 case ARM::CONSTPOOL_ENTRY:
610 emitConstPoolInstruction(MI);
613 // Remember of the address of the PC label for relocation later.
614 addPCLabel(MI.getOperand(2).getImm());
615 // PICADD is just an add instruction that implicitly read pc.
616 emitDataProcessingInstruction(MI, 0, ARM::PC);
623 // Remember of the address of the PC label for relocation later.
624 addPCLabel(MI.getOperand(2).getImm());
625 // These are just load / store instructions that implicitly read pc.
626 emitLoadStoreInstruction(MI, 0, ARM::PC);
633 // Remember of the address of the PC label for relocation later.
634 addPCLabel(MI.getOperand(2).getImm());
635 // These are just load / store instructions that implicitly read pc.
636 emitMiscLoadStoreInstruction(MI, ARM::PC);
639 case ARM::MOVi2pieces:
640 // Two instructions to materialize a constant.
641 emitMOVi2piecesInstruction(MI);
643 case ARM::LEApcrelJT:
644 // Materialize jumptable address.
645 emitLEApcrelJTInstruction(MI);
648 case ARM::MOVsrl_flag:
649 case ARM::MOVsra_flag:
650 emitPseudoMoveInstruction(MI);
655 template<class CodeEmitter>
656 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
657 const MachineInstr &MI,
658 const TargetInstrDesc &TID,
659 const MachineOperand &MO,
661 unsigned Binary = getMachineOpValue(MI, MO);
663 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
664 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
667 // Encode the shift opcode.
669 unsigned Rs = MO1.getReg();
671 // Set shift operand (bit[7:4]).
676 // RRX - 0110 and bit[11:8] clear.
678 default: LLVM_UNREACHABLE("Unknown shift opc!");
679 case ARM_AM::lsl: SBits = 0x1; break;
680 case ARM_AM::lsr: SBits = 0x3; break;
681 case ARM_AM::asr: SBits = 0x5; break;
682 case ARM_AM::ror: SBits = 0x7; break;
683 case ARM_AM::rrx: SBits = 0x6; break;
686 // Set shift operand (bit[6:4]).
692 default: LLVM_UNREACHABLE("Unknown shift opc!");
693 case ARM_AM::lsl: SBits = 0x0; break;
694 case ARM_AM::lsr: SBits = 0x2; break;
695 case ARM_AM::asr: SBits = 0x4; break;
696 case ARM_AM::ror: SBits = 0x6; break;
699 Binary |= SBits << 4;
700 if (SOpc == ARM_AM::rrx)
703 // Encode the shift operation Rs or shift_imm (except rrx).
705 // Encode Rs bit[11:8].
706 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
708 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
711 // Encode shift_imm bit[11:7].
712 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
715 template<class CodeEmitter>
716 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
717 // Encode rotate_imm.
718 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
719 << ARMII::SoRotImmShift;
722 Binary |= ARM_AM::getSOImmValImm(SoImm);
726 template<class CodeEmitter>
727 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
728 const TargetInstrDesc &TID) const {
729 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
730 const MachineOperand &MO = MI.getOperand(i-1);
731 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
732 return 1 << ARMII::S_BitShift;
737 template<class CodeEmitter>
738 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
739 const MachineInstr &MI,
741 unsigned ImplicitRn) {
742 const TargetInstrDesc &TID = MI.getDesc();
744 if (TID.Opcode == ARM::BFC) {
745 llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
748 // Part of binary is determined by TableGn.
749 unsigned Binary = getBinaryCodeForInstr(MI);
751 // Set the conditional execution predicate
752 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
754 // Encode S bit if MI modifies CPSR.
755 Binary |= getAddrModeSBit(MI, TID);
757 // Encode register def if there is one.
758 unsigned NumDefs = TID.getNumDefs();
761 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
763 // Special handling for implicit use (e.g. PC).
764 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
765 << ARMII::RegRdShift);
767 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
768 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
771 // Encode first non-shifter register operand if there is one.
772 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
775 // Special handling for implicit use (e.g. PC).
776 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
777 << ARMII::RegRnShift);
779 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
784 // Encode shifter operand.
785 const MachineOperand &MO = MI.getOperand(OpIdx);
786 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
788 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
793 // Encode register Rm.
794 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
799 Binary |= 1 << ARMII::I_BitShift;
800 Binary |= getMachineSoImmOpValue(MO.getImm());
805 template<class CodeEmitter>
806 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
807 const MachineInstr &MI,
809 unsigned ImplicitRn) {
810 const TargetInstrDesc &TID = MI.getDesc();
811 unsigned Form = TID.TSFlags & ARMII::FormMask;
812 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
814 // Part of binary is determined by TableGn.
815 unsigned Binary = getBinaryCodeForInstr(MI);
817 // Set the conditional execution predicate
818 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
822 // Operand 0 of a pre- and post-indexed store is the address base
823 // writeback. Skip it.
824 bool Skipped = false;
825 if (IsPrePost && Form == ARMII::StFrm) {
832 // Special handling for implicit use (e.g. PC).
833 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
834 << ARMII::RegRdShift);
836 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
838 // Set second operand
840 // Special handling for implicit use (e.g. PC).
841 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
842 << ARMII::RegRnShift);
844 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
846 // If this is a two-address operand, skip it. e.g. LDR_PRE.
847 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
850 const MachineOperand &MO2 = MI.getOperand(OpIdx);
851 unsigned AM2Opc = (ImplicitRn == ARM::PC)
852 ? 0 : MI.getOperand(OpIdx+1).getImm();
854 // Set bit U(23) according to sign of immed value (positive or negative).
855 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
857 if (!MO2.getReg()) { // is immediate
858 if (ARM_AM::getAM2Offset(AM2Opc))
859 // Set the value of offset_12 field
860 Binary |= ARM_AM::getAM2Offset(AM2Opc);
865 // Set bit I(25), because this is not in immediate enconding.
866 Binary |= 1 << ARMII::I_BitShift;
867 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
868 // Set bit[3:0] to the corresponding Rm register
869 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
871 // If this instr is in scaled register offset/index instruction, set
872 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
873 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
874 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
875 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
881 template<class CodeEmitter>
882 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
883 unsigned ImplicitRn) {
884 const TargetInstrDesc &TID = MI.getDesc();
885 unsigned Form = TID.TSFlags & ARMII::FormMask;
886 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
888 // Part of binary is determined by TableGn.
889 unsigned Binary = getBinaryCodeForInstr(MI);
891 // Set the conditional execution predicate
892 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
896 // Operand 0 of a pre- and post-indexed store is the address base
897 // writeback. Skip it.
898 bool Skipped = false;
899 if (IsPrePost && Form == ARMII::StMiscFrm) {
905 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
907 // Skip LDRD and STRD's second operand.
908 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
911 // Set second operand
913 // Special handling for implicit use (e.g. PC).
914 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
915 << ARMII::RegRnShift);
917 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
919 // If this is a two-address operand, skip it. e.g. LDRH_POST.
920 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
923 const MachineOperand &MO2 = MI.getOperand(OpIdx);
924 unsigned AM3Opc = (ImplicitRn == ARM::PC)
925 ? 0 : MI.getOperand(OpIdx+1).getImm();
927 // Set bit U(23) according to sign of immed value (positive or negative)
928 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
931 // If this instr is in register offset/index encoding, set bit[3:0]
932 // to the corresponding Rm register.
934 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
939 // This instr is in immediate offset/index encoding, set bit 22 to 1.
940 Binary |= 1 << ARMII::AM3_I_BitShift;
941 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
943 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
944 Binary |= (ImmOffs & 0xF); // immedL
950 static unsigned getAddrModeUPBits(unsigned Mode) {
953 // Set addressing mode by modifying bits U(23) and P(24)
954 // IA - Increment after - bit U = 1 and bit P = 0
955 // IB - Increment before - bit U = 1 and bit P = 1
956 // DA - Decrement after - bit U = 0 and bit P = 0
957 // DB - Decrement before - bit U = 0 and bit P = 1
959 default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
960 case ARM_AM::da: break;
961 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
962 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
963 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
969 template<class CodeEmitter>
970 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
971 const MachineInstr &MI) {
972 // Part of binary is determined by TableGn.
973 unsigned Binary = getBinaryCodeForInstr(MI);
975 // Set the conditional execution predicate
976 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
978 // Set base address operand
979 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
981 // Set addressing mode by modifying bits U(23) and P(24)
982 const MachineOperand &MO = MI.getOperand(1);
983 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
986 if (ARM_AM::getAM4WBFlag(MO.getImm()))
987 Binary |= 0x1 << ARMII::W_BitShift;
990 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
991 const MachineOperand &MO = MI.getOperand(i);
992 if (!MO.isReg() || MO.isImplicit())
994 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
995 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
997 Binary |= 0x1 << RegNum;
1003 template<class CodeEmitter>
1004 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1005 const TargetInstrDesc &TID = MI.getDesc();
1007 // Part of binary is determined by TableGn.
1008 unsigned Binary = getBinaryCodeForInstr(MI);
1010 // Set the conditional execution predicate
1011 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1013 // Encode S bit if MI modifies CPSR.
1014 Binary |= getAddrModeSBit(MI, TID);
1016 // 32x32->64bit operations have two destination registers. The number
1017 // of register definitions will tell us if that's what we're dealing with.
1019 if (TID.getNumDefs() == 2)
1020 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1023 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1026 Binary |= getMachineOpValue(MI, OpIdx++);
1029 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1031 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1032 // it as Rn (for multiply, that's in the same offset as RdLo.
1033 if (TID.getNumOperands() > OpIdx &&
1034 !TID.OpInfo[OpIdx].isPredicate() &&
1035 !TID.OpInfo[OpIdx].isOptionalDef())
1036 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1041 template<class CodeEmitter>
1042 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1043 const TargetInstrDesc &TID = MI.getDesc();
1045 // Part of binary is determined by TableGn.
1046 unsigned Binary = getBinaryCodeForInstr(MI);
1048 // Set the conditional execution predicate
1049 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1054 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1056 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1057 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1059 // Two register operand form.
1061 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1064 Binary |= getMachineOpValue(MI, MO2);
1067 Binary |= getMachineOpValue(MI, MO1);
1070 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1071 if (MI.getOperand(OpIdx).isImm() &&
1072 !TID.OpInfo[OpIdx].isPredicate() &&
1073 !TID.OpInfo[OpIdx].isOptionalDef())
1074 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1079 template<class CodeEmitter>
1080 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1081 const TargetInstrDesc &TID = MI.getDesc();
1083 // Part of binary is determined by TableGn.
1084 unsigned Binary = getBinaryCodeForInstr(MI);
1086 // Set the conditional execution predicate
1087 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1092 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1094 const MachineOperand &MO = MI.getOperand(OpIdx++);
1095 if (OpIdx == TID.getNumOperands() ||
1096 TID.OpInfo[OpIdx].isPredicate() ||
1097 TID.OpInfo[OpIdx].isOptionalDef()) {
1098 // Encode Rm and it's done.
1099 Binary |= getMachineOpValue(MI, MO);
1105 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1108 Binary |= getMachineOpValue(MI, OpIdx++);
1110 // Encode shift_imm.
1111 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1112 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1113 Binary |= ShiftAmt << ARMII::ShiftShift;
1118 template<class CodeEmitter>
1119 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1120 const TargetInstrDesc &TID = MI.getDesc();
1122 if (TID.Opcode == ARM::TPsoft)
1123 llvm_report_error("ARM::TPsoft FIXME"); // FIXME
1125 // Part of binary is determined by TableGn.
1126 unsigned Binary = getBinaryCodeForInstr(MI);
1128 // Set the conditional execution predicate
1129 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1131 // Set signed_immed_24 field
1132 Binary |= getMachineOpValue(MI, 0);
1137 template<class CodeEmitter>
1138 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1139 // Remember the base address of the inline jump table.
1140 uintptr_t JTBase = MCE.getCurrentPCValue();
1141 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1142 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1144 // Now emit the jump table entries.
1145 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1146 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1148 // DestBB address - JT base.
1149 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1151 // Absolute DestBB address.
1152 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1157 template<class CodeEmitter>
1158 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1159 const TargetInstrDesc &TID = MI.getDesc();
1161 // Handle jump tables.
1162 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1163 TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1164 // First emit a ldr pc, [] instruction.
1165 emitDataProcessingInstruction(MI, ARM::PC);
1167 // Then emit the inline jump table.
1169 (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1170 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1171 emitInlineJumpTable(JTIndex);
1173 } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1174 // First emit a ldr pc, [] instruction.
1175 emitLoadStoreInstruction(MI, ARM::PC);
1177 // Then emit the inline jump table.
1178 emitInlineJumpTable(MI.getOperand(3).getIndex());
1182 // Part of binary is determined by TableGn.
1183 unsigned Binary = getBinaryCodeForInstr(MI);
1185 // Set the conditional execution predicate
1186 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1188 if (TID.Opcode == ARM::BX_RET)
1189 // The return register is LR.
1190 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1192 // otherwise, set the return register
1193 Binary |= getMachineOpValue(MI, 0);
1198 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1199 unsigned RegD = MI.getOperand(OpIdx).getReg();
1200 unsigned Binary = 0;
1201 bool isSPVFP = false;
1202 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1204 Binary |= RegD << ARMII::RegRdShift;
1206 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1207 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1212 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1213 unsigned RegN = MI.getOperand(OpIdx).getReg();
1214 unsigned Binary = 0;
1215 bool isSPVFP = false;
1216 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1218 Binary |= RegN << ARMII::RegRnShift;
1220 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1221 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1226 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1227 unsigned RegM = MI.getOperand(OpIdx).getReg();
1228 unsigned Binary = 0;
1229 bool isSPVFP = false;
1230 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1234 Binary |= ((RegM & 0x1E) >> 1);
1235 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1240 template<class CodeEmitter>
1241 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1242 const TargetInstrDesc &TID = MI.getDesc();
1244 // Part of binary is determined by TableGn.
1245 unsigned Binary = getBinaryCodeForInstr(MI);
1247 // Set the conditional execution predicate
1248 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1251 assert((Binary & ARMII::D_BitShift) == 0 &&
1252 (Binary & ARMII::N_BitShift) == 0 &&
1253 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1256 Binary |= encodeVFPRd(MI, OpIdx++);
1258 // If this is a two-address operand, skip it, e.g. FMACD.
1259 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1263 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1264 Binary |= encodeVFPRn(MI, OpIdx++);
1266 if (OpIdx == TID.getNumOperands() ||
1267 TID.OpInfo[OpIdx].isPredicate() ||
1268 TID.OpInfo[OpIdx].isOptionalDef()) {
1269 // FCMPEZD etc. has only one operand.
1275 Binary |= encodeVFPRm(MI, OpIdx);
1280 template<class CodeEmitter>
1281 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1282 const MachineInstr &MI) {
1283 const TargetInstrDesc &TID = MI.getDesc();
1284 unsigned Form = TID.TSFlags & ARMII::FormMask;
1286 // Part of binary is determined by TableGn.
1287 unsigned Binary = getBinaryCodeForInstr(MI);
1289 // Set the conditional execution predicate
1290 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1294 case ARMII::VFPConv1Frm:
1295 case ARMII::VFPConv2Frm:
1296 case ARMII::VFPConv3Frm:
1298 Binary |= encodeVFPRd(MI, 0);
1300 case ARMII::VFPConv4Frm:
1302 Binary |= encodeVFPRn(MI, 0);
1304 case ARMII::VFPConv5Frm:
1306 Binary |= encodeVFPRm(MI, 0);
1312 case ARMII::VFPConv1Frm:
1314 Binary |= encodeVFPRm(MI, 1);
1316 case ARMII::VFPConv2Frm:
1317 case ARMII::VFPConv3Frm:
1319 Binary |= encodeVFPRn(MI, 1);
1321 case ARMII::VFPConv4Frm:
1322 case ARMII::VFPConv5Frm:
1324 Binary |= encodeVFPRd(MI, 1);
1328 if (Form == ARMII::VFPConv5Frm)
1330 Binary |= encodeVFPRn(MI, 2);
1331 else if (Form == ARMII::VFPConv3Frm)
1333 Binary |= encodeVFPRm(MI, 2);
1338 template<class CodeEmitter>
1339 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1340 // Part of binary is determined by TableGn.
1341 unsigned Binary = getBinaryCodeForInstr(MI);
1343 // Set the conditional execution predicate
1344 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1349 Binary |= encodeVFPRd(MI, OpIdx++);
1351 // Encode address base.
1352 const MachineOperand &Base = MI.getOperand(OpIdx++);
1353 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1355 // If there is a non-zero immediate offset, encode it.
1357 const MachineOperand &Offset = MI.getOperand(OpIdx);
1358 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1359 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1360 Binary |= 1 << ARMII::U_BitShift;
1367 // If immediate offset is omitted, default to +0.
1368 Binary |= 1 << ARMII::U_BitShift;
1373 template<class CodeEmitter>
1374 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1375 const MachineInstr &MI) {
1376 // Part of binary is determined by TableGn.
1377 unsigned Binary = getBinaryCodeForInstr(MI);
1379 // Set the conditional execution predicate
1380 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1382 // Set base address operand
1383 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1385 // Set addressing mode by modifying bits U(23) and P(24)
1386 const MachineOperand &MO = MI.getOperand(1);
1387 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1390 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1391 Binary |= 0x1 << ARMII::W_BitShift;
1393 // First register is encoded in Dd.
1394 Binary |= encodeVFPRd(MI, 4);
1396 // Number of registers are encoded in offset field.
1397 unsigned NumRegs = 1;
1398 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1399 const MachineOperand &MO = MI.getOperand(i);
1400 if (!MO.isReg() || MO.isImplicit())
1404 Binary |= NumRegs * 2;
1409 template<class CodeEmitter>
1410 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1411 // Part of binary is determined by TableGn.
1412 unsigned Binary = getBinaryCodeForInstr(MI);
1414 // Set the conditional execution predicate
1415 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1420 #include "ARMGenCodeEmitter.inc"