1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
22 #include "InstPrinter/ARMInstPrinter.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMMCExpr.h"
25 #include "llvm/ADT/SetVector.h"
26 #include "llvm/ADT/SmallString.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/IR/Type.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCInst.h"
41 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCObjectStreamer.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMBuildAttributes.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 void ARMAsmPrinter::EmitFunctionBodyEnd() {
61 // Make sure to terminate any constant pools that were at the end
65 InConstantPool = false;
66 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
69 void ARMAsmPrinter::EmitFunctionEntryLabel() {
70 if (AFI->isThumbFunction()) {
71 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
72 OutStreamer.EmitThumbFunc(CurrentFnSym);
75 OutStreamer.EmitLabel(CurrentFnSym);
78 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
80 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
81 assert(Size && "C++ constructor pointer had zero size!");
83 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
84 assert(GV && "C++ constructor pointer was not a GlobalValue!");
86 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
88 (Subtarget->isTargetELF()
89 ? MCSymbolRefExpr::VK_ARM_TARGET1
90 : MCSymbolRefExpr::VK_None),
93 OutStreamer.EmitValue(E, Size);
96 /// runOnMachineFunction - This uses the EmitInstruction()
97 /// method to print assembly for each instruction.
99 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
100 AFI = MF.getInfo<ARMFunctionInfo>();
101 MCP = MF.getConstantPool();
103 SetupMachineFunction(MF);
105 if (Subtarget->isTargetCOFF()) {
106 bool Internal = MF.getFunction()->hasInternalLinkage();
107 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
108 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
109 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
111 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
112 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
113 OutStreamer.EmitCOFFSymbolType(Type);
114 OutStreamer.EndCOFFSymbolDef();
117 // Have common code print out the function header with linkage info etc.
118 EmitFunctionHeader();
120 // Emit the rest of the function body.
123 // We didn't modify anything.
127 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
128 raw_ostream &O, const char *Modifier) {
129 const MachineOperand &MO = MI->getOperand(OpNum);
130 unsigned TF = MO.getTargetFlags();
132 switch (MO.getType()) {
133 default: llvm_unreachable("<unknown operand type>");
134 case MachineOperand::MO_Register: {
135 unsigned Reg = MO.getReg();
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 assert(!MO.getSubReg() && "Subregs should be eliminated!");
138 if(ARM::GPRPairRegClass.contains(Reg)) {
139 const MachineFunction &MF = *MI->getParent()->getParent();
140 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
141 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
143 O << ARMInstPrinter::getRegisterName(Reg);
146 case MachineOperand::MO_Immediate: {
147 int64_t Imm = MO.getImm();
149 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
150 (TF == ARMII::MO_LO16))
152 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
153 (TF == ARMII::MO_HI16))
158 case MachineOperand::MO_MachineBasicBlock:
159 O << *MO.getMBB()->getSymbol();
161 case MachineOperand::MO_GlobalAddress: {
162 const GlobalValue *GV = MO.getGlobal();
163 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
164 (TF & ARMII::MO_LO16))
166 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
167 (TF & ARMII::MO_HI16))
169 O << *GetARMGVSymbol(GV, TF);
171 printOffset(MO.getOffset(), O);
172 if (TF == ARMII::MO_PLT)
176 case MachineOperand::MO_ConstantPoolIndex:
177 O << *GetCPISymbol(MO.getIndex());
182 //===--------------------------------------------------------------------===//
184 MCSymbol *ARMAsmPrinter::
185 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
186 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
187 SmallString<60> Name;
188 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
189 << getFunctionNumber() << '_' << uid << '_' << uid2;
190 return OutContext.GetOrCreateSymbol(Name.str());
194 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
195 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
196 SmallString<60> Name;
197 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
198 << getFunctionNumber();
199 return OutContext.GetOrCreateSymbol(Name.str());
202 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
203 unsigned AsmVariant, const char *ExtraCode,
205 // Does this asm operand have a single letter operand modifier?
206 if (ExtraCode && ExtraCode[0]) {
207 if (ExtraCode[1] != 0) return true; // Unknown modifier.
209 switch (ExtraCode[0]) {
211 // See if this is a generic print operand
212 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
213 case 'a': // Print as a memory address.
214 if (MI->getOperand(OpNum).isReg()) {
216 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
221 case 'c': // Don't print "#" before an immediate operand.
222 if (!MI->getOperand(OpNum).isImm())
224 O << MI->getOperand(OpNum).getImm();
226 case 'P': // Print a VFP double precision register.
227 case 'q': // Print a NEON quad precision register.
228 printOperand(MI, OpNum, O);
230 case 'y': // Print a VFP single precision register as indexed double.
231 if (MI->getOperand(OpNum).isReg()) {
232 unsigned Reg = MI->getOperand(OpNum).getReg();
233 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
234 // Find the 'd' register that has this 's' register as a sub-register,
235 // and determine the lane number.
236 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
237 if (!ARM::DPRRegClass.contains(*SR))
239 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
240 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
245 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
246 if (!MI->getOperand(OpNum).isImm())
248 O << ~(MI->getOperand(OpNum).getImm());
250 case 'L': // The low 16 bits of an immediate constant.
251 if (!MI->getOperand(OpNum).isImm())
253 O << (MI->getOperand(OpNum).getImm() & 0xffff);
255 case 'M': { // A register range suitable for LDM/STM.
256 if (!MI->getOperand(OpNum).isReg())
258 const MachineOperand &MO = MI->getOperand(OpNum);
259 unsigned RegBegin = MO.getReg();
260 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
261 // already got the operands in registers that are operands to the
262 // inline asm statement.
264 if (ARM::GPRPairRegClass.contains(RegBegin)) {
265 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
266 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
267 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
268 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
270 O << ARMInstPrinter::getRegisterName(RegBegin);
272 // FIXME: The register allocator not only may not have given us the
273 // registers in sequence, but may not be in ascending registers. This
274 // will require changes in the register allocator that'll need to be
275 // propagated down here if the operands change.
276 unsigned RegOps = OpNum + 1;
277 while (MI->getOperand(RegOps).isReg()) {
279 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
287 case 'R': // The most significant register of a pair.
288 case 'Q': { // The least significant register of a pair.
291 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
292 if (!FlagsOP.isImm())
294 unsigned Flags = FlagsOP.getImm();
296 // This operand may not be the one that actually provides the register. If
297 // it's tied to a previous one then we should refer instead to that one
298 // for registers and their classes.
300 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
301 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
302 unsigned OpFlags = MI->getOperand(OpNum).getImm();
303 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
305 Flags = MI->getOperand(OpNum).getImm();
307 // Later code expects OpNum to be pointing at the register rather than
312 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
314 InlineAsm::hasRegClassConstraint(Flags, RC);
315 if (RC == ARM::GPRPairRegClassID) {
318 const MachineOperand &MO = MI->getOperand(OpNum);
321 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
322 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
323 ARM::gsub_0 : ARM::gsub_1);
324 O << ARMInstPrinter::getRegisterName(Reg);
329 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
330 if (RegOp >= MI->getNumOperands())
332 const MachineOperand &MO = MI->getOperand(RegOp);
335 unsigned Reg = MO.getReg();
336 O << ARMInstPrinter::getRegisterName(Reg);
340 case 'e': // The low doubleword register of a NEON quad register.
341 case 'f': { // The high doubleword register of a NEON quad register.
342 if (!MI->getOperand(OpNum).isReg())
344 unsigned Reg = MI->getOperand(OpNum).getReg();
345 if (!ARM::QPRRegClass.contains(Reg))
347 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
348 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
349 ARM::dsub_0 : ARM::dsub_1);
350 O << ARMInstPrinter::getRegisterName(SubReg);
354 // This modifier is not yet supported.
355 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
357 case 'H': { // The highest-numbered register of a pair.
358 const MachineOperand &MO = MI->getOperand(OpNum);
361 const MachineFunction &MF = *MI->getParent()->getParent();
362 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
363 unsigned Reg = MO.getReg();
364 if(!ARM::GPRPairRegClass.contains(Reg))
366 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
367 O << ARMInstPrinter::getRegisterName(Reg);
373 printOperand(MI, OpNum, O);
377 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
378 unsigned OpNum, unsigned AsmVariant,
379 const char *ExtraCode,
381 // Does this asm operand have a single letter operand modifier?
382 if (ExtraCode && ExtraCode[0]) {
383 if (ExtraCode[1] != 0) return true; // Unknown modifier.
385 switch (ExtraCode[0]) {
386 case 'A': // A memory operand for a VLD1/VST1 instruction.
387 default: return true; // Unknown modifier.
388 case 'm': // The base register of a memory operand.
389 if (!MI->getOperand(OpNum).isReg())
391 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 assert(MO.isReg() && "unexpected inline asm memory operand");
398 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
402 static bool isThumb(const MCSubtargetInfo& STI) {
403 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
406 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
407 const MCSubtargetInfo *EndInfo) const {
408 // If either end mode is unknown (EndInfo == NULL) or different than
409 // the start mode, then restore the start mode.
410 const bool WasThumb = isThumb(StartInfo);
411 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
412 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
416 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
417 if (Subtarget->isTargetMachO()) {
418 Reloc::Model RelocM = TM.getRelocationModel();
419 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
420 // Declare all the text sections up front (before the DWARF sections
421 // emitted by AsmPrinter::doInitialization) so the assembler will keep
422 // them together at the beginning of the object file. This helps
423 // avoid out-of-range branches that are due a fundamental limitation of
424 // the way symbol offsets are encoded with the current Darwin ARM
426 const TargetLoweringObjectFileMachO &TLOFMacho =
427 static_cast<const TargetLoweringObjectFileMachO &>(
428 getObjFileLowering());
430 // Collect the set of sections our functions will go into.
431 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
432 SmallPtrSet<const MCSection *, 8> > TextSections;
433 // Default text section comes first.
434 TextSections.insert(TLOFMacho.getTextSection());
435 // Now any user defined text sections from function attributes.
436 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
437 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
438 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
439 // Now the coalescable sections.
440 TextSections.insert(TLOFMacho.getTextCoalSection());
441 TextSections.insert(TLOFMacho.getConstTextCoalSection());
443 // Emit the sections in the .s file header to fix the order.
444 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
445 OutStreamer.SwitchSection(TextSections[i]);
447 if (RelocM == Reloc::DynamicNoPIC) {
448 const MCSection *sect =
449 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
450 MachO::S_SYMBOL_STUBS,
451 12, SectionKind::getText());
452 OutStreamer.SwitchSection(sect);
454 const MCSection *sect =
455 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
456 MachO::S_SYMBOL_STUBS,
457 16, SectionKind::getText());
458 OutStreamer.SwitchSection(sect);
460 const MCSection *StaticInitSect =
461 OutContext.getMachOSection("__TEXT", "__StaticInit",
463 MachO::S_ATTR_PURE_INSTRUCTIONS,
464 SectionKind::getText());
465 OutStreamer.SwitchSection(StaticInitSect);
468 // Compiling with debug info should not affect the code
469 // generation. Ensure the cstring section comes before the
470 // optional __DWARF secion. Otherwise, PC-relative loads would
471 // have to use different instruction sequences at "-g" in order to
472 // reach global data in the same object file.
473 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
476 // Use unified assembler syntax.
477 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
479 // Emit ARM Build Attributes
480 if (Subtarget->isTargetELF())
483 if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
484 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
488 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
489 MachineModuleInfoImpl::StubValueTy &MCSym) {
491 OutStreamer.EmitLabel(StubLabel);
492 // .indirect_symbol _foo
493 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
496 // External to current translation unit.
497 OutStreamer.EmitIntValue(0, 4/*size*/);
499 // Internal to current translation unit.
501 // When we place the LSDA into the TEXT section, the type info
502 // pointers need to be indirect and pc-rel. We accomplish this by
503 // using NLPs; however, sometimes the types are local to the file.
504 // We need to fill in the value for the NLP in those cases.
505 OutStreamer.EmitValue(
506 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetMachO()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
527 for (auto &Stub : Stubs)
528 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
531 OutStreamer.AddBlankLine();
534 Stubs = MMIMacho.GetHiddenGVStubList();
535 if (!Stubs.empty()) {
536 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539 for (auto &Stub : Stubs)
540 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
543 OutStreamer.AddBlankLine();
546 // Funny Darwin hack: This flag tells the linker that no global symbols
547 // contain code that falls through to other global symbols (e.g. the obvious
548 // implementation of multiple entry points). If this doesn't occur, the
549 // linker can safely perform dead code stripping. Since LLVM never
550 // generates code that does this, it is always safe to set.
551 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
554 // Emit a .data.rel section containing any stubs that were created.
555 if (Subtarget->isTargetELF()) {
556 const TargetLoweringObjectFileELF &TLOFELF =
557 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
559 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
561 // Output stubs for external and common global variables.
562 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
563 if (!Stubs.empty()) {
564 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
565 const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
567 for (auto &stub: Stubs) {
568 OutStreamer.EmitLabel(stub.first);
569 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
570 TD->getPointerSize(0));
577 //===----------------------------------------------------------------------===//
578 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
580 // The following seem like one-off assembler flags, but they actually need
581 // to appear in the .ARM.attributes section in ELF.
582 // Instead of subclassing the MCELFStreamer, we do the work here.
584 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
585 const ARMSubtarget *Subtarget) {
587 return ARMBuildAttrs::v5TEJ;
589 if (Subtarget->hasV8Ops())
590 return ARMBuildAttrs::v8;
591 else if (Subtarget->hasV7Ops()) {
592 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
593 return ARMBuildAttrs::v7E_M;
594 return ARMBuildAttrs::v7;
595 } else if (Subtarget->hasV6T2Ops())
596 return ARMBuildAttrs::v6T2;
597 else if (Subtarget->hasV6MOps())
598 return ARMBuildAttrs::v6S_M;
599 else if (Subtarget->hasV6Ops())
600 return ARMBuildAttrs::v6;
601 else if (Subtarget->hasV5TEOps())
602 return ARMBuildAttrs::v5TE;
603 else if (Subtarget->hasV5TOps())
604 return ARMBuildAttrs::v5T;
605 else if (Subtarget->hasV4TOps())
606 return ARMBuildAttrs::v4T;
608 return ARMBuildAttrs::v4;
611 void ARMAsmPrinter::emitAttributes() {
612 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
613 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
615 ATS.switchVendor("aeabi");
617 std::string CPUString = Subtarget->getCPUString();
619 // FIXME: remove krait check when GNU tools support krait cpu
620 if (CPUString != "generic" && CPUString != "krait")
621 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
623 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
624 getArchForCPU(CPUString, Subtarget));
626 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
627 // profile is not applicable (e.g. pre v7, or cross-profile code)".
628 if (Subtarget->hasV7Ops()) {
629 if (Subtarget->isAClass()) {
630 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
631 ARMBuildAttrs::ApplicationProfile);
632 } else if (Subtarget->isRClass()) {
633 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
634 ARMBuildAttrs::RealTimeProfile);
635 } else if (Subtarget->isMClass()) {
636 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
637 ARMBuildAttrs::MicroControllerProfile);
641 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
642 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
643 if (Subtarget->isThumb1Only()) {
644 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645 ARMBuildAttrs::Allowed);
646 } else if (Subtarget->hasThumb2()) {
647 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
648 ARMBuildAttrs::AllowThumb32);
651 if (Subtarget->hasNEON()) {
652 /* NEON is not exactly a VFP architecture, but GAS emit one of
653 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
654 if (Subtarget->hasFPARMv8()) {
655 if (Subtarget->hasCrypto())
656 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
658 ATS.emitFPU(ARM::NEON_FP_ARMV8);
660 else if (Subtarget->hasVFP4())
661 ATS.emitFPU(ARM::NEON_VFPV4);
663 ATS.emitFPU(ARM::NEON);
664 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
665 if (Subtarget->hasV8Ops())
666 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
667 ARMBuildAttrs::AllowNeonARMv8);
669 if (Subtarget->hasFPARMv8())
670 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
671 // FPU, but there are two different names for it depending on the CPU.
672 ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
673 else if (Subtarget->hasVFP4())
674 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
675 else if (Subtarget->hasVFP3())
676 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
677 else if (Subtarget->hasVFP2())
678 ATS.emitFPU(ARM::VFPV2);
681 if (TM.getRelocationModel() == Reloc::PIC_) {
682 // PIC specific attributes.
683 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
684 ARMBuildAttrs::AddressRWPCRel);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
686 ARMBuildAttrs::AddressROPCRel);
687 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
688 ARMBuildAttrs::AddressGOT);
690 // Allow direct addressing of imported data for all other relocation models.
691 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
692 ARMBuildAttrs::AddressDirect);
695 // Signal various FP modes.
696 if (!TM.Options.UnsafeFPMath) {
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
698 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
699 ARMBuildAttrs::Allowed);
702 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
703 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
704 ARMBuildAttrs::Allowed);
706 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
707 ARMBuildAttrs::AllowIEE754);
709 // FIXME: add more flags to ARMBuildAttributes.h
710 // 8-bytes alignment stuff.
711 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
712 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
714 // ABI_HardFP_use attribute to indicate single precision FP.
715 if (Subtarget->isFPOnlySP())
716 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
717 ARMBuildAttrs::HardFPSinglePrecision);
719 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
720 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
721 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
723 // FIXME: Should we signal R9 usage?
725 if (Subtarget->hasFP16())
726 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
728 if (Subtarget->hasMPExtension())
729 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
731 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
732 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
733 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
734 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
735 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
736 // otherwise, the default value (AllowDIVIfExists) applies.
737 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
738 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
741 if (const Module *SourceModule = MMI->getModule()) {
742 // ABI_PCS_wchar_t to indicate wchar_t width
743 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
744 if (auto WCharWidthValue = cast_or_null<ConstantInt>(
745 SourceModule->getModuleFlag("wchar_size"))) {
746 int WCharWidth = WCharWidthValue->getZExtValue();
747 assert((WCharWidth == 2 || WCharWidth == 4) &&
748 "wchar_t width must be 2 or 4 bytes");
749 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
752 // ABI_enum_size to indicate enum width
753 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
754 // (all enums contain a value needing 32 bits to encode).
755 if (auto EnumWidthValue = cast_or_null<ConstantInt>(
756 SourceModule->getModuleFlag("min_enum_size"))) {
757 int EnumWidth = EnumWidthValue->getZExtValue();
758 assert((EnumWidth == 1 || EnumWidth == 4) &&
759 "Minimum enum width must be 1 or 4 bytes");
760 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
761 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
766 // TODO: We currently only support either reserving the register, or treating
767 // it as another callee-saved register, but not as SB or a TLS pointer; It
768 // would instead be nicer to push this from the frontend as metadata, as we do
769 // for the wchar and enum size tags
770 if (Subtarget->isR9Reserved())
771 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
772 ARMBuildAttrs::R9Reserved);
774 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
775 ARMBuildAttrs::R9IsGPR);
777 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
778 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
779 ARMBuildAttrs::AllowTZVirtualization);
780 else if (Subtarget->hasTrustZone())
781 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
782 ARMBuildAttrs::AllowTZ);
783 else if (Subtarget->hasVirtualization())
784 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
785 ARMBuildAttrs::AllowVirtualization);
787 ATS.finishAttributeSection();
790 //===----------------------------------------------------------------------===//
792 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
793 unsigned LabelId, MCContext &Ctx) {
795 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
796 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
800 static MCSymbolRefExpr::VariantKind
801 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
803 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
804 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
805 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
806 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
807 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
808 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
810 llvm_unreachable("Invalid ARMCPModifier!");
813 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
814 unsigned char TargetFlags) {
815 if (Subtarget->isTargetMachO()) {
816 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
817 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
820 return getSymbol(GV);
822 // FIXME: Remove this when Darwin transition to @GOT like syntax.
823 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
824 MachineModuleInfoMachO &MMIMachO =
825 MMI->getObjFileInfo<MachineModuleInfoMachO>();
826 MachineModuleInfoImpl::StubValueTy &StubSym =
827 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
828 : MMIMachO.getGVStubEntry(MCSym);
829 if (!StubSym.getPointer())
830 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
831 !GV->hasInternalLinkage());
833 } else if (Subtarget->isTargetCOFF()) {
834 assert(Subtarget->isTargetWindows() &&
835 "Windows is the only supported COFF target");
837 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
839 return getSymbol(GV);
841 SmallString<128> Name;
843 getNameWithPrefix(Name, GV);
845 return OutContext.GetOrCreateSymbol(Name);
846 } else if (Subtarget->isTargetELF()) {
847 return getSymbol(GV);
849 llvm_unreachable("unexpected target");
853 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
854 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
856 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
858 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
861 if (ACPV->isLSDA()) {
862 SmallString<128> Str;
863 raw_svector_ostream OS(Str);
864 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
865 MCSym = OutContext.GetOrCreateSymbol(OS.str());
866 } else if (ACPV->isBlockAddress()) {
867 const BlockAddress *BA =
868 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
869 MCSym = GetBlockAddressSymbol(BA);
870 } else if (ACPV->isGlobalValue()) {
871 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
873 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
874 // flag the global as MO_NONLAZY.
875 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
876 MCSym = GetARMGVSymbol(GV, TF);
877 } else if (ACPV->isMachineBasicBlock()) {
878 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
879 MCSym = MBB->getSymbol();
881 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
882 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
883 MCSym = GetExternalSymbolSymbol(Sym);
886 // Create an MCSymbol for the reference.
888 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
891 if (ACPV->getPCAdjustment()) {
892 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
896 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
898 MCBinaryExpr::CreateAdd(PCRelExpr,
899 MCConstantExpr::Create(ACPV->getPCAdjustment(),
902 if (ACPV->mustAddCurrentAddress()) {
903 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
904 // label, so just emit a local label end reference that instead.
905 MCSymbol *DotSym = OutContext.CreateTempSymbol();
906 OutStreamer.EmitLabel(DotSym);
907 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
908 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
910 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
912 OutStreamer.EmitValue(Expr, Size);
915 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
916 unsigned Opcode = MI->getOpcode();
918 if (Opcode == ARM::BR_JTadd)
920 else if (Opcode == ARM::BR_JTm)
923 const MachineOperand &MO1 = MI->getOperand(OpNum);
924 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
925 unsigned JTI = MO1.getIndex();
927 // Emit a label for the jump table.
928 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
929 OutStreamer.EmitLabel(JTISymbol);
931 // Mark the jump table as data-in-code.
932 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
934 // Emit each entry of the table.
935 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
936 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
937 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
939 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
940 MachineBasicBlock *MBB = JTBBs[i];
941 // Construct an MCExpr for the entry. We want a value of the form:
942 // (BasicBlockAddr - TableBeginAddr)
944 // For example, a table with entries jumping to basic blocks BB0 and BB1
947 // .word (LBB0 - LJTI_0_0)
948 // .word (LBB1 - LJTI_0_0)
949 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
951 if (TM.getRelocationModel() == Reloc::PIC_)
952 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
955 // If we're generating a table of Thumb addresses in static relocation
956 // model, we need to add one to keep interworking correctly.
957 else if (AFI->isThumbFunction())
958 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
960 OutStreamer.EmitValue(Expr, 4);
962 // Mark the end of jump table data-in-code region.
963 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
966 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
967 unsigned Opcode = MI->getOpcode();
968 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
969 const MachineOperand &MO1 = MI->getOperand(OpNum);
970 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
971 unsigned JTI = MO1.getIndex();
973 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
974 OutStreamer.EmitLabel(JTISymbol);
976 // Emit each entry of the table.
977 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
978 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
979 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
980 unsigned OffsetWidth = 4;
981 if (MI->getOpcode() == ARM::t2TBB_JT) {
983 // Mark the jump table as data-in-code.
984 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
985 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
987 // Mark the jump table as data-in-code.
988 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
991 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
992 MachineBasicBlock *MBB = JTBBs[i];
993 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
995 // If this isn't a TBB or TBH, the entries are direct branch instructions.
996 if (OffsetWidth == 4) {
997 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
998 .addExpr(MBBSymbolExpr)
1003 // Otherwise it's an offset from the dispatch instruction. Construct an
1004 // MCExpr for the entry. We want a value of the form:
1005 // (BasicBlockAddr - TableBeginAddr) / 2
1007 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1010 // .byte (LBB0 - LJTI_0_0) / 2
1011 // .byte (LBB1 - LJTI_0_0) / 2
1012 const MCExpr *Expr =
1013 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1014 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1016 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1018 OutStreamer.EmitValue(Expr, OffsetWidth);
1020 // Mark the end of jump table data-in-code region. 32-bit offsets use
1021 // actual branch instructions here, so we don't mark those as a data-region
1023 if (OffsetWidth != 4)
1024 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1027 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1028 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1029 "Only instruction which are involved into frame setup code are allowed");
1031 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1032 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1033 const MachineFunction &MF = *MI->getParent()->getParent();
1034 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1035 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1037 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1038 unsigned Opc = MI->getOpcode();
1039 unsigned SrcReg, DstReg;
1041 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1042 // Two special cases:
1043 // 1) tPUSH does not have src/dst regs.
1044 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1045 // load. Yes, this is pretty fragile, but for now I don't see better
1047 SrcReg = DstReg = ARM::SP;
1049 SrcReg = MI->getOperand(1).getReg();
1050 DstReg = MI->getOperand(0).getReg();
1053 // Try to figure out the unwinding opcode out of src / dst regs.
1054 if (MI->mayStore()) {
1056 assert(DstReg == ARM::SP &&
1057 "Only stack pointer as a destination reg is supported");
1059 SmallVector<unsigned, 4> RegList;
1060 // Skip src & dst reg, and pred ops.
1061 unsigned StartOp = 2 + 2;
1062 // Use all the operands.
1063 unsigned NumOffset = 0;
1068 llvm_unreachable("Unsupported opcode for unwinding information");
1070 // Special case here: no src & dst reg, but two extra imp ops.
1071 StartOp = 2; NumOffset = 2;
1072 case ARM::STMDB_UPD:
1073 case ARM::t2STMDB_UPD:
1074 case ARM::VSTMDDB_UPD:
1075 assert(SrcReg == ARM::SP &&
1076 "Only stack pointer as a source reg is supported");
1077 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1079 const MachineOperand &MO = MI->getOperand(i);
1080 // Actually, there should never be any impdef stuff here. Skip it
1081 // temporary to workaround PR11902.
1082 if (MO.isImplicit())
1084 RegList.push_back(MO.getReg());
1087 case ARM::STR_PRE_IMM:
1088 case ARM::STR_PRE_REG:
1089 case ARM::t2STR_PRE:
1090 assert(MI->getOperand(2).getReg() == ARM::SP &&
1091 "Only stack pointer as a source reg is supported");
1092 RegList.push_back(SrcReg);
1095 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1096 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1098 // Changes of stack / frame pointer.
1099 if (SrcReg == ARM::SP) {
1104 llvm_unreachable("Unsupported opcode for unwinding information");
1110 Offset = -MI->getOperand(2).getImm();
1114 Offset = MI->getOperand(2).getImm();
1117 Offset = MI->getOperand(2).getImm()*4;
1121 Offset = -MI->getOperand(2).getImm()*4;
1123 case ARM::tLDRpci: {
1124 // Grab the constpool index and check, whether it corresponds to
1125 // original or cloned constpool entry.
1126 unsigned CPI = MI->getOperand(1).getIndex();
1127 const MachineConstantPool *MCP = MF.getConstantPool();
1128 if (CPI >= MCP->getConstants().size())
1129 CPI = AFI.getOriginalCPIdx(CPI);
1130 assert(CPI != -1U && "Invalid constpool index");
1132 // Derive the actual offset.
1133 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1134 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1135 // FIXME: Check for user, it should be "add" instruction!
1136 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1141 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1142 if (DstReg == FramePtr && FramePtr != ARM::SP)
1143 // Set-up of the frame pointer. Positive values correspond to "add"
1145 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1146 else if (DstReg == ARM::SP) {
1147 // Change of SP by an offset. Positive values correspond to "sub"
1149 ATS.emitPad(Offset);
1151 // Move of SP to a register. Positive values correspond to an "add"
1153 ATS.emitMovSP(DstReg, -Offset);
1156 } else if (DstReg == ARM::SP) {
1158 llvm_unreachable("Unsupported opcode for unwinding information");
1162 llvm_unreachable("Unsupported opcode for unwinding information");
1167 // Simple pseudo-instructions have their lowering (with expansion to real
1168 // instructions) auto-generated.
1169 #include "ARMGenMCPseudoLowering.inc"
1171 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1172 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
1174 // If we just ended a constant pool, mark it as such.
1175 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1176 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1177 InConstantPool = false;
1180 // Emit unwinding stuff for frame-related instructions
1181 if (Subtarget->isTargetEHABICompatible() &&
1182 MI->getFlag(MachineInstr::FrameSetup))
1183 EmitUnwindingInstruction(MI);
1185 // Do any auto-generated pseudo lowerings.
1186 if (emitPseudoExpansionLowering(OutStreamer, MI))
1189 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1190 "Pseudo flag setting opcode should be expanded early");
1192 // Check for manual lowerings.
1193 unsigned Opc = MI->getOpcode();
1195 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1196 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1198 case ARM::tLEApcrel:
1199 case ARM::t2LEApcrel: {
1200 // FIXME: Need to also handle globals and externals
1201 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1202 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1203 ARM::t2LEApcrel ? ARM::t2ADR
1204 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1206 .addReg(MI->getOperand(0).getReg())
1207 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1208 // Add predicate operands.
1209 .addImm(MI->getOperand(2).getImm())
1210 .addReg(MI->getOperand(3).getReg()));
1213 case ARM::LEApcrelJT:
1214 case ARM::tLEApcrelJT:
1215 case ARM::t2LEApcrelJT: {
1216 MCSymbol *JTIPICSymbol =
1217 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1218 MI->getOperand(2).getImm());
1219 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1220 ARM::t2LEApcrelJT ? ARM::t2ADR
1221 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1223 .addReg(MI->getOperand(0).getReg())
1224 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1225 // Add predicate operands.
1226 .addImm(MI->getOperand(3).getImm())
1227 .addReg(MI->getOperand(4).getReg()));
1230 // Darwin call instructions are just normal call instructions with different
1231 // clobber semantics (they clobber R9).
1232 case ARM::BX_CALL: {
1233 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1236 // Add predicate operands.
1239 // Add 's' bit operand (always reg0 for this)
1242 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1243 .addReg(MI->getOperand(0).getReg()));
1246 case ARM::tBX_CALL: {
1247 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1250 // Add predicate operands.
1254 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1255 .addReg(MI->getOperand(0).getReg())
1256 // Add predicate operands.
1261 case ARM::BMOVPCRX_CALL: {
1262 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1265 // Add predicate operands.
1268 // Add 's' bit operand (always reg0 for this)
1271 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1273 .addReg(MI->getOperand(0).getReg())
1274 // Add predicate operands.
1277 // Add 's' bit operand (always reg0 for this)
1281 case ARM::BMOVPCB_CALL: {
1282 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1285 // Add predicate operands.
1288 // Add 's' bit operand (always reg0 for this)
1291 const MachineOperand &Op = MI->getOperand(0);
1292 const GlobalValue *GV = Op.getGlobal();
1293 const unsigned TF = Op.getTargetFlags();
1294 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1295 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1296 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1298 // Add predicate operands.
1303 case ARM::MOVi16_ga_pcrel:
1304 case ARM::t2MOVi16_ga_pcrel: {
1306 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1307 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1309 unsigned TF = MI->getOperand(1).getTargetFlags();
1310 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1311 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1312 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1314 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1315 getFunctionNumber(),
1316 MI->getOperand(2).getImm(), OutContext);
1317 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1318 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1319 const MCExpr *PCRelExpr =
1320 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1321 MCBinaryExpr::CreateAdd(LabelSymExpr,
1322 MCConstantExpr::Create(PCAdj, OutContext),
1323 OutContext), OutContext), OutContext);
1324 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1326 // Add predicate operands.
1327 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1328 TmpInst.addOperand(MCOperand::CreateReg(0));
1329 // Add 's' bit operand (always reg0 for this)
1330 TmpInst.addOperand(MCOperand::CreateReg(0));
1331 EmitToStreamer(OutStreamer, TmpInst);
1334 case ARM::MOVTi16_ga_pcrel:
1335 case ARM::t2MOVTi16_ga_pcrel: {
1337 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1338 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1339 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1342 unsigned TF = MI->getOperand(2).getTargetFlags();
1343 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1344 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1345 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1347 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1348 getFunctionNumber(),
1349 MI->getOperand(3).getImm(), OutContext);
1350 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1351 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1352 const MCExpr *PCRelExpr =
1353 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1354 MCBinaryExpr::CreateAdd(LabelSymExpr,
1355 MCConstantExpr::Create(PCAdj, OutContext),
1356 OutContext), OutContext), OutContext);
1357 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1358 // Add predicate operands.
1359 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1360 TmpInst.addOperand(MCOperand::CreateReg(0));
1361 // Add 's' bit operand (always reg0 for this)
1362 TmpInst.addOperand(MCOperand::CreateReg(0));
1363 EmitToStreamer(OutStreamer, TmpInst);
1366 case ARM::tPICADD: {
1367 // This is a pseudo op for a label + instruction sequence, which looks like:
1370 // This adds the address of LPC0 to r0.
1373 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1374 getFunctionNumber(), MI->getOperand(2).getImm(),
1377 // Form and emit the add.
1378 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1379 .addReg(MI->getOperand(0).getReg())
1380 .addReg(MI->getOperand(0).getReg())
1382 // Add predicate operands.
1388 // This is a pseudo op for a label + instruction sequence, which looks like:
1391 // This adds the address of LPC0 to r0.
1394 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1395 getFunctionNumber(), MI->getOperand(2).getImm(),
1398 // Form and emit the add.
1399 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1400 .addReg(MI->getOperand(0).getReg())
1402 .addReg(MI->getOperand(1).getReg())
1403 // Add predicate operands.
1404 .addImm(MI->getOperand(3).getImm())
1405 .addReg(MI->getOperand(4).getReg())
1406 // Add 's' bit operand (always reg0 for this)
1417 case ARM::PICLDRSH: {
1418 // This is a pseudo op for a label + instruction sequence, which looks like:
1421 // The LCP0 label is referenced by a constant pool entry in order to get
1422 // a PC-relative address at the ldr instruction.
1425 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1426 getFunctionNumber(), MI->getOperand(2).getImm(),
1429 // Form and emit the load
1431 switch (MI->getOpcode()) {
1433 llvm_unreachable("Unexpected opcode!");
1434 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1435 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1436 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1437 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1438 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1439 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1440 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1441 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1443 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1444 .addReg(MI->getOperand(0).getReg())
1446 .addReg(MI->getOperand(1).getReg())
1448 // Add predicate operands.
1449 .addImm(MI->getOperand(3).getImm())
1450 .addReg(MI->getOperand(4).getReg()));
1454 case ARM::CONSTPOOL_ENTRY: {
1455 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1456 /// in the function. The first operand is the ID# for this instruction, the
1457 /// second is the index into the MachineConstantPool that this is, the third
1458 /// is the size in bytes of this constant pool entry.
1459 /// The required alignment is specified on the basic block holding this MI.
1460 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1461 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1463 // If this is the first entry of the pool, mark it.
1464 if (!InConstantPool) {
1465 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1466 InConstantPool = true;
1469 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1471 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1472 if (MCPE.isMachineConstantPoolEntry())
1473 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1475 EmitGlobalConstant(MCPE.Val.ConstVal);
1478 case ARM::t2BR_JT: {
1479 // Lower and emit the instruction itself, then the jump table following it.
1480 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1482 .addReg(MI->getOperand(0).getReg())
1483 // Add predicate operands.
1487 // Output the data for the jump table itself
1491 case ARM::t2TBB_JT: {
1492 // Lower and emit the instruction itself, then the jump table following it.
1493 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1495 .addReg(MI->getOperand(0).getReg())
1496 // Add predicate operands.
1500 // Output the data for the jump table itself
1502 // Make sure the next instruction is 2-byte aligned.
1506 case ARM::t2TBH_JT: {
1507 // Lower and emit the instruction itself, then the jump table following it.
1508 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1510 .addReg(MI->getOperand(0).getReg())
1511 // Add predicate operands.
1515 // Output the data for the jump table itself
1521 // Lower and emit the instruction itself, then the jump table following it.
1524 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1525 ARM::MOVr : ARM::tMOVr;
1526 TmpInst.setOpcode(Opc);
1527 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1528 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1529 // Add predicate operands.
1530 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1531 TmpInst.addOperand(MCOperand::CreateReg(0));
1532 // Add 's' bit operand (always reg0 for this)
1533 if (Opc == ARM::MOVr)
1534 TmpInst.addOperand(MCOperand::CreateReg(0));
1535 EmitToStreamer(OutStreamer, TmpInst);
1537 // Make sure the Thumb jump table is 4-byte aligned.
1538 if (Opc == ARM::tMOVr)
1541 // Output the data for the jump table itself
1546 // Lower and emit the instruction itself, then the jump table following it.
1549 if (MI->getOperand(1).getReg() == 0) {
1551 TmpInst.setOpcode(ARM::LDRi12);
1552 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1553 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1554 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1556 TmpInst.setOpcode(ARM::LDRrs);
1557 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1558 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1559 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1560 TmpInst.addOperand(MCOperand::CreateImm(0));
1562 // Add predicate operands.
1563 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1564 TmpInst.addOperand(MCOperand::CreateReg(0));
1565 EmitToStreamer(OutStreamer, TmpInst);
1567 // Output the data for the jump table itself
1571 case ARM::BR_JTadd: {
1572 // Lower and emit the instruction itself, then the jump table following it.
1573 // add pc, target, idx
1574 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1576 .addReg(MI->getOperand(0).getReg())
1577 .addReg(MI->getOperand(1).getReg())
1578 // Add predicate operands.
1581 // Add 's' bit operand (always reg0 for this)
1584 // Output the data for the jump table itself
1589 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1590 // FIXME: Remove this special case when they do.
1591 if (!Subtarget->isTargetMachO()) {
1592 //.long 0xe7ffdefe @ trap
1593 uint32_t Val = 0xe7ffdefeUL;
1594 OutStreamer.AddComment("trap");
1595 OutStreamer.EmitIntValue(Val, 4);
1600 case ARM::TRAPNaCl: {
1601 //.long 0xe7fedef0 @ trap
1602 uint32_t Val = 0xe7fedef0UL;
1603 OutStreamer.AddComment("trap");
1604 OutStreamer.EmitIntValue(Val, 4);
1608 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1609 // FIXME: Remove this special case when they do.
1610 if (!Subtarget->isTargetMachO()) {
1611 //.short 57086 @ trap
1612 uint16_t Val = 0xdefe;
1613 OutStreamer.AddComment("trap");
1614 OutStreamer.EmitIntValue(Val, 2);
1619 case ARM::t2Int_eh_sjlj_setjmp:
1620 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1621 case ARM::tInt_eh_sjlj_setjmp: {
1622 // Two incoming args: GPR:$src, GPR:$val
1625 // str $val, [$src, #4]
1630 unsigned SrcReg = MI->getOperand(0).getReg();
1631 unsigned ValReg = MI->getOperand(1).getReg();
1632 MCSymbol *Label = GetARMSJLJEHLabel();
1633 OutStreamer.AddComment("eh_setjmp begin");
1634 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1641 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1651 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1654 // The offset immediate is #4. The operand value is scaled by 4 for the
1655 // tSTR instruction.
1661 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1669 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1670 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1671 .addExpr(SymbolExpr)
1675 OutStreamer.AddComment("eh_setjmp end");
1676 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1684 OutStreamer.EmitLabel(Label);
1688 case ARM::Int_eh_sjlj_setjmp_nofp:
1689 case ARM::Int_eh_sjlj_setjmp: {
1690 // Two incoming args: GPR:$src, GPR:$val
1692 // str $val, [$src, #+4]
1696 unsigned SrcReg = MI->getOperand(0).getReg();
1697 unsigned ValReg = MI->getOperand(1).getReg();
1699 OutStreamer.AddComment("eh_setjmp begin");
1700 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1707 // 's' bit operand (always reg0 for this).
1710 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1718 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1724 // 's' bit operand (always reg0 for this).
1727 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1734 // 's' bit operand (always reg0 for this).
1737 OutStreamer.AddComment("eh_setjmp end");
1738 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1744 // 's' bit operand (always reg0 for this).
1748 case ARM::Int_eh_sjlj_longjmp: {
1749 // ldr sp, [$src, #8]
1750 // ldr $scratch, [$src, #4]
1753 unsigned SrcReg = MI->getOperand(0).getReg();
1754 unsigned ScratchReg = MI->getOperand(1).getReg();
1755 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1763 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1771 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1779 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1786 case ARM::tInt_eh_sjlj_longjmp: {
1787 // ldr $scratch, [$src, #8]
1789 // ldr $scratch, [$src, #4]
1792 unsigned SrcReg = MI->getOperand(0).getReg();
1793 unsigned ScratchReg = MI->getOperand(1).getReg();
1794 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1797 // The offset immediate is #8. The operand value is scaled by 4 for the
1798 // tLDR instruction.
1804 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1811 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1819 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1827 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1837 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1839 EmitToStreamer(OutStreamer, TmpInst);
1842 //===----------------------------------------------------------------------===//
1843 // Target Registry Stuff
1844 //===----------------------------------------------------------------------===//
1846 // Force static initialization.
1847 extern "C" void LLVMInitializeARMAsmPrinter() {
1848 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1849 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1850 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1851 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);