lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19
  20 //===----------------------------------------------------------------------===//
  21 // ARM Subtarget features.
  22 //
  23
  24 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  25                                    "Enable VFP2 instructions">;
  26 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  27                                    "Enable VFP3 instructions">;
  28 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  29                                    "Enable NEON instructions">;
  30 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  31                                      "Enable Thumb2 instructions">;
  32 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  33                                      "Does not support ARM mode execution">;
  34 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  35                                      "Enable half-precision floating point">;
  36 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  37                                      "Restrict VFP3 to 16 double registers">;
  38 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  39                                      "Enable divide instructions">;
  40 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  41                                  "Enable Thumb2 extract and pack instructions">;
  42 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  43                                    "Has data barrier (dmb / dsb) instructions">;
  44 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  45                                          "FP compare + branch is slow">;
  46 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  47                           "Floating point unit supports single precision only">;
  48
  49 // Some processors have FP multiply-accumulate instructions that don't
  50 // play nicely with other VFP / NEON instructions, and it's generally better
  51 // to just not use them.
  52 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  53                                          "Disable VFP / NEON MAC instructions">;
  54
  55 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  56 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  57                                        "HasVMLxForwarding", "true",
  58                                        "Has multiplier accumulator forwarding">;
  59
  60 // Some processors benefit from using NEON instructions for scalar
  61 // single-precision FP operations.
  62 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  63                                         "true",
  64                                         "Use NEON for single precision FP">;
  65
  66 // Disable 32-bit to 16-bit narrowing for experimentation.
  67 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  68                                              "Prefer 32-bit Thumb instrs">;
  69
  70 /// Some instructions update CPSR partially, which can add false dependency for
  71 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  72 /// mapped to a separate physical register. Avoid partial CPSR update for these
  73 /// processors.
  74 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  75                                                "AvoidCPSRPartialUpdate", "true",
  76                                  "Avoid CPSR partial update for OOO execution">;
  77
  78 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
  79 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
  80                                  "Supports v7 DSP instructions in Thumb2.">;
  81
  82 // Multiprocessing extension.
  83 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
  84                                  "Supports Multiprocessing extension">;
  85
  86 // ARM architectures.
  87 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  88                                    "ARM v4T">;
  89 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  90                                    "ARM v5T">;
  91 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  92                                    "ARM v5TE, v5TEj, v5TExp">;
  93 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  94                                    "ARM v6">;
  95 def ArchV6M     : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
  96                                    "ARM v6m",
  97                                    [FeatureNoARM, FeatureDB]>;
  98 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
  99                                    "ARM v6t2",
 100                                    [FeatureThumb2, FeatureDSPThumb2]>;
 101 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
 102                                    "ARM v7A",
 103                                    [FeatureThumb2, FeatureNEON, FeatureDB,
 104                                     FeatureDSPThumb2]>;
 105 def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
 106                                    "ARM v7M",
 107                                    [FeatureThumb2, FeatureNoARM, FeatureDB,
 108                                     FeatureHWDiv]>;
 109 def ArchV7EM    : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
 110                                    "ARM v7E-M",
 111                                    [FeatureThumb2, FeatureNoARM, FeatureDB,
 112                                     FeatureHWDiv, FeatureDSPThumb2,
 113                                     FeatureT2XtPk]>;
 114
 115 //===----------------------------------------------------------------------===//
 116 // ARM Processors supported.
 117 //
 118
 119 include "ARMSchedule.td"
 120
 121 // ARM processor families.
 122 def ProcOthers  : SubtargetFeature<"others", "ARMProcFamily", "Others",
 123                                    "One of the other ARM processor families">;
 124 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 125                                    "Cortex-A8 ARM processors",
 126                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 127                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 128                                     FeatureT2XtPk]>;
 129 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 130                                    "Cortex-A9 ARM processors",
 131                                    [FeatureVMLxForwarding,
 132                                     FeatureT2XtPk, FeatureFP16,
 133                                     FeatureAvoidPartialCPSR]>;
 134
 135 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 136  : Processor<Name, GenericItineraries, Features>;
 137
 138 // V4 Processors.
 139 def : ProcNoItin<"generic",         []>;
 140 def : ProcNoItin<"arm8",            []>;
 141 def : ProcNoItin<"arm810",          []>;
 142 def : ProcNoItin<"strongarm",       []>;
 143 def : ProcNoItin<"strongarm110",    []>;
 144 def : ProcNoItin<"strongarm1100",   []>;
 145 def : ProcNoItin<"strongarm1110",   []>;
 146
 147 // V4T Processors.
 148 def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
 149 def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
 150 def : ProcNoItin<"arm710t",         [ArchV4T]>;
 151 def : ProcNoItin<"arm720t",         [ArchV4T]>;
 152 def : ProcNoItin<"arm9",            [ArchV4T]>;
 153 def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
 154 def : ProcNoItin<"arm920",          [ArchV4T]>;
 155 def : ProcNoItin<"arm920t",         [ArchV4T]>;
 156 def : ProcNoItin<"arm922t",         [ArchV4T]>;
 157 def : ProcNoItin<"arm940t",         [ArchV4T]>;
 158 def : ProcNoItin<"ep9312",          [ArchV4T]>;
 159
 160 // V5T Processors.
 161 def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
 162 def : ProcNoItin<"arm1020t",        [ArchV5T]>;
 163
 164 // V5TE Processors.
 165 def : ProcNoItin<"arm9e",           [ArchV5TE]>;
 166 def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
 167 def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
 168 def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
 169 def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
 170 def : ProcNoItin<"arm10e",          [ArchV5TE]>;
 171 def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
 172 def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
 173 def : ProcNoItin<"xscale",          [ArchV5TE]>;
 174 def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
 175
 176 // V6 Processors.
 177 def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
 178 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
 179                                                        FeatureHasSlowFPVMLx]>;
 180 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
 181 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2,
 182                                                        FeatureHasSlowFPVMLx]>;
 183 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
 184 def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2,
 185                                                        FeatureHasSlowFPVMLx]>;
 186
 187 // V6M Processors.
 188 def : Processor<"cortex-m0",        ARMV6Itineraries, [ArchV6M]>;
 189
 190 // V6T2 Processors.
 191 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [ArchV6T2]>;
 192 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
 193                                                        FeatureHasSlowFPVMLx]>;
 194
 195 // V7 Processors.
 196 def : Processor<"cortex-a8",        CortexA8Itineraries,
 197                                     [ArchV7A, ProcA8]>;
 198 def : Processor<"cortex-a9",        CortexA9Itineraries,
 199                                     [ArchV7A, ProcA9]>;
 200 def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
 201                                     [ArchV7A, ProcA9, FeatureMP]>;
 202
 203 // V7M Processors.
 204 def : ProcNoItin<"cortex-m3",       [ArchV7M]>;
 205 def : ProcNoItin<"cortex-m4",       [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
 206
 207 //===----------------------------------------------------------------------===//
 208 // Register File Description
 209 //===----------------------------------------------------------------------===//
 210
 211 include "ARMRegisterInfo.td"
 212
 213 include "ARMCallingConv.td"
 214
 215 //===----------------------------------------------------------------------===//
 216 // Instruction Descriptions
 217 //===----------------------------------------------------------------------===//
 218
 219 include "ARMInstrInfo.td"
 220
 221 def ARMInstrInfo : InstrInfo;
 222
 223
 224 //===----------------------------------------------------------------------===//
 225 // Assembly printer
 226 //===----------------------------------------------------------------------===//
 227 // ARM Uses the MC printer for asm output, so make sure the TableGen
 228 // AsmWriter bits get associated with the correct class.
 229 def ARMAsmWriter : AsmWriter {
 230   string AsmWriterClassName  = "InstPrinter";
 231   bit isMCAsmWriter = 1;
 232 }
 233
 234 //===----------------------------------------------------------------------===//
 235 // Declare the target which we are implementing
 236 //===----------------------------------------------------------------------===//
 237
 238 def ARM : Target {
 239   // Pull in Instruction Info:
 240   let InstructionSet = ARMInstrInfo;
 241
 242   let AssemblyWriters = [ARMAsmWriter];
 243 }