1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // ARM Subtarget features.
24 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
25 "Enable VFP2 instructions">;
26 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
27 "Enable VFP3 instructions">;
28 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
29 "Enable NEON instructions">;
30 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
31 "Enable Thumb2 instructions">;
32 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
33 "Does not support ARM mode execution">;
34 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
35 "Enable half-precision floating point">;
36 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
37 "Enable divide instructions">;
38 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
39 "Enable Thumb2 extract and pack instructions">;
40 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
41 "Has data barrier (dmb / dsb) instructions">;
42 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
43 "FP compare + branch is slow">;
44 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
45 "Floating point unit supports single precision only">;
47 // Some processors have multiply-accumulate instructions that don't
48 // play nicely with other VFP instructions, and it's generally better
49 // to just not use them.
50 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
51 // others as well. We should do more benchmarking and confirm one way or
53 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
54 "Disable VFP MAC instructions">;
55 // Some processors benefit from using NEON instructions for scalar
56 // single-precision FP operations.
57 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
59 "Use NEON for single precision FP">;
61 // Disable 32-bit to 16-bit narrowing for experimentation.
62 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
63 "Prefer 32-bit Thumb instrs">;
67 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
69 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
71 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
72 "ARM v5TE, v5TEj, v5TExp">;
73 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
75 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
77 [FeatureNoARM, FeatureDB]>;
78 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
81 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
83 [FeatureThumb2, FeatureNEON, FeatureDB]>;
84 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
86 [FeatureThumb2, FeatureNoARM, FeatureDB,
89 //===----------------------------------------------------------------------===//
90 // ARM Processors supported.
93 include "ARMSchedule.td"
95 // ARM processor families.
96 def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
97 "One of the other ARM processor families">;
98 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
99 "Cortex-A8 ARM processors",
100 [FeatureSlowFPBrcc, FeatureNEONForFP]>;
101 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
102 "Cortex-A9 ARM processors">;
104 class ProcNoItin<string Name, list<SubtargetFeature> Features>
105 : Processor<Name, GenericItineraries, Features>;
108 def : ProcNoItin<"generic", []>;
109 def : ProcNoItin<"arm8", []>;
110 def : ProcNoItin<"arm810", []>;
111 def : ProcNoItin<"strongarm", []>;
112 def : ProcNoItin<"strongarm110", []>;
113 def : ProcNoItin<"strongarm1100", []>;
114 def : ProcNoItin<"strongarm1110", []>;
117 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
118 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
119 def : ProcNoItin<"arm710t", [ArchV4T]>;
120 def : ProcNoItin<"arm720t", [ArchV4T]>;
121 def : ProcNoItin<"arm9", [ArchV4T]>;
122 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
123 def : ProcNoItin<"arm920", [ArchV4T]>;
124 def : ProcNoItin<"arm920t", [ArchV4T]>;
125 def : ProcNoItin<"arm922t", [ArchV4T]>;
126 def : ProcNoItin<"arm940t", [ArchV4T]>;
127 def : ProcNoItin<"ep9312", [ArchV4T]>;
130 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
131 def : ProcNoItin<"arm1020t", [ArchV5T]>;
134 def : ProcNoItin<"arm9e", [ArchV5TE]>;
135 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
136 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
137 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
138 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
139 def : ProcNoItin<"arm10e", [ArchV5TE]>;
140 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
141 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
142 def : ProcNoItin<"xscale", [ArchV5TE]>;
143 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
146 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
147 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
148 FeatureHasSlowVMLx]>;
149 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
150 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
151 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
152 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
155 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
158 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
159 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
162 def : Processor<"cortex-a8", CortexA8Itineraries,
164 FeatureHasSlowVMLx, FeatureT2XtPk]>;
165 def : Processor<"cortex-a9", CortexA9Itineraries,
166 [ArchV7A, ProcA9, FeatureT2XtPk]>;
169 def : ProcNoItin<"cortex-m3", [ArchV7M]>;
170 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
172 //===----------------------------------------------------------------------===//
173 // Register File Description
174 //===----------------------------------------------------------------------===//
176 include "ARMRegisterInfo.td"
178 include "ARMCallingConv.td"
180 //===----------------------------------------------------------------------===//
181 // Instruction Descriptions
182 //===----------------------------------------------------------------------===//
184 include "ARMInstrInfo.td"
186 def ARMInstrInfo : InstrInfo;
189 //===----------------------------------------------------------------------===//
191 //===----------------------------------------------------------------------===//
192 // ARM Uses the MC printer for asm output, so make sure the TableGen
193 // AsmWriter bits get associated with the correct class.
194 def ARMAsmWriter : AsmWriter {
195 string AsmWriterClassName = "InstPrinter";
196 bit isMCAsmWriter = 1;
199 //===----------------------------------------------------------------------===//
200 // Declare the target which we are implementing
201 //===----------------------------------------------------------------------===//
204 // Pull in Instruction Info:
205 let InstructionSet = ARMInstrInfo;
207 let AssemblyWriters = [ARMAsmWriter];