1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71 "Enable support for Cryptography extensions",
74 // Some processors have FP multiply-accumulate instructions that don't
75 // play nicely with other VFP / NEON instructions, and it's generally better
76 // to just not use them.
77 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
78 "Disable VFP / NEON MAC instructions">;
80 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
81 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
82 "HasVMLxForwarding", "true",
83 "Has multiplier accumulator forwarding">;
85 // Some processors benefit from using NEON instructions for scalar
86 // single-precision FP operations.
87 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
89 "Use NEON for single precision FP">;
91 // Disable 32-bit to 16-bit narrowing for experimentation.
92 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
93 "Prefer 32-bit Thumb instrs">;
95 /// Some instructions update CPSR partially, which can add false dependency for
96 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
97 /// mapped to a separate physical register. Avoid partial CPSR update for these
99 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
100 "AvoidCPSRPartialUpdate", "true",
101 "Avoid CPSR partial update for OOO execution">;
103 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
104 "AvoidMOVsShifterOperand", "true",
105 "Avoid movs instructions with shifter operand">;
107 // Some processors perform return stack prediction. CodeGen should avoid issue
108 // "normal" call instructions to callees which do not return.
109 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
110 "Has return address stack">;
112 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
113 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
114 "Supports v7 DSP instructions in Thumb2">;
116 // Multiprocessing extension.
117 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
118 "Supports Multiprocessing extension">;
121 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
122 "Is microcontroller profile ('M' series)">;
125 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
126 "Is realtime profile ('R' series)">;
129 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
130 "Is application profile ('A' series)">;
132 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
133 // See ARMInstrInfo.td for details.
134 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
138 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
139 "Support ARM v4T instructions">;
140 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
141 "Support ARM v5T instructions",
143 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
144 "Support ARM v5TE, v5TEj, and v5TExp instructions",
146 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
147 "Support ARM v6 instructions",
149 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
150 "Support ARM v6M instructions",
152 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
153 "Support ARM v6t2 instructions",
154 [HasV6MOps, FeatureThumb2]>;
155 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
156 "Support ARM v7 instructions",
157 [HasV6T2Ops, FeaturePerfMon]>;
158 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
159 "Support ARM v8 instructions",
162 //===----------------------------------------------------------------------===//
163 // ARM Processors supported.
166 include "ARMSchedule.td"
168 // ARM processor families.
169 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
170 "Cortex-A5 ARM processors",
171 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
172 FeatureVMLxForwarding, FeatureT2XtPk,
174 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
175 "Cortex-A8 ARM processors",
176 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
177 FeatureVMLxForwarding, FeatureT2XtPk,
179 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
180 "Cortex-A9 ARM processors",
181 [FeatureVMLxForwarding,
182 FeatureT2XtPk, FeatureFP16,
183 FeatureAvoidPartialCPSR,
185 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
186 "Swift ARM processors",
187 [FeatureNEONForFP, FeatureT2XtPk,
188 FeatureVFP4, FeatureMP, FeatureHWDiv,
189 FeatureHWDivARM, FeatureAvoidPartialCPSR,
190 FeatureAvoidMOVsShOp,
191 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
193 // FIXME: It has not been determined if A15 has these features.
194 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
195 "Cortex-A15 ARM processors",
196 [FeatureT2XtPk, FeatureVFP4,
197 FeatureAvoidPartialCPSR,
200 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
201 "Cortex-A53 ARM processors",
202 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
203 FeatureTrustZone, FeatureT2XtPk,
206 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
207 "Cortex-A57 ARM processors",
208 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
209 FeatureTrustZone, FeatureT2XtPk,
212 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
213 "Cortex-R5 ARM processors",
215 FeatureHWDiv, FeatureHWDivARM,
216 FeatureHasSlowFPVMLx,
217 FeatureAvoidPartialCPSR,
220 class ProcNoItin<string Name, list<SubtargetFeature> Features>
221 : Processor<Name, NoItineraries, Features>;
224 def : ProcNoItin<"generic", []>;
225 def : ProcNoItin<"arm8", []>;
226 def : ProcNoItin<"arm810", []>;
227 def : ProcNoItin<"strongarm", []>;
228 def : ProcNoItin<"strongarm110", []>;
229 def : ProcNoItin<"strongarm1100", []>;
230 def : ProcNoItin<"strongarm1110", []>;
233 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
234 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
235 def : ProcNoItin<"arm710t", [HasV4TOps]>;
236 def : ProcNoItin<"arm720t", [HasV4TOps]>;
237 def : ProcNoItin<"arm9", [HasV4TOps]>;
238 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
239 def : ProcNoItin<"arm920", [HasV4TOps]>;
240 def : ProcNoItin<"arm920t", [HasV4TOps]>;
241 def : ProcNoItin<"arm922t", [HasV4TOps]>;
242 def : ProcNoItin<"arm940t", [HasV4TOps]>;
243 def : ProcNoItin<"ep9312", [HasV4TOps]>;
246 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
247 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
250 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
251 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
252 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
253 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
254 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
255 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
256 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
257 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
258 def : ProcNoItin<"xscale", [HasV5TEOps]>;
259 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
262 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
263 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
264 FeatureHasSlowFPVMLx]>;
265 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
266 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
267 FeatureHasSlowFPVMLx]>;
268 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
269 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
270 FeatureHasSlowFPVMLx]>;
273 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
274 FeatureDB, FeatureMClass]>;
277 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
279 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
280 FeatureHasSlowFPVMLx,
284 // FIXME: A5 has currently the same Schedule model as A8
285 def : ProcessorModel<"cortex-a5", CortexA8Model,
286 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
287 FeatureVFP4, FeatureDSPThumb2,
288 FeatureHasRAS, FeatureAClass]>;
289 def : ProcessorModel<"cortex-a8", CortexA8Model,
290 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
291 FeatureDSPThumb2, FeatureHasRAS,
293 def : ProcessorModel<"cortex-a9", CortexA9Model,
294 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
295 FeatureDSPThumb2, FeatureHasRAS,
297 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
298 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
299 FeatureDSPThumb2, FeatureMP,
300 FeatureHasRAS, FeatureAClass]>;
301 // FIXME: A15 has currently the same ProcessorModel as A9.
302 def : ProcessorModel<"cortex-a15", CortexA9Model,
303 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
304 FeatureDSPThumb2, FeatureHasRAS,
306 // FIXME: R5 has currently the same ProcessorModel as A8.
307 def : ProcessorModel<"cortex-r5", CortexA8Model,
308 [ProcR5, HasV7Ops, FeatureDB,
309 FeatureVFP3, FeatureDSPThumb2,
310 FeatureHasRAS, FeatureVFPOnlySP,
314 def : ProcNoItin<"cortex-m3", [HasV7Ops,
315 FeatureThumb2, FeatureNoARM, FeatureDB,
316 FeatureHWDiv, FeatureMClass]>;
319 def : ProcNoItin<"cortex-m4", [HasV7Ops,
320 FeatureThumb2, FeatureNoARM, FeatureDB,
321 FeatureHWDiv, FeatureDSPThumb2,
322 FeatureT2XtPk, FeatureVFP4,
323 FeatureVFPOnlySP, FeatureMClass]>;
325 // Swift uArch Processors.
326 def : ProcessorModel<"swift", SwiftModel,
327 [ProcSwift, HasV7Ops, FeatureNEON,
328 FeatureDB, FeatureDSPThumb2,
329 FeatureHasRAS, FeatureAClass]>;
332 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
333 FeatureDB, FeatureFPARMv8,
334 FeatureNEON, FeatureDSPThumb2]>;
335 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
336 FeatureDB, FeatureFPARMv8,
337 FeatureNEON, FeatureDSPThumb2]>;
339 //===----------------------------------------------------------------------===//
340 // Register File Description
341 //===----------------------------------------------------------------------===//
343 include "ARMRegisterInfo.td"
345 include "ARMCallingConv.td"
347 //===----------------------------------------------------------------------===//
348 // Instruction Descriptions
349 //===----------------------------------------------------------------------===//
351 include "ARMInstrInfo.td"
353 def ARMInstrInfo : InstrInfo;
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
359 // ARM Uses the MC printer for asm output, so make sure the TableGen
360 // AsmWriter bits get associated with the correct class.
361 def ARMAsmWriter : AsmWriter {
362 string AsmWriterClassName = "InstPrinter";
363 bit isMCAsmWriter = 1;
366 //===----------------------------------------------------------------------===//
367 // Declare the target which we are implementing
368 //===----------------------------------------------------------------------===//
371 // Pull in Instruction Info:
372 let InstructionSet = ARMInstrInfo;
374 let AssemblyWriters = [ARMAsmWriter];