lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Helper classes.
  21 //
  22
  23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  24  : Processor<Name, NoItineraries, Features>;
  25
  26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
  27   : SubtargetFeature<fname, "ARMArch", aname,
  28                      !strconcat(aname, " architecture"), features>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget state.
  32 //
  33
  34 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  35                                   "Thumb mode">;
  36
  37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  38                                      "Use software floating point features.">;
  39
  40 //===----------------------------------------------------------------------===//
  41 // ARM Subtarget features.
  42 //
  43
  44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  45                                    "Enable VFP2 instructions">;
  46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  47                                    "Enable VFP3 instructions",
  48                                    [FeatureVFP2]>;
  49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  50                                    "Enable NEON instructions",
  51                                    [FeatureVFP3]>;
  52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  53                                      "Enable Thumb2 instructions">;
  54 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  55                                      "Does not support ARM mode execution",
  56                                      [ModeThumb]>;
  57 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  58                                      "Enable half-precision floating point">;
  59 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  60                                      "Enable VFP4 instructions",
  61                                      [FeatureVFP3, FeatureFP16]>;
  62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  63                                    "true", "Enable ARMv8 FP",
  64                                    [FeatureVFP4]>;
  65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  66                                        "Enable full half-precision floating point",
  67                                        [FeatureFPARMv8]>;
  68 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  69                                      "Restrict FP to 16 double registers">;
  70 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  71                                      "Enable divide instructions">;
  72 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  73                                         "HasHardwareDivideInARM", "true",
  74                                       "Enable divide instructions in ARM mode">;
  75 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  76                                  "Enable Thumb2 extract and pack instructions">;
  77 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  78                                    "Has data barrier (dmb / dsb) instructions">;
  79 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  80                                          "FP compare + branch is slow">;
  81 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  82                           "Floating point unit supports single precision only">;
  83 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  84                            "Enable support for Performance Monitor extensions">;
  85 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  86                           "Enable support for TrustZone security extensions">;
  87 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  88                           "Enable support for Cryptography extensions",
  89                           [FeatureNEON]>;
  90 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  91                           "Enable support for CRC instructions">;
  92
  93 // Cyclone has preferred instructions for zeroing VFP registers, which can
  94 // execute in 0 cycles.
  95 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  96                                         "Has zero-cycle zeroing instructions">;
  97
  98 // Some processors have FP multiply-accumulate instructions that don't
  99 // play nicely with other VFP / NEON instructions, and it's generally better
 100 // to just not use them.
 101 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 102                                          "Disable VFP / NEON MAC instructions">;
 103
 104 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 105 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 106                                        "HasVMLxForwarding", "true",
 107                                        "Has multiplier accumulator forwarding">;
 108
 109 // Some processors benefit from using NEON instructions for scalar
 110 // single-precision FP operations.
 111 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
 112                                         "true",
 113                                         "Use NEON for single precision FP">;
 114
 115 // Disable 32-bit to 16-bit narrowing for experimentation.
 116 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 117                                              "Prefer 32-bit Thumb instrs">;
 118
 119 /// Some instructions update CPSR partially, which can add false dependency for
 120 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 121 /// mapped to a separate physical register. Avoid partial CPSR update for these
 122 /// processors.
 123 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 124                                                "AvoidCPSRPartialUpdate", "true",
 125                                  "Avoid CPSR partial update for OOO execution">;
 126
 127 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 128                                             "AvoidMOVsShifterOperand", "true",
 129                                 "Avoid movs instructions with shifter operand">;
 130
 131 // Some processors perform return stack prediction. CodeGen should avoid issue
 132 // "normal" call instructions to callees which do not return.
 133 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
 134                                      "Has return address stack">;
 135
 136 /// DSP extension.
 137 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
 138                               "Supports DSP instructions in ARM and/or Thumb2">;
 139
 140 // Multiprocessing extension.
 141 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 142                                  "Supports Multiprocessing extension">;
 143
 144 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 145 def FeatureVirtualization : SubtargetFeature<"virtualization",
 146                                  "HasVirtualization", "true",
 147                                  "Supports Virtualization extension",
 148                                  [FeatureHWDiv, FeatureHWDivARM]>;
 149
 150 // M-series ISA
 151 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 152                                      "Is microcontroller profile ('M' series)">;
 153
 154 // R-series ISA
 155 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 156                                      "Is realtime profile ('R' series)">;
 157
 158 // A-series ISA
 159 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 160                                      "Is application profile ('A' series)">;
 161
 162 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 163 // See ARMInstrInfo.td for details.
 164 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 165                                        "NaCl trap">;
 166
 167 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 168                                           "StrictAlign", "true",
 169                                           "Disallow all unaligned memory "
 170                                           "access">;
 171
 172 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 173                                         "Generate calls via indirect call "
 174                                         "instructions">;
 175
 176 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 177                                         "Reserve R9, making it unavailable as "
 178                                         "GPR">;
 179
 180 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
 181                                      "Don't use movt/movw pairs for 32-bit "
 182                                      "imms">;
 183
 184
 185 //===----------------------------------------------------------------------===//
 186 // ARM ISAa.
 187 //
 188
 189 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 190                                    "Support ARM v4T instructions">;
 191 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 192                                    "Support ARM v5T instructions",
 193                                    [HasV4TOps]>;
 194 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 195                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 196                                    [HasV5TOps]>;
 197 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 198                                    "Support ARM v6 instructions",
 199                                    [HasV5TEOps]>;
 200 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 201                                    "Support ARM v6M instructions",
 202                                    [HasV6Ops]>;
 203 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 204                                    "Support ARM v6k instructions",
 205                                    [HasV6Ops]>;
 206 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 207                                    "Support ARM v6t2 instructions",
 208                                    [HasV6MOps, HasV6KOps, FeatureThumb2]>;
 209 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 210                                    "Support ARM v7 instructions",
 211                                    [HasV6T2Ops, FeaturePerfMon]>;
 212 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 213                                    "Support ARM v8 instructions",
 214                                    [HasV7Ops]>;
 215 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 216                                    "Support ARM v8.1a instructions",
 217                                    [HasV8Ops]>;
 218 def HasV8_2aOps   : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 219                                    "Support ARM v8.2a instructions",
 220                                    [HasV8_1aOps]>;
 221
 222
 223 //===----------------------------------------------------------------------===//
 224 // ARM Processor subtarget features.
 225 //
 226
 227 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 228                                    "Cortex-A5 ARM processors", []>;
 229 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 230                                    "Cortex-A7 ARM processors", []>;
 231 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 232                                    "Cortex-A8 ARM processors", []>;
 233 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 234                                    "Cortex-A9 ARM processors", []>;
 235 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 236                                    "Cortex-A12 ARM processors", []>;
 237 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 238                                    "Cortex-A15 ARM processors", []>;
 239 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 240                                    "Cortex-A17 ARM processors", []>;
 241 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 242                                    "Cortex-A53 ARM processors", []>;
 243 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 244                                    "Cortex-A57 ARM processors", []>;
 245 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 246                                    "Cortex-A72 ARM processors", []>;
 247
 248 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 249                                    "Qualcomm ARM processors", []>;
 250 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 251                                    "Swift ARM processors", []>;
 252
 253
 254 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 255                                     "Cortex-R4 ARM processors", []>;
 256 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 257                                    "Cortex-R5 ARM processors", []>;
 258 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 259                                    "Cortex-R7 ARM processors", []>;
 260
 261
 262 //===----------------------------------------------------------------------===//
 263 // ARM schedules.
 264 //
 265
 266 include "ARMSchedule.td"
 267
 268
 269 //===----------------------------------------------------------------------===//
 270 // ARM architectures
 271 //
 272
 273 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 274
 275 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 276
 277 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 278
 279 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 280
 281 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 282
 283 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 284
 285 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 286
 287 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 288
 289 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 290
 291 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 292
 293 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 294                                                        FeatureDSP]>;
 295
 296 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 297
 298 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 299                                                        FeatureTrustZone]>;
 300
 301 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 302                                                        FeatureNoARM,
 303                                                        FeatureDB,
 304                                                        FeatureMClass]>;
 305
 306 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 307                                                        FeatureNoARM,
 308                                                        FeatureDB,
 309                                                        FeatureMClass]>;
 310
 311 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 312                                                        FeatureNEON,
 313                                                        FeatureDB,
 314                                                        FeatureDSP,
 315                                                        FeatureAClass]>;
 316
 317 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 318                                                        FeatureDB,
 319                                                        FeatureDSP,
 320                                                        FeatureHWDiv,
 321                                                        FeatureRClass]>;
 322
 323 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 324                                                        FeatureThumb2,
 325                                                        FeatureNoARM,
 326                                                        FeatureDB,
 327                                                        FeatureHWDiv,
 328                                                        FeatureMClass]>;
 329
 330 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 331                                                        FeatureThumb2,
 332                                                        FeatureNoARM,
 333                                                        FeatureDB,
 334                                                        FeatureHWDiv,
 335                                                        FeatureMClass,
 336                                                        FeatureDSP,
 337                                                        FeatureT2XtPk]>;
 338
 339 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 340                                                        FeatureAClass,
 341                                                        FeatureDB,
 342                                                        FeatureFPARMv8,
 343                                                        FeatureNEON,
 344                                                        FeatureDSP,
 345                                                        FeatureTrustZone,
 346                                                        FeatureMP,
 347                                                        FeatureVirtualization,
 348                                                        FeatureCrypto,
 349                                                        FeatureCRC]>;
 350
 351 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 352                                                        FeatureAClass,
 353                                                        FeatureDB,
 354                                                        FeatureFPARMv8,
 355                                                        FeatureNEON,
 356                                                        FeatureDSP,
 357                                                        FeatureTrustZone,
 358                                                        FeatureMP,
 359                                                        FeatureVirtualization,
 360                                                        FeatureCrypto,
 361                                                        FeatureCRC]>;
 362
 363 // Aliases
 364 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 365 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 366 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 367 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 368 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 369 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 370
 371
 372 //===----------------------------------------------------------------------===//
 373 // ARM processors
 374 //
 375
 376 // Dummy CPU, used to target architectures
 377 def : ProcNoItin<"generic",                             []>;
 378
 379 def : ProcNoItin<"arm8",                                [ARMv4]>;
 380 def : ProcNoItin<"arm810",                              [ARMv4]>;
 381 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 382 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 383 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 384 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 385
 386 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 387 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 388 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 389 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 390 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 391 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 392 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 393 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 394 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 395 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 396 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 397
 398 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 399 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 400
 401 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 402 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 403 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 404 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 405 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 406 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 407 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 408 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 409 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 410 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 411
 412 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 413 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 414                                                          FeatureVFP2,
 415                                                          FeatureHasSlowFPVMLx]>;
 416
 417 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 418 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 419 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 420 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 421
 422 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 423 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 424                                                          FeatureVFP2,
 425                                                          FeatureHasSlowFPVMLx]>;
 426
 427 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 428 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 429                                                          FeatureVFP2,
 430                                                          FeatureHasSlowFPVMLx]>;
 431
 432 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 433 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 434                                                          FeatureVFP2,
 435                                                          FeatureHasSlowFPVMLx]>;
 436
 437 // FIXME: A5 has currently the same Schedule model as A8
 438 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 439                                                          FeatureHasRAS,
 440                                                          FeatureTrustZone,
 441                                                          FeatureSlowFPBrcc,
 442                                                          FeatureHasSlowFPVMLx,
 443                                                          FeatureVMLxForwarding,
 444                                                          FeatureT2XtPk,
 445                                                          FeatureMP,
 446                                                          FeatureVFP4]>;
 447
 448 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 449                                                          FeatureHasRAS,
 450                                                          FeatureTrustZone,
 451                                                          FeatureSlowFPBrcc,
 452                                                          FeatureHasSlowFPVMLx,
 453                                                          FeatureVMLxForwarding,
 454                                                          FeatureT2XtPk,
 455                                                          FeatureMP,
 456                                                          FeatureVFP4,
 457                                                          FeatureHWDiv,
 458                                                          FeatureHWDivARM,
 459                                                          FeatureVirtualization]>;
 460
 461 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 462                                                          FeatureHasRAS,
 463                                                          FeatureTrustZone,
 464                                                          FeatureSlowFPBrcc,
 465                                                          FeatureHasSlowFPVMLx,
 466                                                          FeatureVMLxForwarding,
 467                                                          FeatureT2XtPk]>;
 468
 469 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 470                                                          FeatureHasRAS,
 471                                                          FeatureTrustZone,
 472                                                          FeatureVMLxForwarding,
 473                                                          FeatureT2XtPk,
 474                                                          FeatureFP16,
 475                                                          FeatureAvoidPartialCPSR,
 476                                                          FeatureMP]>;
 477
 478 // FIXME: A12 has currently the same Schedule model as A9
 479 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 480                                                          FeatureHasRAS,
 481                                                          FeatureTrustZone,
 482                                                          FeatureVMLxForwarding,
 483                                                          FeatureT2XtPk,
 484                                                          FeatureVFP4,
 485                                                          FeatureHWDiv,
 486                                                          FeatureHWDivARM,
 487                                                          FeatureAvoidPartialCPSR,
 488                                                          FeatureVirtualization,
 489                                                          FeatureMP]>;
 490
 491 // FIXME: A15 has currently the same Schedule model as A9.
 492 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 493                                                          FeatureHasRAS,
 494                                                          FeatureTrustZone,
 495                                                          FeatureT2XtPk,
 496                                                          FeatureVFP4,
 497                                                          FeatureMP,
 498                                                          FeatureHWDiv,
 499                                                          FeatureHWDivARM,
 500                                                          FeatureAvoidPartialCPSR,
 501                                                          FeatureVirtualization]>;
 502
 503 // FIXME: A17 has currently the same Schedule model as A9
 504 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 505                                                          FeatureHasRAS,
 506                                                          FeatureTrustZone,
 507                                                          FeatureMP,
 508                                                          FeatureVMLxForwarding,
 509                                                          FeatureT2XtPk,
 510                                                          FeatureVFP4,
 511                                                          FeatureHWDiv,
 512                                                          FeatureHWDivARM,
 513                                                          FeatureAvoidPartialCPSR,
 514                                                          FeatureVirtualization]>;
 515
 516 // FIXME: krait has currently the same Schedule model as A9
 517 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 518 //        division features.
 519 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 520                                                          FeatureHasRAS,
 521                                                          FeatureVMLxForwarding,
 522                                                          FeatureT2XtPk,
 523                                                          FeatureFP16,
 524                                                          FeatureAvoidPartialCPSR,
 525                                                          FeatureVFP4,
 526                                                          FeatureHWDiv,
 527                                                          FeatureHWDivARM]>;
 528
 529 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 530                                                          FeatureHasRAS,
 531                                                          FeatureNEONForFP,
 532                                                          FeatureT2XtPk,
 533                                                          FeatureVFP4,
 534                                                          FeatureMP,
 535                                                          FeatureHWDiv,
 536                                                          FeatureHWDivARM,
 537                                                          FeatureAvoidPartialCPSR,
 538                                                          FeatureAvoidMOVsShOp,
 539                                                          FeatureHasSlowFPVMLx]>;
 540
 541 // FIXME: R4 has currently the same ProcessorModel as A8.
 542 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 543                                                          FeatureHasRAS,
 544                                                          FeatureAvoidPartialCPSR,
 545                                                          FeatureT2XtPk]>;
 546
 547 // FIXME: R4F has currently the same ProcessorModel as A8.
 548 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 549                                                          FeatureHasRAS,
 550                                                          FeatureSlowFPBrcc,
 551                                                          FeatureHasSlowFPVMLx,
 552                                                          FeatureVFP3,
 553                                                          FeatureD16,
 554                                                          FeatureAvoidPartialCPSR,
 555                                                          FeatureT2XtPk]>;
 556
 557 // FIXME: R5 has currently the same ProcessorModel as A8.
 558 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 559                                                          FeatureHasRAS,
 560                                                          FeatureVFP3,
 561                                                          FeatureD16,
 562                                                          FeatureSlowFPBrcc,
 563                                                          FeatureHWDivARM,
 564                                                          FeatureHasSlowFPVMLx,
 565                                                          FeatureAvoidPartialCPSR,
 566                                                          FeatureT2XtPk]>;
 567
 568 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 569 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 570                                                          FeatureHasRAS,
 571                                                          FeatureVFP3,
 572                                                          FeatureVFPOnlySP,
 573                                                          FeatureD16,
 574                                                          FeatureMP,
 575                                                          FeatureSlowFPBrcc,
 576                                                          FeatureHWDivARM,
 577                                                          FeatureHasSlowFPVMLx,
 578                                                          FeatureAvoidPartialCPSR,
 579                                                          FeatureT2XtPk]>;
 580
 581 def : ProcNoItin<"cortex-m3",                           [ARMv7m]>;
 582 def : ProcNoItin<"sc300",                               [ARMv7m]>;
 583
 584 def : ProcNoItin<"cortex-m4",                           [ARMv7em,
 585                                                          FeatureVFP4,
 586                                                          FeatureVFPOnlySP,
 587                                                          FeatureD16]>;
 588
 589 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 590                                                          FeatureFPARMv8,
 591                                                          FeatureD16]>;
 592
 593
 594 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 595                                                          FeatureHWDiv,
 596                                                          FeatureHWDivARM,
 597                                                          FeatureT2XtPk,
 598                                                          FeatureCrypto,
 599                                                          FeatureCRC]>;
 600
 601 def : ProcNoItin<"cortex-a57",                          [ARMv8a, ProcA57,
 602                                                          FeatureHWDiv,
 603                                                          FeatureHWDivARM,
 604                                                          FeatureT2XtPk,
 605                                                          FeatureCrypto,
 606                                                          FeatureCRC]>;
 607
 608 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 609                                                          FeatureHWDiv,
 610                                                          FeatureHWDivARM,
 611                                                          FeatureT2XtPk,
 612                                                          FeatureCrypto,
 613                                                          FeatureCRC]>;
 614
 615 // Cyclone is very similar to swift
 616 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 617                                                          FeatureHasRAS,
 618                                                          FeatureNEONForFP,
 619                                                          FeatureT2XtPk,
 620                                                          FeatureVFP4,
 621                                                          FeatureMP,
 622                                                          FeatureHWDiv,
 623                                                          FeatureHWDivARM,
 624                                                          FeatureAvoidPartialCPSR,
 625                                                          FeatureAvoidMOVsShOp,
 626                                                          FeatureHasSlowFPVMLx,
 627                                                          FeatureCrypto,
 628                                                          FeatureZCZeroing]>;
 629
 630
 631 //===----------------------------------------------------------------------===//
 632 // Register File Description
 633 //===----------------------------------------------------------------------===//
 634
 635 include "ARMRegisterInfo.td"
 636
 637 include "ARMCallingConv.td"
 638
 639 //===----------------------------------------------------------------------===//
 640 // Instruction Descriptions
 641 //===----------------------------------------------------------------------===//
 642
 643 include "ARMInstrInfo.td"
 644
 645 def ARMInstrInfo : InstrInfo;
 646
 647 //===----------------------------------------------------------------------===//
 648 // Declare the target which we are implementing
 649 //===----------------------------------------------------------------------===//
 650
 651 def ARMAsmWriter : AsmWriter {
 652   string AsmWriterClassName  = "InstPrinter";
 653   int PassSubtarget = 1;
 654   int Variant = 0;
 655   bit isMCAsmWriter = 1;
 656 }
 657
 658 def ARMAsmParserVariant : AsmParserVariant {
 659   int Variant = 0;
 660   string Name = "ARM";
 661   string BreakCharacters = ".";
 662 }
 663
 664 def ARM : Target {
 665   // Pull in Instruction Info:
 666   let InstructionSet = ARMInstrInfo;
 667   let AssemblyWriters = [ARMAsmWriter];
 668   let AssemblyParserVariants = [ARMAsmParserVariant];
 669 }