lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

   1 //===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 #include "AMDGPUBaseInfo.h"
  10 #include "AMDGPU.h"
  11 #include "llvm/IR/GlobalValue.h"
  12 #include "llvm/MC/MCContext.h"
  13 #include "llvm/MC/MCSectionELF.h"
  14 #include "llvm/MC/SubtargetFeature.h"
  15
  16 #define GET_SUBTARGETINFO_ENUM
  17 #include "AMDGPUGenSubtargetInfo.inc"
  18 #undef GET_SUBTARGETINFO_ENUM
  19
  20 namespace llvm {
  21 namespace AMDGPU {
  22
  23 IsaVersion getIsaVersion(const FeatureBitset &Features) {
  24
  25   if (Features.test(FeatureISAVersion7_0_0))
  26     return {7, 0, 0};
  27
  28   if (Features.test(FeatureISAVersion7_0_1))
  29     return {7, 0, 1};
  30
  31   if (Features.test(FeatureISAVersion8_0_0))
  32     return {8, 0, 0};
  33
  34   if (Features.test(FeatureISAVersion8_0_1))
  35     return {8, 0, 1};
  36
  37   return {0, 0, 0};
  38 }
  39
  40 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
  41                                const FeatureBitset &Features) {
  42
  43   IsaVersion ISA = getIsaVersion(Features);
  44
  45   memset(&Header, 0, sizeof(Header));
  46
  47   Header.amd_kernel_code_version_major = 1;
  48   Header.amd_kernel_code_version_minor = 0;
  49   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
  50   Header.amd_machine_version_major = ISA.Major;
  51   Header.amd_machine_version_minor = ISA.Minor;
  52   Header.amd_machine_version_stepping = ISA.Stepping;
  53   Header.kernel_code_entry_byte_offset = sizeof(Header);
  54   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
  55   Header.wavefront_size = 6;
  56   // These alignment values are specified in powers of two, so alignment =
  57   // 2^n.  The minimum alignment is 2^4 = 16.
  58   Header.kernarg_segment_alignment = 4;
  59   Header.group_segment_alignment = 4;
  60   Header.private_segment_alignment = 4;
  61 }
  62
  63 MCSection *getHSATextSection(MCContext &Ctx) {
  64   return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
  65                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
  66                            ELF::SHF_EXECINSTR |
  67                            ELF::SHF_AMDGPU_HSA_AGENT |
  68                            ELF::SHF_AMDGPU_HSA_CODE);
  69 }
  70
  71 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
  72   return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
  73                            ELF::SHF_ALLOC | ELF::SHF_WRITE |
  74                            ELF::SHF_AMDGPU_HSA_GLOBAL |
  75                            ELF::SHF_AMDGPU_HSA_AGENT);
  76 }
  77
  78 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
  79   return  Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
  80                             ELF::SHF_ALLOC | ELF::SHF_WRITE |
  81                             ELF::SHF_AMDGPU_HSA_GLOBAL);
  82 }
  83
  84 bool isGroupSegment(const GlobalValue *GV) {
  85   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
  86 }
  87
  88 bool isGlobalSegment(const GlobalValue *GV) {
  89   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
  90 }
  91
  92 bool isReadOnlySegment(const GlobalValue *GV) {
  93   return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
  94 }
  95
  96 } // End namespace AMDGPU
  97 } // End namespace llvm