1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The file contains the R600 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "R600RegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "R600MachineFunctionInfo.h"
20 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
27 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
29 BitVector Reserved(getNumRegs());
30 const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
42 E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
46 for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
47 E = MFI->ReservedRegs.end(); I != E; ++I) {
54 const TargetRegisterClass *
55 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
57 switch (rc->getID()) {
58 case AMDGPU::GPRF32RegClassID:
59 case AMDGPU::GPRI32RegClassID:
60 return &AMDGPU::R600_Reg32RegClass;
65 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
73 case AMDGPU::NEG_HALF:
74 case AMDGPU::ALU_LITERAL_X:
76 default: return getHWRegChanGen(reg);
80 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
85 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
88 #include "R600HwRegInfo.include"