1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 StringRef Annot, const MCSubtargetInfo &STI) {
25 printInstruction(MI, OS);
27 printAnnotation(OS, Annot);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
50 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
55 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm())
67 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
69 if (MI->getOperand(OpNo).getImm())
73 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
75 if (MI->getOperand(OpNo).getImm()) {
77 printU16ImmDecOperand(MI, OpNo, O);
81 void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo,
83 uint16_t Imm = MI->getOperand(OpNo).getImm();
86 printU16ImmDecOperand(MI, OpNo, O);
90 void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo,
92 if (MI->getOperand(OpNo).getImm()) {
94 printU8ImmDecOperand(MI, OpNo, O);
98 void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
100 if (MI->getOperand(OpNo).getImm()) {
102 printU8ImmDecOperand(MI, OpNo, O);
106 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
108 if (MI->getOperand(OpNo).getImm())
112 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
114 if (MI->getOperand(OpNo).getImm())
118 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
120 if (MI->getOperand(OpNo).getImm())
124 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
126 if (MI->getOperand(OpNo).getImm())
130 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
131 const MCRegisterInfo &MRI) {
145 case AMDGPU::FLAT_SCR:
154 case AMDGPU::EXEC_LO:
157 case AMDGPU::EXEC_HI:
160 case AMDGPU::FLAT_SCR_LO:
161 O << "flat_scratch_lo";
163 case AMDGPU::FLAT_SCR_HI:
164 O << "flat_scratch_hi";
173 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
176 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
179 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
182 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
185 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
188 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
191 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
194 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
197 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
200 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
203 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
207 O << getRegisterName(reg);
211 // The low 8 bits of the encoding value is the register index, for both VGPRs
213 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
219 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
222 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
224 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
229 printOperand(MI, OpNo, O);
232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
233 int32_t SImm = static_cast<int32_t>(Imm);
234 if (SImm >= -16 && SImm <= 64) {
239 if (Imm == FloatToBits(0.0f))
241 else if (Imm == FloatToBits(1.0f))
243 else if (Imm == FloatToBits(-1.0f))
245 else if (Imm == FloatToBits(0.5f))
247 else if (Imm == FloatToBits(-0.5f))
249 else if (Imm == FloatToBits(2.0f))
251 else if (Imm == FloatToBits(-2.0f))
253 else if (Imm == FloatToBits(4.0f))
255 else if (Imm == FloatToBits(-4.0f))
258 O << formatHex(static_cast<uint64_t>(Imm));
261 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
262 int64_t SImm = static_cast<int64_t>(Imm);
263 if (SImm >= -16 && SImm <= 64) {
268 if (Imm == DoubleToBits(0.0))
270 else if (Imm == DoubleToBits(1.0))
272 else if (Imm == DoubleToBits(-1.0))
274 else if (Imm == DoubleToBits(0.5))
276 else if (Imm == DoubleToBits(-0.5))
278 else if (Imm == DoubleToBits(2.0))
280 else if (Imm == DoubleToBits(-2.0))
282 else if (Imm == DoubleToBits(4.0))
284 else if (Imm == DoubleToBits(-4.0))
287 assert(isUInt<32>(Imm));
289 // In rare situations, we will have a 32-bit literal in a 64-bit
290 // operand. This is technically allowed for the encoding of s_mov_b64.
291 O << formatHex(static_cast<uint64_t>(Imm));
295 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
298 const MCOperand &Op = MI->getOperand(OpNo);
300 switch (Op.getReg()) {
301 // This is the default predicate state, so we don't need to print it.
302 case AMDGPU::PRED_SEL_OFF:
306 printRegOperand(Op.getReg(), O, MRI);
309 } else if (Op.isImm()) {
310 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
311 int RCID = Desc.OpInfo[OpNo].RegClass;
313 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
314 if (ImmRC.getSize() == 4)
315 printImmediate32(Op.getImm(), O);
316 else if (ImmRC.getSize() == 8)
317 printImmediate64(Op.getImm(), O);
319 llvm_unreachable("Invalid register class size");
320 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
321 printImmediate32(Op.getImm(), O);
323 // We hit this for the immediate instruction bits that don't yet have a
325 // TODO: Eventually this should be unnecessary.
326 O << formatDec(Op.getImm());
328 } else if (Op.isFPImm()) {
329 // We special case 0.0 because otherwise it will be printed as an integer.
330 if (Op.getFPImm() == 0.0)
333 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
334 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
336 if (ImmRC.getSize() == 4)
337 printImmediate32(FloatToBits(Op.getFPImm()), O);
338 else if (ImmRC.getSize() == 8)
339 printImmediate64(DoubleToBits(Op.getFPImm()), O);
341 llvm_unreachable("Invalid register class size");
343 } else if (Op.isExpr()) {
344 const MCExpr *Exp = Op.getExpr();
347 llvm_unreachable("unknown operand type in printOperand");
351 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
353 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
354 if (InputModifiers & SISrcMods::NEG)
356 if (InputModifiers & SISrcMods::ABS)
358 printOperand(MI, OpNo + 1, O);
359 if (InputModifiers & SISrcMods::ABS)
363 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
365 unsigned Imm = MI->getOperand(OpNum).getImm();
369 } else if (Imm == 1) {
371 } else if (Imm == 0) {
374 llvm_unreachable("Invalid interpolation parameter slot");
378 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
380 printOperand(MI, OpNo, O);
382 printOperand(MI, OpNo + 1, O);
385 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
386 raw_ostream &O, StringRef Asm,
388 const MCOperand &Op = MI->getOperand(OpNo);
390 if (Op.getImm() == 1) {
397 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
399 printIfSet(MI, OpNo, O, "|");
402 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
404 printIfSet(MI, OpNo, O, "_SAT");
407 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
409 if (MI->getOperand(OpNo).getImm())
413 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
415 int Imm = MI->getOperand(OpNo).getImm();
416 if (Imm == SIOutMods::MUL2)
418 else if (Imm == SIOutMods::MUL4)
420 else if (Imm == SIOutMods::DIV2)
424 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
426 int32_t Imm = MI->getOperand(OpNo).getImm();
427 O << Imm << '(' << BitsToFloat(Imm) << ')';
430 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
432 printIfSet(MI, OpNo, O, "*", " ");
435 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
437 printIfSet(MI, OpNo, O, "-");
440 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
442 switch (MI->getOperand(OpNo).getImm()) {
456 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
458 printIfSet(MI, OpNo, O, "+");
461 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
463 printIfSet(MI, OpNo, O, "ExecMask,");
466 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
468 printIfSet(MI, OpNo, O, "Pred,");
471 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
473 const MCOperand &Op = MI->getOperand(OpNo);
474 if (Op.getImm() == 0) {
479 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
481 const char * chans = "XYZW";
482 int sel = MI->getOperand(OpNo).getImm();
491 O << cb << '[' << sel << ']';
492 } else if (sel >= 448) {
495 } else if (sel >= 0){
500 O << '.' << chans[chan];
503 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
505 int BankSwizzle = MI->getOperand(OpNo).getImm();
506 switch (BankSwizzle) {
508 O << "BS:VEC_021/SCL_122";
511 O << "BS:VEC_120/SCL_212";
514 O << "BS:VEC_102/SCL_221";
528 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
530 unsigned Sel = MI->getOperand(OpNo).getImm();
558 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
560 unsigned CT = MI->getOperand(OpNo).getImm();
573 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
575 int KCacheMode = MI->getOperand(OpNo).getImm();
576 if (KCacheMode > 0) {
577 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
578 O << "CB" << KCacheBank << ':';
579 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
580 int LineSize = (KCacheMode == 1) ? 16 : 32;
581 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
585 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
587 unsigned SImm16 = MI->getOperand(OpNo).getImm();
588 unsigned Msg = SImm16 & 0xF;
589 if (Msg == 2 || Msg == 3) {
590 unsigned Op = (SImm16 >> 4) & 0xF;
598 unsigned Stream = (SImm16 >> 8) & 0x3;
605 O << " stream " << Stream;
613 O << "unknown(" << Msg << ") ";
616 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
618 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
619 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
620 // works so it might be a misprint in docs.
621 unsigned SImm16 = MI->getOperand(OpNo).getImm();
622 unsigned Vmcnt = SImm16 & 0xF;
623 unsigned Expcnt = (SImm16 >> 4) & 0xF;
624 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
626 bool NeedSpace = false;
629 O << "vmcnt(" << Vmcnt << ')';
636 O << "expcnt(" << Expcnt << ')';
640 if (Lgkmcnt != 0x7) {
643 O << "lgkmcnt(" << Lgkmcnt << ')';
647 #include "AMDGPUGenAsmWriter.inc"