1 //===- AMDILInstrInfo.h - AMDIL Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // This file contains the AMDIL implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef AMDILINSTRUCTIONINFO_H_
15 #define AMDILINSTRUCTIONINFO_H_
17 #include "AMDILRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
20 #define GET_INSTRINFO_HEADER
21 #include "AMDGPUGenInstrInfo.inc"
24 // AMDIL - This namespace holds all of the target specific flags that
25 // instruction info tracks.
27 //class AMDILTargetMachine;
28 class AMDILInstrInfo : public AMDILGenInstrInfo {
30 const AMDILRegisterInfo RI;
31 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
32 MachineBasicBlock &MBB) const;
33 unsigned int getBranchInstr(const MachineOperand &op) const;
35 explicit AMDILInstrInfo(TargetMachine &tm);
37 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 // such, whenever a client has an instance of instruction info, it should
39 // always be able to get register info as well (through this method).
40 const AMDILRegisterInfo &getRegisterInfo() const;
42 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
43 unsigned &DstReg, unsigned &SubIdx) const;
45 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
46 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
47 int &FrameIndex) const;
48 bool hasLoadFromStackSlot(const MachineInstr *MI,
49 const MachineMemOperand *&MMO,
50 int &FrameIndex) const;
51 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
52 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
53 int &FrameIndex) const;
54 bool hasStoreFromStackSlot(const MachineInstr *MI,
55 const MachineMemOperand *&MMO,
56 int &FrameIndex) const;
59 convertToThreeAddress(MachineFunction::iterator &MFI,
60 MachineBasicBlock::iterator &MBBI,
61 LiveVariables *LV) const;
63 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
64 MachineBasicBlock *&FBB,
65 SmallVectorImpl<MachineOperand> &Cond,
66 bool AllowModify) const;
68 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
71 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72 MachineBasicBlock *FBB,
73 const SmallVectorImpl<MachineOperand> &Cond,
76 virtual void copyPhysReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MI, DebugLoc DL,
78 unsigned DestReg, unsigned SrcReg,
79 bool KillSrc) const = 0;
81 void storeRegToStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned SrcReg, bool isKill, int FrameIndex,
84 const TargetRegisterClass *RC,
85 const TargetRegisterInfo *TRI) const;
86 void loadRegFromStackSlot(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 unsigned DestReg, int FrameIndex,
89 const TargetRegisterClass *RC,
90 const TargetRegisterInfo *TRI) const;
93 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
95 const SmallVectorImpl<unsigned> &Ops,
96 int FrameIndex) const;
97 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
99 const SmallVectorImpl<unsigned> &Ops,
100 MachineInstr *LoadMI) const;
102 bool canFoldMemoryOperand(const MachineInstr *MI,
103 const SmallVectorImpl<unsigned> &Ops) const;
104 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
105 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
106 SmallVectorImpl<MachineInstr *> &NewMIs) const;
107 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
108 SmallVectorImpl<SDNode *> &NewNodes) const;
109 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
110 bool UnfoldLoad, bool UnfoldStore,
111 unsigned *LoadRegIndex = 0) const;
112 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
113 int64_t Offset1, int64_t Offset2,
114 unsigned NumLoads) const;
116 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
117 void insertNoop(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator MI) const;
119 bool isPredicated(const MachineInstr *MI) const;
120 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
121 const SmallVectorImpl<MachineOperand> &Pred2) const;
122 bool DefinesPredicate(MachineInstr *MI,
123 std::vector<MachineOperand> &Pred) const;
124 bool isPredicable(MachineInstr *MI) const;
125 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
127 // Helper functions that check the opcode for status information
128 bool isLoadInst(llvm::MachineInstr *MI) const;
129 bool isExtLoadInst(llvm::MachineInstr *MI) const;
130 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
131 bool isSExtLoadInst(llvm::MachineInstr *MI) const;
132 bool isZExtLoadInst(llvm::MachineInstr *MI) const;
133 bool isAExtLoadInst(llvm::MachineInstr *MI) const;
134 bool isStoreInst(llvm::MachineInstr *MI) const;
135 bool isTruncStoreInst(llvm::MachineInstr *MI) const;
136 bool isAtomicInst(llvm::MachineInstr *MI) const;
137 bool isVolatileInst(llvm::MachineInstr *MI) const;
138 bool isGlobalInst(llvm::MachineInstr *MI) const;
139 bool isPrivateInst(llvm::MachineInstr *MI) const;
140 bool isConstantInst(llvm::MachineInstr *MI) const;
141 bool isRegionInst(llvm::MachineInstr *MI) const;
142 bool isLocalInst(llvm::MachineInstr *MI) const;
143 bool isImageInst(llvm::MachineInstr *MI) const;
144 bool isAppendInst(llvm::MachineInstr *MI) const;
145 bool isRegionAtomic(llvm::MachineInstr *MI) const;
146 bool isLocalAtomic(llvm::MachineInstr *MI) const;
147 bool isGlobalAtomic(llvm::MachineInstr *MI) const;
148 bool isArenaAtomic(llvm::MachineInstr *MI) const;
150 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
151 int64_t Imm) const = 0;
153 virtual unsigned getIEQOpcode() const = 0;
155 virtual bool isMov(unsigned Opcode) const = 0;
160 #endif // AMDILINSTRINFO_H_