1 //===-- AMDILISelLowering.h - AMDIL DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // This file defines the interfaces that AMDIL uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef AMDIL_ISELLOWERING_H_
16 #define AMDIL_ISELLOWERING_H_
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 CMOVLOG, // 32bit FP Conditional move logical instruction
31 MAD, // 32bit Fused Multiply Add instruction
32 VBUILD, // scalar to vector mov instruction
33 CALL, // Function call based on a single integer
34 SELECT_CC, // Select the correct conditional instruction
35 UMUL, // 32bit unsigned multiplication
36 DIV_INF, // Divide with infinity returned on zero divisor
50 class MachineBasicBlock;
53 class TargetInstrInfo;
55 class AMDILTargetLowering : public TargetLowering
58 AMDILTargetLowering(TargetMachine &TM);
61 LowerOperation(SDValue Op, SelectionDAG &DAG) const;
63 /// computeMaskedBitsForTargetNode - Determine which of
64 /// the bits specified
65 /// in Mask are known to be either zero or one and return them in
67 /// KnownZero/KnownOne bitsets.
69 computeMaskedBitsForTargetNode(
73 const SelectionDAG &DAG,
78 getTgtMemIntrinsic(IntrinsicInfo &Info,
79 const CallInst &I, unsigned Intrinsic) const;
84 // We want to mark f32/f64 floating point values as
87 isFPImmLegal(const APFloat &Imm, EVT VT) const;
88 // We don't want to shrink f64/f32 constants because
89 // they both take up the same amount of space and
90 // we don't want to use a f2d instruction.
91 bool ShouldShrinkFPConstant(EVT VT) const;
93 /// getFunctionAlignment - Return the Log2 alignment of this
96 getFunctionAlignment(const Function *F) const;
100 CCAssignFnForNode(unsigned int CC) const;
102 SDValue LowerCallResult(SDValue Chain,
104 CallingConv::ID CallConv,
106 const SmallVectorImpl<ISD::InputArg> &Ins,
109 SmallVectorImpl<SDValue> &InVals) const;
111 SDValue LowerMemArgument(SDValue Chain,
112 CallingConv::ID CallConv,
113 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
114 DebugLoc dl, SelectionDAG &DAG,
115 const CCValAssign &VA, MachineFrameInfo *MFI,
118 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
120 DebugLoc dl, SelectionDAG &DAG,
121 const CCValAssign &VA,
122 ISD::ArgFlagsTy Flags) const;
125 LowerFormalArguments(SDValue Chain,
126 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
128 DebugLoc dl, SelectionDAG &DAG,
129 SmallVectorImpl<SDValue> &InVals) const;
132 LowerCall(CallLoweringInfo &CLI,
133 SmallVectorImpl<SDValue> &InVals) const;
136 LowerReturn(SDValue Chain,
137 CallingConv::ID CallConv, bool isVarArg,
138 const SmallVectorImpl<ISD::OutputArg> &Outs,
139 const SmallVectorImpl<SDValue> &OutVals,
140 DebugLoc dl, SelectionDAG &DAG) const;
143 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
146 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
149 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
152 LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
155 LowerSREM(SDValue Op, SelectionDAG &DAG) const;
157 LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
159 LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
161 LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
163 LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
166 LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
168 LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
170 LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
172 LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
175 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
178 LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
181 LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
184 LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
187 genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
190 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
193 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
196 LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
198 LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
200 }; // AMDILTargetLowering
201 } // end namespace llvm
203 #endif // AMDIL_ISELLOWERING_H_