1 //==- AMDILFormats.td - AMDIL Instruction Formats ----*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 //===--------------------------------------------------------------------===//
11 include "AMDILTokenDesc.td"
13 //===--------------------------------------------------------------------===//
14 // The parent IL instruction class that inherits the Instruction class. This
15 // class sets the corresponding namespace, the out and input dag lists the
16 // pattern to match to and the string to print out for the assembly printer.
17 //===--------------------------------------------------------------------===//
18 class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
21 let Namespace = "AMDGPU";
22 dag OutOperandList = outs;
23 dag InOperandList = ins;
24 ILOpCode operation = op;
25 let Pattern = pattern;
26 let AsmString = !strconcat(asmstr, "\n");
28 let Itinerary = NullALU;
30 bit hasZeroOpFlag = 0;
33 //===--------------------------------------------------------------------===//
34 // Class that has one input parameters and one output parameter.
35 // The basic pattern for this class is "Opcode Dst, Src0" and
36 // handles the unary math operators.
37 // It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod
38 // if the addressing is register relative for input and output register 0.
39 //===--------------------------------------------------------------------===//
40 class OneInOneOut<ILOpCode op, dag outs, dag ins,
41 string asmstr, list<dag> pattern>
42 : ILFormat<op, outs, ins, asmstr, pattern>
48 ILSrcMod dst_reg_rel_mod;
53 ILSrcMod src0_reg_rel_mod;
56 //===--------------------------------------------------------------------===//
57 // This class is similiar to the UnaryOp class, however, there is no
58 // result value to assign.
59 //===--------------------------------------------------------------------===//
60 class UnaryOpNoRet<ILOpCode op, dag outs, dag ins,
61 string asmstr, list<dag> pattern>
62 : ILFormat<op, outs, ins, asmstr, pattern>
68 ILSrcMod src0_reg_rel_mod;
71 //===--------------------------------------------------------------------===//
72 // Set of classes that have two input parameters and one output parameter.
73 // The basic pattern for this class is "Opcode Dst, Src0, Src1" and
74 // handles the binary math operators and comparison operations.
75 // It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod
76 // if the addressing is register relative for input register 1.
77 //===--------------------------------------------------------------------===//
78 class TwoInOneOut<ILOpCode op, dag outs, dag ins,
79 string asmstr, list<dag> pattern>
80 : OneInOneOut<op, outs, ins, asmstr, pattern>
86 ILSrcMod src1_reg_rel_mod;
89 //===--------------------------------------------------------------------===//
90 // Similiar to the UnaryOpNoRet class, but takes as arguments two input
91 // operands. Used mainly for barrier instructions on PC platform.
92 //===--------------------------------------------------------------------===//
93 class BinaryOpNoRet<ILOpCode op, dag outs, dag ins,
94 string asmstr, list<dag> pattern>
95 : UnaryOpNoRet<op, outs, ins, asmstr, pattern>
101 ILSrcMod src1_reg_rel_mod;
104 //===--------------------------------------------------------------------===//
105 // Set of classes that have three input parameters and one output parameter.
106 // The basic pattern for this class is "Opcode Dst, Src0, Src1, Src2" and
107 // handles the mad and conditional mov instruction.
108 // It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod
109 // if the addressing is register relative.
110 // This class is the parent class of TernaryOp
111 //===--------------------------------------------------------------------===//
112 class ThreeInOneOut<ILOpCode op, dag outs, dag ins,
113 string asmstr, list<dag> pattern>
114 : TwoInOneOut<op, outs, ins, asmstr, pattern> {
119 ILSrcMod src2_reg_rel_mod;
122 //===--------------------------------------------------------------------===//
124 // Generic versions of the above classes but for Target specific intrinsics
125 // instead of SDNode patterns.
126 //===--------------------------------------------------------------------===//
127 let TargetPrefix = "AMDIL", isTarget = 1 in {
129 Intrinsic<[llvm_i64_ty], [], []>;
131 Intrinsic<[llvm_i32_ty], [], []>;
133 Intrinsic<[llvm_i32_ty], [], []>;
135 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
136 class UnaryIntFloat :
137 Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
138 class ConvertIntFTOI :
139 Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
140 class ConvertIntITOF :
141 Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], [IntrNoMem]>;
142 class UnaryIntNoRetInt :
143 Intrinsic<[], [llvm_anyint_ty], []>;
144 class UnaryIntNoRetFloat :
145 Intrinsic<[], [llvm_anyfloat_ty], []>;
147 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
148 class BinaryIntFloat :
149 Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
150 class BinaryIntNoRetInt :
151 Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>;
152 class BinaryIntNoRetFloat :
153 Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>;
154 class TernaryIntInt :
155 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
156 LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
157 class TernaryIntFloat :
158 Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>,
159 LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
160 class QuaternaryIntInt :
161 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
162 LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
163 class UnaryAtomicInt :
164 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
165 class BinaryAtomicInt :
166 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
167 class TernaryAtomicInt :
168 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
169 class UnaryAtomicIntNoRet :
170 Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
171 class BinaryAtomicIntNoRet :
172 Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
173 class TernaryAtomicIntNoRet :
174 Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;