lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
  24         "DumpCode",
  25         "true",
  26         "Dump MachineInstrs in the CodeEmitter">;
  27
  28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  29         "EnableIRStructurizer",
  30         "false",
  31         "Disable IR Structurizer">;
  32
  33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  34         "EnablePromoteAlloca",
  35         "true",
  36         "Enable promote alloca pass">;
  37
  38 // Target features
  39
  40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  41         "EnableIfCvt",
  42         "false",
  43         "Disable the if conversion pass">;
  44
  45 def FeatureFP64 : SubtargetFeature<"fp64",
  46         "FP64",
  47         "true",
  48         "Enable double precision operations">;
  49
  50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  51         "FP64Denormals",
  52         "true",
  53         "Enable double precision denormal handling",
  54         [FeatureFP64]>;
  55
  56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  57         "FastFMAF32",
  58         "true",
  59         "Assuming f32 fma is at least as fast as mul + add",
  60         []>;
  61
  62 // Some instructions do not support denormals despite this flag. Using
  63 // fp32 denormals also causes instructions to run at the double
  64 // precision rate for the device.
  65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  66         "FP32Denormals",
  67         "true",
  68         "Enable single precision denormal handling">;
  69
  70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  71         "Is64bit",
  72         "true",
  73         "Specify if 64-bit addressing should be used">;
  74
  75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  76         "R600ALUInst",
  77         "false",
  78         "Older version of ALU instructions encoding">;
  79
  80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  81         "HasVertexCache",
  82         "true",
  83         "Specify use of dedicated vertex cache">;
  84
  85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  86         "CaymanISA",
  87         "true",
  88         "Use Cayman ISA">;
  89
  90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  91         "CFALUBug",
  92         "true",
  93         "GPU has CF_ALU bug">;
  94
  95 // XXX - This should probably be removed once enabled by default
  96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  97         "EnableLoadStoreOpt",
  98         "true",
  99         "Enable SI load/store optimizer pass">;
 100
 101 // Performance debugging feature. Allow using DS instruction immediate
 102 // offsets even if the base pointer can't be proven to be base. On SI,
 103 // base pointer values that won't give the same result as a 16-bit add
 104 // are not safe to fold, but this will override the conservative test
 105 // for the base pointer.
 106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
 107         "EnableUnsafeDSOffsetFolding",
 108         "true",
 109         "Force using DS instruction immediate offsets on SI">;
 110
 111 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 112         "FlatForGlobal",
 113         "true",
 114         "Force to generate flat instruction for global">;
 115
 116 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
 117         "FlatAddressSpace",
 118         "true",
 119         "Support flat address space">;
 120
 121 def FeatureXNACK : SubtargetFeature<"xnack",
 122         "EnableXNACK",
 123         "true",
 124         "Enable XNACK support">;
 125
 126 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 127         "EnableVGPRSpilling",
 128         "true",
 129         "Enable spilling of VGPRs to scratch memory">;
 130
 131 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 132         "SGPRInitBug",
 133         "true",
 134         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
 135
 136 def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
 137         "EnableHugeScratchBuffer",
 138         "true",
 139         "Enable scratch buffer sizes greater than 128 GB">;
 140
 141 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 142         "EnableSIScheduler",
 143         "true",
 144         "Enable SI Machine Scheduler">;
 145
 146 class SubtargetFeatureFetchLimit <string Value> :
 147                           SubtargetFeature <"fetch"#Value,
 148         "TexVTXClauseSize",
 149         Value,
 150         "Limit the maximum number of fetches in a clause to "#Value>;
 151
 152 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 153 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 154
 155 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 156         "wavefrontsize"#Value,
 157         "WavefrontSize",
 158         !cast<string>(Value),
 159         "The number of threads per wavefront">;
 160
 161 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 162 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 163 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 164
 165 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 166       "ldsbankcount"#Value,
 167       "LDSBankCount",
 168       !cast<string>(Value),
 169       "The number of LDS banks per compute unit.">;
 170
 171 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 172 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 173
 174 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
 175                                  : SubtargetFeature <
 176       "isaver"#Major#"."#Minor#"."#Stepping,
 177       "IsaVersion",
 178       "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
 179       "Instruction set version number"
 180 >;
 181
 182 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
 183 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
 184 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
 185 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
 186 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
 187
 188 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 189         "localmemorysize"#Value,
 190         "LocalMemorySize",
 191         !cast<string>(Value),
 192         "The size of local memory in bytes">;
 193
 194 def FeatureGCN : SubtargetFeature<"gcn",
 195         "IsGCN",
 196         "true",
 197         "GCN or newer GPU">;
 198
 199 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
 200         "GCN1Encoding",
 201         "true",
 202         "Encoding format for SI and CI">;
 203
 204 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 205         "GCN3Encoding",
 206         "true",
 207         "Encoding format for VI">;
 208
 209 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 210         "CIInsts",
 211         "true",
 212         "Additional intstructions for CI+">;
 213
 214 // Dummy feature used to disable assembler instructions.
 215 def FeatureDisable : SubtargetFeature<"",
 216                                       "FeatureDisable","true",
 217                                       "Dummy feature to disable assembler"
 218                                       " instructions">;
 219
 220 class SubtargetFeatureGeneration <string Value,
 221                                   list<SubtargetFeature> Implies> :
 222         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 223                           Value#" GPU generation", Implies>;
 224
 225 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 226 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 227 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 228
 229 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 230         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 231
 232 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 233         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 234
 235 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 236         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 237
 238 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 239         [FeatureFetchLimit16, FeatureWavefrontSize64,
 240          FeatureLocalMemorySize32768]
 241 >;
 242
 243 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 244         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 245          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
 246          FeatureLDSBankCount32]>;
 247
 248 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 249         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 250          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 251          FeatureGCN1Encoding, FeatureCIInsts]>;
 252
 253 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 254         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 255          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 256          FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
 257
 258 //===----------------------------------------------------------------------===//
 259
 260 def AMDGPUInstrInfo : InstrInfo {
 261   let guessInstructionProperties = 1;
 262   let noNamedPositionallyEncodedOperands = 1;
 263 }
 264
 265 def AMDGPUAsmParser : AsmParser {
 266   // Some of the R600 registers have the same name, so this crashes.
 267   // For example T0_XYZW and T0_XY both have the asm name T0.
 268   let ShouldEmitMatchRegisterName = 0;
 269 }
 270
 271 def AMDGPU : Target {
 272   // Pull in Instruction Info:
 273   let InstructionSet = AMDGPUInstrInfo;
 274   let AssemblyParsers = [AMDGPUAsmParser];
 275 }
 276
 277 // Dummy Instruction itineraries for pseudo instructions
 278 def ALU_NULL : FuncUnit;
 279 def NullALU : InstrItinClass;
 280
 281 //===----------------------------------------------------------------------===//
 282 // Predicate helper class
 283 //===----------------------------------------------------------------------===//
 284
 285 def TruePredicate : Predicate<"true">;
 286 def isSICI : Predicate<
 287   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 288   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 289 >, AssemblerPredicate<"FeatureGCN1Encoding">;
 290
 291 def isVI : Predicate <
 292   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
 293   AssemblerPredicate<"FeatureGCN3Encoding">;
 294
 295 class PredicateControl {
 296   Predicate SubtargetPredicate;
 297   Predicate SIAssemblerPredicate = isSICI;
 298   Predicate VIAssemblerPredicate = isVI;
 299   list<Predicate> AssemblerPredicates = [];
 300   Predicate AssemblerPredicate = TruePredicate;
 301   list<Predicate> OtherPredicates = [];
 302   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
 303                                             AssemblerPredicates,
 304                                             OtherPredicates);
 305 }
 306
 307 // Include AMDGPU TD files
 308 include "R600Schedule.td"
 309 include "SISchedule.td"
 310 include "Processors.td"
 311 include "AMDGPUInstrInfo.td"
 312 include "AMDGPUIntrinsics.td"
 313 include "AMDGPURegisterInfo.td"
 314 include "AMDGPUInstructions.td"
 315 include "AMDGPUCallingConv.td"