lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

   1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides AArch64 specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AArch64MCTargetDesc.h"
  15 #include "AArch64ELFStreamer.h"
  16 #include "AArch64MCAsmInfo.h"
  17 #include "InstPrinter/AArch64InstPrinter.h"
  18 #include "llvm/ADT/APInt.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCInstrAnalysis.h"
  21 #include "llvm/MC/MCInstrInfo.h"
  22 #include "llvm/MC/MCRegisterInfo.h"
  23 #include "llvm/MC/MCStreamer.h"
  24 #include "llvm/MC/MCSubtargetInfo.h"
  25 #include "llvm/Support/ErrorHandling.h"
  26 #include "llvm/Support/TargetRegistry.h"
  27
  28 using namespace llvm;
  29
  30 #define GET_REGINFO_MC_DESC
  31 #include "AArch64GenRegisterInfo.inc"
  32
  33 #define GET_INSTRINFO_MC_DESC
  34 #include "AArch64GenInstrInfo.inc"
  35
  36 #define GET_SUBTARGETINFO_MC_DESC
  37 #include "AArch64GenSubtargetInfo.inc"
  38
  39 MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT,
  40                                                           StringRef CPU,
  41                                                           StringRef FS) {
  42   MCSubtargetInfo *X = new MCSubtargetInfo();
  43   InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
  44   return X;
  45 }
  46
  47
  48 static MCInstrInfo *createAArch64MCInstrInfo() {
  49   MCInstrInfo *X = new MCInstrInfo();
  50   InitAArch64MCInstrInfo(X);
  51   return X;
  52 }
  53
  54 static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
  55   MCRegisterInfo *X = new MCRegisterInfo();
  56   InitAArch64MCRegisterInfo(X, AArch64::X30);
  57   return X;
  58 }
  59
  60 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
  61                                          StringRef TT) {
  62   Triple TheTriple(TT);
  63
  64   MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
  65   unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
  66   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
  67   MAI->addInitialFrameState(Inst);
  68
  69   return MAI;
  70 }
  71
  72 static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
  73                                                  CodeModel::Model CM,
  74                                                  CodeGenOpt::Level OL) {
  75   MCCodeGenInfo *X = new MCCodeGenInfo();
  76   if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) {
  77     // On ELF platforms the default static relocation model has a smart enough
  78     // linker to cope with referencing external symbols defined in a shared
  79     // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
  80     RM = Reloc::Static;
  81   }
  82
  83   if (CM == CodeModel::Default)
  84     CM = CodeModel::Small;
  85   else if (CM == CodeModel::JITDefault) {
  86     // The default MCJIT memory managers make no guarantees about where they can
  87     // find an executable page; JITed code needs to be able to refer to globals
  88     // no matter how far away they are.
  89     CM = CodeModel::Large;
  90   }
  91
  92   X->InitMCCodeGenInfo(RM, CM, OL);
  93   return X;
  94 }
  95
  96 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
  97                                     MCContext &Ctx, MCAsmBackend &MAB,
  98                                     raw_ostream &OS,
  99                                     MCCodeEmitter *Emitter,
 100                                     const MCSubtargetInfo &STI,
 101                                     bool RelaxAll,
 102                                     bool NoExecStack) {
 103   Triple TheTriple(TT);
 104
 105   return createAArch64ELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
 106 }
 107
 108
 109 static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
 110                                                  unsigned SyntaxVariant,
 111                                                  const MCAsmInfo &MAI,
 112                                                  const MCInstrInfo &MII,
 113                                                  const MCRegisterInfo &MRI,
 114                                                  const MCSubtargetInfo &STI) {
 115   if (SyntaxVariant == 0)
 116     return new AArch64InstPrinter(MAI, MII, MRI, STI);
 117   return 0;
 118 }
 119
 120 namespace {
 121
 122 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
 123 public:
 124   AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 125
 126   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
 127     if (Inst.getOpcode() == AArch64::Bcc
 128         && Inst.getOperand(0).getImm() == A64CC::AL)
 129       return true;
 130     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 131   }
 132
 133   virtual bool isConditionalBranch(const MCInst &Inst) const {
 134     if (Inst.getOpcode() == AArch64::Bcc
 135         && Inst.getOperand(0).getImm() == A64CC::AL)
 136       return false;
 137     return MCInstrAnalysis::isConditionalBranch(Inst);
 138   }
 139
 140   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 141                       uint64_t Size, uint64_t &Target) const {
 142     unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
 143     // FIXME: We only handle PCRel branches for now.
 144     if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
 145         != MCOI::OPERAND_PCREL)
 146       return false;
 147
 148     int64_t Imm = Inst.getOperand(LblOperand).getImm();
 149     Target = Addr + Imm;
 150     return true;
 151   }
 152 };
 153
 154 }
 155
 156 static MCInstrAnalysis *createAArch64MCInstrAnalysis(const MCInstrInfo *Info) {
 157   return new AArch64MCInstrAnalysis(Info);
 158 }
 159
 160
 161
 162 extern "C" void LLVMInitializeAArch64TargetMC() {
 163   // Register the MC asm info.
 164   RegisterMCAsmInfoFn A(TheAArch64leTarget, createAArch64MCAsmInfo);
 165   RegisterMCAsmInfoFn B(TheAArch64beTarget, createAArch64MCAsmInfo);
 166
 167   // Register the MC codegen info.
 168   TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
 169                                         createAArch64MCCodeGenInfo);
 170   TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
 171                                         createAArch64MCCodeGenInfo);
 172
 173   // Register the MC instruction info.
 174   TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget,
 175                                       createAArch64MCInstrInfo);
 176   TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget,
 177                                       createAArch64MCInstrInfo);
 178
 179   // Register the MC register info.
 180   TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget,
 181                                     createAArch64MCRegisterInfo);
 182   TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget,
 183                                     createAArch64MCRegisterInfo);
 184
 185   // Register the MC subtarget info.
 186   using AArch64_MC::createAArch64MCSubtargetInfo;
 187   TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
 188                                           createAArch64MCSubtargetInfo);
 189   TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
 190                                           createAArch64MCSubtargetInfo);
 191
 192   // Register the MC instruction analyzer.
 193   TargetRegistry::RegisterMCInstrAnalysis(TheAArch64leTarget,
 194                                           createAArch64MCInstrAnalysis);
 195   TargetRegistry::RegisterMCInstrAnalysis(TheAArch64beTarget,
 196                                           createAArch64MCInstrAnalysis);
 197
 198   // Register the MC Code Emitter
 199   TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
 200                                         createAArch64MCCodeEmitter);
 201   TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
 202                                         createAArch64MCCodeEmitter);
 203
 204   // Register the asm backend.
 205   TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget,
 206                                        createAArch64leAsmBackend);
 207   TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
 208                                        createAArch64beAsmBackend);
 209
 210   // Register the object streamer.
 211   TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget,
 212                                            createMCStreamer);
 213   TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget,
 214                                            createMCStreamer);
 215
 216   // Register the MCInstPrinter.
 217   TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
 218                                         createAArch64MCInstPrinter);
 219   TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
 220                                         createAArch64MCInstPrinter);
 221 }