lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AArch64Disassembler.h"
  14 #include "AArch64ExternalSymbolizer.h"
  15 #include "AArch64Subtarget.h"
  16 #include "MCTargetDesc/AArch64AddressingModes.h"
  17 #include "Utils/AArch64BaseInfo.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 #define DEBUG_TYPE "aarch64-disassembler"
  27
  28 // Pull DecodeStatus and its enum values into the global namespace.
  29 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 // Forward declare these because the autogenerated code will reference them.
  32 // Definitions are further down.
  33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  34                                               unsigned RegNo, uint64_t Address,
  35                                               const void *Decoder);
  36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
  37                                                  unsigned RegNo,
  38                                                  uint64_t Address,
  39                                                  const void *Decoder);
  40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  41                                              uint64_t Address,
  42                                              const void *Decoder);
  43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  44                                              uint64_t Address,
  45                                              const void *Decoder);
  46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  47                                              uint64_t Address,
  48                                              const void *Decoder);
  49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  50                                             uint64_t Address,
  51                                             const void *Decoder);
  52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  53                                              uint64_t Address,
  54                                              const void *Decoder);
  55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
  56                                                unsigned RegNo, uint64_t Address,
  57                                                const void *Decoder);
  58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  59                                              uint64_t Address,
  60                                              const void *Decoder);
  61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
  62                                                unsigned RegNo, uint64_t Address,
  63                                                const void *Decoder);
  64 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  65                                           uint64_t Address,
  66                                           const void *Decoder);
  67 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  68                                            uint64_t Address,
  69                                            const void *Decoder);
  70 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  71                                             uint64_t Address,
  72                                             const void *Decoder);
  73 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  74                                           uint64_t Address,
  75                                           const void *Decoder);
  76 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  77                                            uint64_t Address,
  78                                            const void *Decoder);
  79 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                             uint64_t Address,
  81                                             const void *Decoder);
  82
  83 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
  84                                                uint64_t Address,
  85                                                const void *Decoder);
  86 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
  87                                                uint64_t Address,
  88                                                const void *Decoder);
  89 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
  90                                        uint64_t Address, const void *Decoder);
  91 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
  92                                     uint64_t Address, const void *Decoder);
  93 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  94                                             uint64_t Address, const void *Decoder);
  95 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
  96                                             uint64_t Address, const void *Decoder);
  97 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
  98                                                    uint32_t insn,
  99                                                    uint64_t Address,
 100                                                    const void *Decoder);
 101 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 102                                              uint64_t Address,
 103                                              const void *Decoder);
 104 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 105                                                   uint32_t insn,
 106                                                   uint64_t Address,
 107                                                   const void *Decoder);
 108 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 109                                                 uint32_t insn, uint64_t Address,
 110                                                 const void *Decoder);
 111 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
 112                                                    uint32_t insn,
 113                                                    uint64_t Address,
 114                                                    const void *Decoder);
 115 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
 116                                               uint64_t Address,
 117                                               const void *Decoder);
 118 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
 119                                                 uint32_t insn, uint64_t Address,
 120                                                 const void *Decoder);
 121 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
 122                                                 uint32_t insn, uint64_t Address,
 123                                                 const void *Decoder);
 124 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 125                                             uint64_t Address,
 126                                             const void *Decoder);
 127 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
 128                                                 uint32_t insn, uint64_t Address,
 129                                                 const void *Decoder);
 130 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
 131                                          uint64_t Address, const void *Decoder);
 132 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
 133                                         uint64_t Address, const void *Decoder);
 134 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
 138                                                   uint32_t insn,
 139                                                   uint64_t Address,
 140                                                   const void *Decoder);
 141 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
 142                                         uint64_t Address, const void *Decoder);
 143
 144 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 145                                               uint64_t Address,
 146                                               const void *Decoder);
 147 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 148                                          uint64_t Addr, const void *Decoder);
 149 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 150                                                uint64_t Addr,
 151                                                const void *Decoder);
 152 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 153                                          uint64_t Addr, const void *Decoder);
 154 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 155                                                uint64_t Addr,
 156                                                const void *Decoder);
 157 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 158                                          uint64_t Addr, const void *Decoder);
 159 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 160                                                uint64_t Addr,
 161                                                const void *Decoder);
 162 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 163                                         uint64_t Addr, const void *Decoder);
 164 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 165                                          uint64_t Addr, const void *Decoder);
 166 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 167                                          uint64_t Addr, const void *Decoder);
 168 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 169                                          uint64_t Addr, const void *Decoder);
 170 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 171                                         uint64_t Addr, const void *Decoder);
 172 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
 173                                                       unsigned RegNo,
 174                                                       uint64_t Addr,
 175                                                       const void *Decoder);
 176 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
 177                                                       unsigned RegNo,
 178                                                       uint64_t Addr,
 179                                                       const void *Decoder);
 180
 181 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 182   switch (In) {
 183     case MCDisassembler::Success:
 184       // Out stays the same.
 185       return true;
 186     case MCDisassembler::SoftFail:
 187       Out = In;
 188       return true;
 189     case MCDisassembler::Fail:
 190       Out = In;
 191       return false;
 192   }
 193   llvm_unreachable("Invalid DecodeStatus!");
 194 }
 195
 196 #include "AArch64GenDisassemblerTables.inc"
 197 #include "AArch64GenInstrInfo.inc"
 198
 199 #define Success llvm::MCDisassembler::Success
 200 #define Fail llvm::MCDisassembler::Fail
 201 #define SoftFail llvm::MCDisassembler::SoftFail
 202
 203 static MCDisassembler *createAArch64Disassembler(const Target &T,
 204                                                const MCSubtargetInfo &STI,
 205                                                MCContext &Ctx) {
 206   return new AArch64Disassembler(STI, Ctx);
 207 }
 208
 209 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 210                                                  ArrayRef<uint8_t> Bytes,
 211                                                  uint64_t Address,
 212                                                  raw_ostream &OS,
 213                                                  raw_ostream &CS) const {
 214   CommentStream = &CS;
 215
 216   Size = 0;
 217   // We want to read exactly 4 bytes of data.
 218   if (Bytes.size() < 4)
 219     return Fail;
 220   Size = 4;
 221
 222   // Encoded as a small-endian 32-bit word in the stream.
 223   uint32_t Insn =
 224       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
 225
 226   // Calling the auto-generated decoder function.
 227   return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
 228 }
 229
 230 static MCSymbolizer *createAArch64ExternalSymbolizer(
 231     const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo,
 232     LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
 233     std::unique_ptr<MCRelocationInfo> &&RelInfo) {
 234   return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
 235                                              SymbolLookUp, DisInfo);
 236 }
 237
 238 extern "C" void LLVMInitializeAArch64Disassembler() {
 239   TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
 240                                          createAArch64Disassembler);
 241   TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
 242                                          createAArch64Disassembler);
 243   TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
 244                                        createAArch64ExternalSymbolizer);
 245   TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
 246                                        createAArch64ExternalSymbolizer);
 247
 248   TargetRegistry::RegisterMCDisassembler(TheARM64Target,
 249                                          createAArch64Disassembler);
 250   TargetRegistry::RegisterMCSymbolizer(TheARM64Target,
 251                                        createAArch64ExternalSymbolizer);
 252 }
 253
 254 static const unsigned FPR128DecoderTable[] = {
 255     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 256     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 257     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 258     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 259     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 260     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 261     AArch64::Q30, AArch64::Q31
 262 };
 263
 264 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
 265                                               uint64_t Addr,
 266                                               const void *Decoder) {
 267   if (RegNo > 31)
 268     return Fail;
 269
 270   unsigned Register = FPR128DecoderTable[RegNo];
 271   Inst.addOperand(MCOperand::createReg(Register));
 272   return Success;
 273 }
 274
 275 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
 276                                                  uint64_t Addr,
 277                                                  const void *Decoder) {
 278   if (RegNo > 15)
 279     return Fail;
 280   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
 281 }
 282
 283 static const unsigned FPR64DecoderTable[] = {
 284     AArch64::D0,  AArch64::D1,  AArch64::D2,  AArch64::D3,  AArch64::D4,
 285     AArch64::D5,  AArch64::D6,  AArch64::D7,  AArch64::D8,  AArch64::D9,
 286     AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
 287     AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
 288     AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
 289     AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
 290     AArch64::D30, AArch64::D31
 291 };
 292
 293 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 294                                              uint64_t Addr,
 295                                              const void *Decoder) {
 296   if (RegNo > 31)
 297     return Fail;
 298
 299   unsigned Register = FPR64DecoderTable[RegNo];
 300   Inst.addOperand(MCOperand::createReg(Register));
 301   return Success;
 302 }
 303
 304 static const unsigned FPR32DecoderTable[] = {
 305     AArch64::S0,  AArch64::S1,  AArch64::S2,  AArch64::S3,  AArch64::S4,
 306     AArch64::S5,  AArch64::S6,  AArch64::S7,  AArch64::S8,  AArch64::S9,
 307     AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
 308     AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
 309     AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
 310     AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
 311     AArch64::S30, AArch64::S31
 312 };
 313
 314 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 315                                              uint64_t Addr,
 316                                              const void *Decoder) {
 317   if (RegNo > 31)
 318     return Fail;
 319
 320   unsigned Register = FPR32DecoderTable[RegNo];
 321   Inst.addOperand(MCOperand::createReg(Register));
 322   return Success;
 323 }
 324
 325 static const unsigned FPR16DecoderTable[] = {
 326     AArch64::H0,  AArch64::H1,  AArch64::H2,  AArch64::H3,  AArch64::H4,
 327     AArch64::H5,  AArch64::H6,  AArch64::H7,  AArch64::H8,  AArch64::H9,
 328     AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
 329     AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
 330     AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
 331     AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
 332     AArch64::H30, AArch64::H31
 333 };
 334
 335 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
 336                                              uint64_t Addr,
 337                                              const void *Decoder) {
 338   if (RegNo > 31)
 339     return Fail;
 340
 341   unsigned Register = FPR16DecoderTable[RegNo];
 342   Inst.addOperand(MCOperand::createReg(Register));
 343   return Success;
 344 }
 345
 346 static const unsigned FPR8DecoderTable[] = {
 347     AArch64::B0,  AArch64::B1,  AArch64::B2,  AArch64::B3,  AArch64::B4,
 348     AArch64::B5,  AArch64::B6,  AArch64::B7,  AArch64::B8,  AArch64::B9,
 349     AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
 350     AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
 351     AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
 352     AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
 353     AArch64::B30, AArch64::B31
 354 };
 355
 356 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 357                                             uint64_t Addr,
 358                                             const void *Decoder) {
 359   if (RegNo > 31)
 360     return Fail;
 361
 362   unsigned Register = FPR8DecoderTable[RegNo];
 363   Inst.addOperand(MCOperand::createReg(Register));
 364   return Success;
 365 }
 366
 367 static const unsigned GPR64DecoderTable[] = {
 368     AArch64::X0,  AArch64::X1,  AArch64::X2,  AArch64::X3,  AArch64::X4,
 369     AArch64::X5,  AArch64::X6,  AArch64::X7,  AArch64::X8,  AArch64::X9,
 370     AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
 371     AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
 372     AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
 373     AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
 374     AArch64::LR,  AArch64::XZR
 375 };
 376
 377 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
 378                                              uint64_t Addr,
 379                                              const void *Decoder) {
 380   if (RegNo > 31)
 381     return Fail;
 382
 383   unsigned Register = GPR64DecoderTable[RegNo];
 384   Inst.addOperand(MCOperand::createReg(Register));
 385   return Success;
 386 }
 387
 388 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
 389                                                uint64_t Addr,
 390                                                const void *Decoder) {
 391   if (RegNo > 31)
 392     return Fail;
 393   unsigned Register = GPR64DecoderTable[RegNo];
 394   if (Register == AArch64::XZR)
 395     Register = AArch64::SP;
 396   Inst.addOperand(MCOperand::createReg(Register));
 397   return Success;
 398 }
 399
 400 static const unsigned GPR32DecoderTable[] = {
 401     AArch64::W0,  AArch64::W1,  AArch64::W2,  AArch64::W3,  AArch64::W4,
 402     AArch64::W5,  AArch64::W6,  AArch64::W7,  AArch64::W8,  AArch64::W9,
 403     AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
 404     AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
 405     AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
 406     AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
 407     AArch64::W30, AArch64::WZR
 408 };
 409
 410 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
 411                                              uint64_t Addr,
 412                                              const void *Decoder) {
 413   if (RegNo > 31)
 414     return Fail;
 415
 416   unsigned Register = GPR32DecoderTable[RegNo];
 417   Inst.addOperand(MCOperand::createReg(Register));
 418   return Success;
 419 }
 420
 421 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
 422                                                uint64_t Addr,
 423                                                const void *Decoder) {
 424   if (RegNo > 31)
 425     return Fail;
 426
 427   unsigned Register = GPR32DecoderTable[RegNo];
 428   if (Register == AArch64::WZR)
 429     Register = AArch64::WSP;
 430   Inst.addOperand(MCOperand::createReg(Register));
 431   return Success;
 432 }
 433
 434 static const unsigned VectorDecoderTable[] = {
 435     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
 436     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
 437     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
 438     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
 439     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
 440     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
 441     AArch64::Q30, AArch64::Q31
 442 };
 443
 444 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
 445                                               uint64_t Addr,
 446                                               const void *Decoder) {
 447   if (RegNo > 31)
 448     return Fail;
 449
 450   unsigned Register = VectorDecoderTable[RegNo];
 451   Inst.addOperand(MCOperand::createReg(Register));
 452   return Success;
 453 }
 454
 455 static const unsigned QQDecoderTable[] = {
 456   AArch64::Q0_Q1,   AArch64::Q1_Q2,   AArch64::Q2_Q3,   AArch64::Q3_Q4,
 457   AArch64::Q4_Q5,   AArch64::Q5_Q6,   AArch64::Q6_Q7,   AArch64::Q7_Q8,
 458   AArch64::Q8_Q9,   AArch64::Q9_Q10,  AArch64::Q10_Q11, AArch64::Q11_Q12,
 459   AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
 460   AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
 461   AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
 462   AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
 463   AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
 464 };
 465
 466 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
 467                                           uint64_t Addr, const void *Decoder) {
 468   if (RegNo > 31)
 469     return Fail;
 470   unsigned Register = QQDecoderTable[RegNo];
 471   Inst.addOperand(MCOperand::createReg(Register));
 472   return Success;
 473 }
 474
 475 static const unsigned QQQDecoderTable[] = {
 476   AArch64::Q0_Q1_Q2,    AArch64::Q1_Q2_Q3,    AArch64::Q2_Q3_Q4,
 477   AArch64::Q3_Q4_Q5,    AArch64::Q4_Q5_Q6,    AArch64::Q5_Q6_Q7,
 478   AArch64::Q6_Q7_Q8,    AArch64::Q7_Q8_Q9,    AArch64::Q8_Q9_Q10,
 479   AArch64::Q9_Q10_Q11,  AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
 480   AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
 481   AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
 482   AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
 483   AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
 484   AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
 485   AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
 486   AArch64::Q30_Q31_Q0,  AArch64::Q31_Q0_Q1
 487 };
 488
 489 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 490                                            uint64_t Addr, const void *Decoder) {
 491   if (RegNo > 31)
 492     return Fail;
 493   unsigned Register = QQQDecoderTable[RegNo];
 494   Inst.addOperand(MCOperand::createReg(Register));
 495   return Success;
 496 }
 497
 498 static const unsigned QQQQDecoderTable[] = {
 499   AArch64::Q0_Q1_Q2_Q3,     AArch64::Q1_Q2_Q3_Q4,     AArch64::Q2_Q3_Q4_Q5,
 500   AArch64::Q3_Q4_Q5_Q6,     AArch64::Q4_Q5_Q6_Q7,     AArch64::Q5_Q6_Q7_Q8,
 501   AArch64::Q6_Q7_Q8_Q9,     AArch64::Q7_Q8_Q9_Q10,    AArch64::Q8_Q9_Q10_Q11,
 502   AArch64::Q9_Q10_Q11_Q12,  AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
 503   AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
 504   AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
 505   AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
 506   AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
 507   AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
 508   AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
 509   AArch64::Q30_Q31_Q0_Q1,   AArch64::Q31_Q0_Q1_Q2
 510 };
 511
 512 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
 513                                             uint64_t Addr,
 514                                             const void *Decoder) {
 515   if (RegNo > 31)
 516     return Fail;
 517   unsigned Register = QQQQDecoderTable[RegNo];
 518   Inst.addOperand(MCOperand::createReg(Register));
 519   return Success;
 520 }
 521
 522 static const unsigned DDDecoderTable[] = {
 523   AArch64::D0_D1,   AArch64::D1_D2,   AArch64::D2_D3,   AArch64::D3_D4,
 524   AArch64::D4_D5,   AArch64::D5_D6,   AArch64::D6_D7,   AArch64::D7_D8,
 525   AArch64::D8_D9,   AArch64::D9_D10,  AArch64::D10_D11, AArch64::D11_D12,
 526   AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
 527   AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
 528   AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
 529   AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
 530   AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
 531 };
 532
 533 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
 534                                           uint64_t Addr, const void *Decoder) {
 535   if (RegNo > 31)
 536     return Fail;
 537   unsigned Register = DDDecoderTable[RegNo];
 538   Inst.addOperand(MCOperand::createReg(Register));
 539   return Success;
 540 }
 541
 542 static const unsigned DDDDecoderTable[] = {
 543   AArch64::D0_D1_D2,    AArch64::D1_D2_D3,    AArch64::D2_D3_D4,
 544   AArch64::D3_D4_D5,    AArch64::D4_D5_D6,    AArch64::D5_D6_D7,
 545   AArch64::D6_D7_D8,    AArch64::D7_D8_D9,    AArch64::D8_D9_D10,
 546   AArch64::D9_D10_D11,  AArch64::D10_D11_D12, AArch64::D11_D12_D13,
 547   AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
 548   AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
 549   AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
 550   AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
 551   AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
 552   AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
 553   AArch64::D30_D31_D0,  AArch64::D31_D0_D1
 554 };
 555
 556 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 557                                            uint64_t Addr, const void *Decoder) {
 558   if (RegNo > 31)
 559     return Fail;
 560   unsigned Register = DDDDecoderTable[RegNo];
 561   Inst.addOperand(MCOperand::createReg(Register));
 562   return Success;
 563 }
 564
 565 static const unsigned DDDDDecoderTable[] = {
 566   AArch64::D0_D1_D2_D3,     AArch64::D1_D2_D3_D4,     AArch64::D2_D3_D4_D5,
 567   AArch64::D3_D4_D5_D6,     AArch64::D4_D5_D6_D7,     AArch64::D5_D6_D7_D8,
 568   AArch64::D6_D7_D8_D9,     AArch64::D7_D8_D9_D10,    AArch64::D8_D9_D10_D11,
 569   AArch64::D9_D10_D11_D12,  AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
 570   AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
 571   AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
 572   AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
 573   AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
 574   AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
 575   AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
 576   AArch64::D30_D31_D0_D1,   AArch64::D31_D0_D1_D2
 577 };
 578
 579 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
 580                                             uint64_t Addr,
 581                                             const void *Decoder) {
 582   if (RegNo > 31)
 583     return Fail;
 584   unsigned Register = DDDDDecoderTable[RegNo];
 585   Inst.addOperand(MCOperand::createReg(Register));
 586   return Success;
 587 }
 588
 589 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
 590                                                uint64_t Addr,
 591                                                const void *Decoder) {
 592   // scale{5} is asserted as 1 in tblgen.
 593   Imm |= 0x20;
 594   Inst.addOperand(MCOperand::createImm(64 - Imm));
 595   return Success;
 596 }
 597
 598 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
 599                                                uint64_t Addr,
 600                                                const void *Decoder) {
 601   Inst.addOperand(MCOperand::createImm(64 - Imm));
 602   return Success;
 603 }
 604
 605 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
 606                                        uint64_t Addr, const void *Decoder) {
 607   int64_t ImmVal = Imm;
 608   const AArch64Disassembler *Dis =
 609       static_cast<const AArch64Disassembler *>(Decoder);
 610
 611   // Sign-extend 19-bit immediate.
 612   if (ImmVal & (1 << (19 - 1)))
 613     ImmVal |= ~((1LL << 19) - 1);
 614
 615   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal *  4, Addr,
 616                                      Inst.getOpcode() != AArch64::LDRXl, 0, 4))
 617     Inst.addOperand(MCOperand::createImm(ImmVal));
 618   return Success;
 619 }
 620
 621 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
 622                                     uint64_t Address, const void *Decoder) {
 623   Inst.addOperand(MCOperand::createImm((Imm  >> 1) & 1));
 624   Inst.addOperand(MCOperand::createImm(Imm & 1));
 625   return Success;
 626 }
 627
 628 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 629                                             uint64_t Address,
 630                                             const void *Decoder) {
 631   Inst.addOperand(MCOperand::createImm(Imm));
 632
 633   // Every system register in the encoding space is valid with the syntax
 634   // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
 635   return Success;
 636 }
 637
 638 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
 639                                             uint64_t Address,
 640                                             const void *Decoder) {
 641   Inst.addOperand(MCOperand::createImm(Imm));
 642
 643   return Success;
 644 }
 645
 646 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 647                                               uint64_t Address,
 648                                               const void *Decoder) {
 649   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 650   // be 1 in assembly but has no other real manifestation.
 651   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 652   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 653   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 654
 655   if (IsToVec) {
 656     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 657     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 658   } else {
 659     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 660     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 661   }
 662
 663   // Add the lane
 664   Inst.addOperand(MCOperand::createImm(1));
 665
 666   return Success;
 667 }
 668
 669 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
 670                                        unsigned Add) {
 671   Inst.addOperand(MCOperand::createImm(Add - Imm));
 672   return Success;
 673 }
 674
 675 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
 676                                        unsigned Add) {
 677   Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
 678   return Success;
 679 }
 680
 681 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
 682                                          uint64_t Addr, const void *Decoder) {
 683   return DecodeVecShiftRImm(Inst, Imm, 64);
 684 }
 685
 686 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 687                                                uint64_t Addr,
 688                                                const void *Decoder) {
 689   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
 690 }
 691
 692 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
 693                                          uint64_t Addr, const void *Decoder) {
 694   return DecodeVecShiftRImm(Inst, Imm, 32);
 695 }
 696
 697 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 698                                                uint64_t Addr,
 699                                                const void *Decoder) {
 700   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
 701 }
 702
 703 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
 704                                          uint64_t Addr, const void *Decoder) {
 705   return DecodeVecShiftRImm(Inst, Imm, 16);
 706 }
 707
 708 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
 709                                                uint64_t Addr,
 710                                                const void *Decoder) {
 711   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
 712 }
 713
 714 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
 715                                         uint64_t Addr, const void *Decoder) {
 716   return DecodeVecShiftRImm(Inst, Imm, 8);
 717 }
 718
 719 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
 720                                          uint64_t Addr, const void *Decoder) {
 721   return DecodeVecShiftLImm(Inst, Imm, 64);
 722 }
 723
 724 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
 725                                          uint64_t Addr, const void *Decoder) {
 726   return DecodeVecShiftLImm(Inst, Imm, 32);
 727 }
 728
 729 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
 730                                          uint64_t Addr, const void *Decoder) {
 731   return DecodeVecShiftLImm(Inst, Imm, 16);
 732 }
 733
 734 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
 735                                         uint64_t Addr, const void *Decoder) {
 736   return DecodeVecShiftLImm(Inst, Imm, 8);
 737 }
 738
 739 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
 740                                                    uint32_t insn, uint64_t Addr,
 741                                                    const void *Decoder) {
 742   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 743   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 744   unsigned Rm = fieldFromInstruction(insn, 16, 5);
 745   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
 746   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
 747   unsigned shift = (shiftHi << 6) | shiftLo;
 748   switch (Inst.getOpcode()) {
 749   default:
 750     return Fail;
 751   case AArch64::ADDWrs:
 752   case AArch64::ADDSWrs:
 753   case AArch64::SUBWrs:
 754   case AArch64::SUBSWrs:
 755     // if shift == '11' then ReservedValue()
 756     if (shiftHi == 0x3)
 757       return Fail;
 758     // Deliberate fallthrough
 759   case AArch64::ANDWrs:
 760   case AArch64::ANDSWrs:
 761   case AArch64::BICWrs:
 762   case AArch64::BICSWrs:
 763   case AArch64::ORRWrs:
 764   case AArch64::ORNWrs:
 765   case AArch64::EORWrs:
 766   case AArch64::EONWrs: {
 767     // if sf == '0' and imm6<5> == '1' then ReservedValue()
 768     if (shiftLo >> 5 == 1)
 769       return Fail;
 770     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 771     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
 772     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 773     break;
 774   }
 775   case AArch64::ADDXrs:
 776   case AArch64::ADDSXrs:
 777   case AArch64::SUBXrs:
 778   case AArch64::SUBSXrs:
 779     // if shift == '11' then ReservedValue()
 780     if (shiftHi == 0x3)
 781       return Fail;
 782     // Deliberate fallthrough
 783   case AArch64::ANDXrs:
 784   case AArch64::ANDSXrs:
 785   case AArch64::BICXrs:
 786   case AArch64::BICSXrs:
 787   case AArch64::ORRXrs:
 788   case AArch64::ORNXrs:
 789   case AArch64::EORXrs:
 790   case AArch64::EONXrs:
 791     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 792     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
 793     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
 794     break;
 795   }
 796
 797   Inst.addOperand(MCOperand::createImm(shift));
 798   return Success;
 799 }
 800
 801 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
 802                                              uint64_t Addr,
 803                                              const void *Decoder) {
 804   unsigned Rd = fieldFromInstruction(insn, 0, 5);
 805   unsigned imm = fieldFromInstruction(insn, 5, 16);
 806   unsigned shift = fieldFromInstruction(insn, 21, 2);
 807   shift <<= 4;
 808   switch (Inst.getOpcode()) {
 809   default:
 810     return Fail;
 811   case AArch64::MOVZWi:
 812   case AArch64::MOVNWi:
 813   case AArch64::MOVKWi:
 814     if (shift & (1U << 5))
 815       return Fail;
 816     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
 817     break;
 818   case AArch64::MOVZXi:
 819   case AArch64::MOVNXi:
 820   case AArch64::MOVKXi:
 821     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
 822     break;
 823   }
 824
 825   if (Inst.getOpcode() == AArch64::MOVKWi ||
 826       Inst.getOpcode() == AArch64::MOVKXi)
 827     Inst.addOperand(Inst.getOperand(0));
 828
 829   Inst.addOperand(MCOperand::createImm(imm));
 830   Inst.addOperand(MCOperand::createImm(shift));
 831   return Success;
 832 }
 833
 834 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
 835                                                   uint32_t insn, uint64_t Addr,
 836                                                   const void *Decoder) {
 837   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 838   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 839   unsigned offset = fieldFromInstruction(insn, 10, 12);
 840   const AArch64Disassembler *Dis =
 841       static_cast<const AArch64Disassembler *>(Decoder);
 842
 843   switch (Inst.getOpcode()) {
 844   default:
 845     return Fail;
 846   case AArch64::PRFMui:
 847     // Rt is an immediate in prefetch.
 848     Inst.addOperand(MCOperand::createImm(Rt));
 849     break;
 850   case AArch64::STRBBui:
 851   case AArch64::LDRBBui:
 852   case AArch64::LDRSBWui:
 853   case AArch64::STRHHui:
 854   case AArch64::LDRHHui:
 855   case AArch64::LDRSHWui:
 856   case AArch64::STRWui:
 857   case AArch64::LDRWui:
 858     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
 859     break;
 860   case AArch64::LDRSBXui:
 861   case AArch64::LDRSHXui:
 862   case AArch64::LDRSWui:
 863   case AArch64::STRXui:
 864   case AArch64::LDRXui:
 865     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
 866     break;
 867   case AArch64::LDRQui:
 868   case AArch64::STRQui:
 869     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
 870     break;
 871   case AArch64::LDRDui:
 872   case AArch64::STRDui:
 873     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
 874     break;
 875   case AArch64::LDRSui:
 876   case AArch64::STRSui:
 877     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
 878     break;
 879   case AArch64::LDRHui:
 880   case AArch64::STRHui:
 881     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
 882     break;
 883   case AArch64::LDRBui:
 884   case AArch64::STRBui:
 885     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
 886     break;
 887   }
 888
 889   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 890   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
 891     Inst.addOperand(MCOperand::createImm(offset));
 892   return Success;
 893 }
 894
 895 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
 896                                                 uint32_t insn, uint64_t Addr,
 897                                                 const void *Decoder) {
 898   unsigned Rt = fieldFromInstruction(insn, 0, 5);
 899   unsigned Rn = fieldFromInstruction(insn, 5, 5);
 900   int64_t offset = fieldFromInstruction(insn, 12, 9);
 901
 902   // offset is a 9-bit signed immediate, so sign extend it to
 903   // fill the unsigned.
 904   if (offset & (1 << (9 - 1)))
 905     offset |= ~((1LL << 9) - 1);
 906
 907   // First operand is always the writeback to the address register, if needed.
 908   switch (Inst.getOpcode()) {
 909   default:
 910     break;
 911   case AArch64::LDRSBWpre:
 912   case AArch64::LDRSHWpre:
 913   case AArch64::STRBBpre:
 914   case AArch64::LDRBBpre:
 915   case AArch64::STRHHpre:
 916   case AArch64::LDRHHpre:
 917   case AArch64::STRWpre:
 918   case AArch64::LDRWpre:
 919   case AArch64::LDRSBWpost:
 920   case AArch64::LDRSHWpost:
 921   case AArch64::STRBBpost:
 922   case AArch64::LDRBBpost:
 923   case AArch64::STRHHpost:
 924   case AArch64::LDRHHpost:
 925   case AArch64::STRWpost:
 926   case AArch64::LDRWpost:
 927   case AArch64::LDRSBXpre:
 928   case AArch64::LDRSHXpre:
 929   case AArch64::STRXpre:
 930   case AArch64::LDRSWpre:
 931   case AArch64::LDRXpre:
 932   case AArch64::LDRSBXpost:
 933   case AArch64::LDRSHXpost:
 934   case AArch64::STRXpost:
 935   case AArch64::LDRSWpost:
 936   case AArch64::LDRXpost:
 937   case AArch64::LDRQpre:
 938   case AArch64::STRQpre:
 939   case AArch64::LDRQpost:
 940   case AArch64::STRQpost:
 941   case AArch64::LDRDpre:
 942   case AArch64::STRDpre:
 943   case AArch64::LDRDpost:
 944   case AArch64::STRDpost:
 945   case AArch64::LDRSpre:
 946   case AArch64::STRSpre:
 947   case AArch64::LDRSpost:
 948   case AArch64::STRSpost:
 949   case AArch64::LDRHpre:
 950   case AArch64::STRHpre:
 951   case AArch64::LDRHpost:
 952   case AArch64::STRHpost:
 953   case AArch64::LDRBpre:
 954   case AArch64::STRBpre:
 955   case AArch64::LDRBpost:
 956   case AArch64::STRBpost:
 957     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 958     break;
 959   }
 960
 961   switch (Inst.getOpcode()) {
 962   default:
 963     return Fail;
 964   case AArch64::PRFUMi:
 965     // Rt is an immediate in prefetch.
 966     Inst.addOperand(MCOperand::createImm(Rt));
 967     break;
 968   case AArch64::STURBBi:
 969   case AArch64::LDURBBi:
 970   case AArch64::LDURSBWi:
 971   case AArch64::STURHHi:
 972   case AArch64::LDURHHi:
 973   case AArch64::LDURSHWi:
 974   case AArch64::STURWi:
 975   case AArch64::LDURWi:
 976   case AArch64::LDTRSBWi:
 977   case AArch64::LDTRSHWi:
 978   case AArch64::STTRWi:
 979   case AArch64::LDTRWi:
 980   case AArch64::STTRHi:
 981   case AArch64::LDTRHi:
 982   case AArch64::LDTRBi:
 983   case AArch64::STTRBi:
 984   case AArch64::LDRSBWpre:
 985   case AArch64::LDRSHWpre:
 986   case AArch64::STRBBpre:
 987   case AArch64::LDRBBpre:
 988   case AArch64::STRHHpre:
 989   case AArch64::LDRHHpre:
 990   case AArch64::STRWpre:
 991   case AArch64::LDRWpre:
 992   case AArch64::LDRSBWpost:
 993   case AArch64::LDRSHWpost:
 994   case AArch64::STRBBpost:
 995   case AArch64::LDRBBpost:
 996   case AArch64::STRHHpost:
 997   case AArch64::LDRHHpost:
 998   case AArch64::STRWpost:
 999   case AArch64::LDRWpost:
1000     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1001     break;
1002   case AArch64::LDURSBXi:
1003   case AArch64::LDURSHXi:
1004   case AArch64::LDURSWi:
1005   case AArch64::STURXi:
1006   case AArch64::LDURXi:
1007   case AArch64::LDTRSBXi:
1008   case AArch64::LDTRSHXi:
1009   case AArch64::LDTRSWi:
1010   case AArch64::STTRXi:
1011   case AArch64::LDTRXi:
1012   case AArch64::LDRSBXpre:
1013   case AArch64::LDRSHXpre:
1014   case AArch64::STRXpre:
1015   case AArch64::LDRSWpre:
1016   case AArch64::LDRXpre:
1017   case AArch64::LDRSBXpost:
1018   case AArch64::LDRSHXpost:
1019   case AArch64::STRXpost:
1020   case AArch64::LDRSWpost:
1021   case AArch64::LDRXpost:
1022     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1023     break;
1024   case AArch64::LDURQi:
1025   case AArch64::STURQi:
1026   case AArch64::LDRQpre:
1027   case AArch64::STRQpre:
1028   case AArch64::LDRQpost:
1029   case AArch64::STRQpost:
1030     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1031     break;
1032   case AArch64::LDURDi:
1033   case AArch64::STURDi:
1034   case AArch64::LDRDpre:
1035   case AArch64::STRDpre:
1036   case AArch64::LDRDpost:
1037   case AArch64::STRDpost:
1038     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1039     break;
1040   case AArch64::LDURSi:
1041   case AArch64::STURSi:
1042   case AArch64::LDRSpre:
1043   case AArch64::STRSpre:
1044   case AArch64::LDRSpost:
1045   case AArch64::STRSpost:
1046     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1047     break;
1048   case AArch64::LDURHi:
1049   case AArch64::STURHi:
1050   case AArch64::LDRHpre:
1051   case AArch64::STRHpre:
1052   case AArch64::LDRHpost:
1053   case AArch64::STRHpost:
1054     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1055     break;
1056   case AArch64::LDURBi:
1057   case AArch64::STURBi:
1058   case AArch64::LDRBpre:
1059   case AArch64::STRBpre:
1060   case AArch64::LDRBpost:
1061   case AArch64::STRBpost:
1062     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1063     break;
1064   }
1065
1066   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1067   Inst.addOperand(MCOperand::createImm(offset));
1068
1069   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1070   bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1071   bool IsFP = fieldFromInstruction(insn, 26, 1);
1072
1073   // Cannot write back to a transfer register (but xzr != sp).
1074   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1075     return SoftFail;
1076
1077   return Success;
1078 }
1079
1080 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
1081                                                    uint32_t insn, uint64_t Addr,
1082                                                    const void *Decoder) {
1083   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1084   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1085   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1086   unsigned Rs = fieldFromInstruction(insn, 16, 5);
1087
1088   unsigned Opcode = Inst.getOpcode();
1089   switch (Opcode) {
1090   default:
1091     return Fail;
1092   case AArch64::STLXRW:
1093   case AArch64::STLXRB:
1094   case AArch64::STLXRH:
1095   case AArch64::STXRW:
1096   case AArch64::STXRB:
1097   case AArch64::STXRH:
1098     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1099   // FALLTHROUGH
1100   case AArch64::LDARW:
1101   case AArch64::LDARB:
1102   case AArch64::LDARH:
1103   case AArch64::LDAXRW:
1104   case AArch64::LDAXRB:
1105   case AArch64::LDAXRH:
1106   case AArch64::LDXRW:
1107   case AArch64::LDXRB:
1108   case AArch64::LDXRH:
1109   case AArch64::STLRW:
1110   case AArch64::STLRB:
1111   case AArch64::STLRH:
1112   case AArch64::STLLRW:
1113   case AArch64::STLLRB:
1114   case AArch64::STLLRH:
1115   case AArch64::LDLARW:
1116   case AArch64::LDLARB:
1117   case AArch64::LDLARH:
1118     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1119     break;
1120   case AArch64::STLXRX:
1121   case AArch64::STXRX:
1122     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1123   // FALLTHROUGH
1124   case AArch64::LDARX:
1125   case AArch64::LDAXRX:
1126   case AArch64::LDXRX:
1127   case AArch64::STLRX:
1128   case AArch64::LDLARX:
1129   case AArch64::STLLRX:
1130     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1131     break;
1132   case AArch64::STLXPW:
1133   case AArch64::STXPW:
1134     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1135   // FALLTHROUGH
1136   case AArch64::LDAXPW:
1137   case AArch64::LDXPW:
1138     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1139     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1140     break;
1141   case AArch64::STLXPX:
1142   case AArch64::STXPX:
1143     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1144   // FALLTHROUGH
1145   case AArch64::LDAXPX:
1146   case AArch64::LDXPX:
1147     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1148     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1149     break;
1150   }
1151
1152   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1153
1154   // You shouldn't load to the same register twice in an instruction...
1155   if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1156        Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1157       Rt == Rt2)
1158     return SoftFail;
1159
1160   return Success;
1161 }
1162
1163 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1164                                               uint64_t Addr,
1165                                               const void *Decoder) {
1166   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1167   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1168   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1169   int64_t offset = fieldFromInstruction(insn, 15, 7);
1170   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1171
1172   // offset is a 7-bit signed immediate, so sign extend it to
1173   // fill the unsigned.
1174   if (offset & (1 << (7 - 1)))
1175     offset |= ~((1LL << 7) - 1);
1176
1177   unsigned Opcode = Inst.getOpcode();
1178   bool NeedsDisjointWritebackTransfer = false;
1179
1180   // First operand is always writeback of base register.
1181   switch (Opcode) {
1182   default:
1183     break;
1184   case AArch64::LDPXpost:
1185   case AArch64::STPXpost:
1186   case AArch64::LDPSWpost:
1187   case AArch64::LDPXpre:
1188   case AArch64::STPXpre:
1189   case AArch64::LDPSWpre:
1190   case AArch64::LDPWpost:
1191   case AArch64::STPWpost:
1192   case AArch64::LDPWpre:
1193   case AArch64::STPWpre:
1194   case AArch64::LDPQpost:
1195   case AArch64::STPQpost:
1196   case AArch64::LDPQpre:
1197   case AArch64::STPQpre:
1198   case AArch64::LDPDpost:
1199   case AArch64::STPDpost:
1200   case AArch64::LDPDpre:
1201   case AArch64::STPDpre:
1202   case AArch64::LDPSpost:
1203   case AArch64::STPSpost:
1204   case AArch64::LDPSpre:
1205   case AArch64::STPSpre:
1206     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1207     break;
1208   }
1209
1210   switch (Opcode) {
1211   default:
1212     return Fail;
1213   case AArch64::LDPXpost:
1214   case AArch64::STPXpost:
1215   case AArch64::LDPSWpost:
1216   case AArch64::LDPXpre:
1217   case AArch64::STPXpre:
1218   case AArch64::LDPSWpre:
1219     NeedsDisjointWritebackTransfer = true;
1220     // Fallthrough
1221   case AArch64::LDNPXi:
1222   case AArch64::STNPXi:
1223   case AArch64::LDPXi:
1224   case AArch64::STPXi:
1225   case AArch64::LDPSWi:
1226     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1227     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1228     break;
1229   case AArch64::LDPWpost:
1230   case AArch64::STPWpost:
1231   case AArch64::LDPWpre:
1232   case AArch64::STPWpre:
1233     NeedsDisjointWritebackTransfer = true;
1234     // Fallthrough
1235   case AArch64::LDNPWi:
1236   case AArch64::STNPWi:
1237   case AArch64::LDPWi:
1238   case AArch64::STPWi:
1239     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1240     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1241     break;
1242   case AArch64::LDNPQi:
1243   case AArch64::STNPQi:
1244   case AArch64::LDPQpost:
1245   case AArch64::STPQpost:
1246   case AArch64::LDPQi:
1247   case AArch64::STPQi:
1248   case AArch64::LDPQpre:
1249   case AArch64::STPQpre:
1250     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1251     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1252     break;
1253   case AArch64::LDNPDi:
1254   case AArch64::STNPDi:
1255   case AArch64::LDPDpost:
1256   case AArch64::STPDpost:
1257   case AArch64::LDPDi:
1258   case AArch64::STPDi:
1259   case AArch64::LDPDpre:
1260   case AArch64::STPDpre:
1261     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1262     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1263     break;
1264   case AArch64::LDNPSi:
1265   case AArch64::STNPSi:
1266   case AArch64::LDPSpost:
1267   case AArch64::STPSpost:
1268   case AArch64::LDPSi:
1269   case AArch64::STPSi:
1270   case AArch64::LDPSpre:
1271   case AArch64::STPSpre:
1272     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1273     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1274     break;
1275   }
1276
1277   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1278   Inst.addOperand(MCOperand::createImm(offset));
1279
1280   // You shouldn't load to the same register twice in an instruction...
1281   if (IsLoad && Rt == Rt2)
1282     return SoftFail;
1283
1284   // ... or do any operation that writes-back to a transfer register. But note
1285   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1286   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1287     return SoftFail;
1288
1289   return Success;
1290 }
1291
1292 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1293                                                 uint32_t insn, uint64_t Addr,
1294                                                 const void *Decoder) {
1295   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1296   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1297   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1298   unsigned extend = fieldFromInstruction(insn, 10, 6);
1299
1300   unsigned shift = extend & 0x7;
1301   if (shift > 4)
1302     return Fail;
1303
1304   switch (Inst.getOpcode()) {
1305   default:
1306     return Fail;
1307   case AArch64::ADDWrx:
1308   case AArch64::SUBWrx:
1309     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1310     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1311     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1312     break;
1313   case AArch64::ADDSWrx:
1314   case AArch64::SUBSWrx:
1315     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1316     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1317     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1318     break;
1319   case AArch64::ADDXrx:
1320   case AArch64::SUBXrx:
1321     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1322     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1323     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1324     break;
1325   case AArch64::ADDSXrx:
1326   case AArch64::SUBSXrx:
1327     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1328     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1329     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1330     break;
1331   case AArch64::ADDXrx64:
1332   case AArch64::SUBXrx64:
1333     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1334     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1335     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1336     break;
1337   case AArch64::SUBSXrx64:
1338   case AArch64::ADDSXrx64:
1339     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1340     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1341     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1342     break;
1343   }
1344
1345   Inst.addOperand(MCOperand::createImm(extend));
1346   return Success;
1347 }
1348
1349 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1350                                                 uint32_t insn, uint64_t Addr,
1351                                                 const void *Decoder) {
1352   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1353   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1354   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1355   unsigned imm;
1356
1357   if (Datasize) {
1358     if (Inst.getOpcode() == AArch64::ANDSXri)
1359       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1360     else
1361       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1362     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1363     imm = fieldFromInstruction(insn, 10, 13);
1364     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1365       return Fail;
1366   } else {
1367     if (Inst.getOpcode() == AArch64::ANDSWri)
1368       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1369     else
1370       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1371     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1372     imm = fieldFromInstruction(insn, 10, 12);
1373     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1374       return Fail;
1375   }
1376   Inst.addOperand(MCOperand::createImm(imm));
1377   return Success;
1378 }
1379
1380 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1381                                             uint64_t Addr,
1382                                             const void *Decoder) {
1383   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1384   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1385   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1386   imm |= fieldFromInstruction(insn, 5, 5);
1387
1388   if (Inst.getOpcode() == AArch64::MOVID)
1389     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1390   else
1391     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1392
1393   Inst.addOperand(MCOperand::createImm(imm));
1394
1395   switch (Inst.getOpcode()) {
1396   default:
1397     break;
1398   case AArch64::MOVIv4i16:
1399   case AArch64::MOVIv8i16:
1400   case AArch64::MVNIv4i16:
1401   case AArch64::MVNIv8i16:
1402   case AArch64::MOVIv2i32:
1403   case AArch64::MOVIv4i32:
1404   case AArch64::MVNIv2i32:
1405   case AArch64::MVNIv4i32:
1406     Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1407     break;
1408   case AArch64::MOVIv2s_msl:
1409   case AArch64::MOVIv4s_msl:
1410   case AArch64::MVNIv2s_msl:
1411   case AArch64::MVNIv4s_msl:
1412     Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
1413     break;
1414   }
1415
1416   return Success;
1417 }
1418
1419 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1420                                                 uint32_t insn, uint64_t Addr,
1421                                                 const void *Decoder) {
1422   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1423   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1424   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1425   imm |= fieldFromInstruction(insn, 5, 5);
1426
1427   // Tied operands added twice.
1428   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1429   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1430
1431   Inst.addOperand(MCOperand::createImm(imm));
1432   Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1433
1434   return Success;
1435 }
1436
1437 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1438                                          uint64_t Addr, const void *Decoder) {
1439   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1440   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1441   imm |= fieldFromInstruction(insn, 29, 2);
1442   const AArch64Disassembler *Dis =
1443       static_cast<const AArch64Disassembler *>(Decoder);
1444
1445   // Sign-extend the 21-bit immediate.
1446   if (imm & (1 << (21 - 1)))
1447     imm |= ~((1LL << 21) - 1);
1448
1449   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1450   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1451     Inst.addOperand(MCOperand::createImm(imm));
1452
1453   return Success;
1454 }
1455
1456 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1457                                         uint64_t Addr, const void *Decoder) {
1458   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1459   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1460   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1461   unsigned S = fieldFromInstruction(insn, 29, 1);
1462   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1463
1464   unsigned ShifterVal = (Imm >> 12) & 3;
1465   unsigned ImmVal = Imm & 0xFFF;
1466   const AArch64Disassembler *Dis =
1467       static_cast<const AArch64Disassembler *>(Decoder);
1468
1469   if (ShifterVal != 0 && ShifterVal != 1)
1470     return Fail;
1471
1472   if (Datasize) {
1473     if (Rd == 31 && !S)
1474       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1475     else
1476       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1477     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1478   } else {
1479     if (Rd == 31 && !S)
1480       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1481     else
1482       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1483     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1484   }
1485
1486   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1487     Inst.addOperand(MCOperand::createImm(ImmVal));
1488   Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1489   return Success;
1490 }
1491
1492 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1493                                               uint64_t Addr,
1494                                               const void *Decoder) {
1495   int64_t imm = fieldFromInstruction(insn, 0, 26);
1496   const AArch64Disassembler *Dis =
1497       static_cast<const AArch64Disassembler *>(Decoder);
1498
1499   // Sign-extend the 26-bit immediate.
1500   if (imm & (1 << (26 - 1)))
1501     imm |= ~((1LL << 26) - 1);
1502
1503   if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1504     Inst.addOperand(MCOperand::createImm(imm));
1505
1506   return Success;
1507 }
1508
1509 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1510                                                   uint32_t insn, uint64_t Addr,
1511                                                   const void *Decoder) {
1512   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1513   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1514   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1515
1516   uint64_t pstate_field = (op1 << 3) | op2;
1517
1518   Inst.addOperand(MCOperand::createImm(pstate_field));
1519   Inst.addOperand(MCOperand::createImm(crm));
1520
1521   bool ValidNamed;
1522   const AArch64Disassembler *Dis =
1523       static_cast<const AArch64Disassembler *>(Decoder);
1524   (void)AArch64PState::PStateMapper().toString(pstate_field,
1525       Dis->getSubtargetInfo().getFeatureBits(), ValidNamed);
1526
1527   return ValidNamed ? Success : Fail;
1528 }
1529
1530 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1531                                         uint64_t Addr, const void *Decoder) {
1532   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1533   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1534   bit |= fieldFromInstruction(insn, 19, 5);
1535   int64_t dst = fieldFromInstruction(insn, 5, 14);
1536   const AArch64Disassembler *Dis =
1537       static_cast<const AArch64Disassembler *>(Decoder);
1538
1539   // Sign-extend 14-bit immediate.
1540   if (dst & (1 << (14 - 1)))
1541     dst |= ~((1LL << 14) - 1);
1542
1543   if (fieldFromInstruction(insn, 31, 1) == 0)
1544     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1545   else
1546     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1547   Inst.addOperand(MCOperand::createImm(bit));
1548   if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1549     Inst.addOperand(MCOperand::createImm(dst));
1550
1551   return Success;
1552 }
1553
1554 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1555                                                         unsigned RegClassID,
1556                                                         unsigned RegNo,
1557                                                         uint64_t Addr,
1558                                                         const void *Decoder) {
1559   // Register number must be even (see CASP instruction)
1560   if (RegNo & 0x1)
1561     return Fail;
1562
1563   unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1564   Inst.addOperand(MCOperand::createReg(Register));
1565   return Success;
1566 }
1567
1568 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1569                                                       unsigned RegNo,
1570                                                       uint64_t Addr,
1571                                                       const void *Decoder) {
1572   return DecodeGPRSeqPairsClassRegisterClass(Inst,
1573                                              AArch64::WSeqPairsClassRegClassID,
1574                                              RegNo, Addr, Decoder);
1575 }
1576
1577 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1578                                                       unsigned RegNo,
1579                                                       uint64_t Addr,
1580                                                       const void *Decoder) {
1581   return DecodeGPRSeqPairsClassRegisterClass(Inst,
1582                                              AArch64::XSeqPairsClassRegClassID,
1583                                              RegNo, Addr, Decoder);
1584 }