1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/Target/TargetLowering.h"
26 namespace AArch64ISD {
28 enum NodeType : unsigned {
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
31 CALL, // Function call.
33 // Produces the full sequence of instructions for getting the thread pointer
34 // offset of a variable into X0, using the TLSDesc model.
36 ADRP, // Page address of a TargetGlobalAddress operand.
37 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
38 LOADgot, // Load from automatically generated descriptor (e.g. Global
39 // Offset Table, TLS record).
40 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
41 BRCOND, // Conditional branch instruction; "b.cond".
43 FCSEL, // Conditional move instruction.
44 CSINV, // Conditional select invert.
45 CSNEG, // Conditional select negate.
46 CSINC, // Conditional select increment.
48 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
52 SBC, // adc, sbc instructions
54 // Arithmetic instructions which write flags.
61 // Conditional compares. Operands: left,right,falsecc,cc,flags
66 // Floating point comparison
72 // Scalar-to-vector duplication
79 // Vector immedate moves
88 // Vector immediate ops
92 // Vector bit select: similar to ISD::VSELECT but not all bits within an
93 // element must be identical.
96 // Vector arithmetic negation
111 // Vector shift by scalar
116 // Vector shift by scalar (again)
123 // Vector comparisons
133 // Vector zero comparisons
145 // Vector across-lanes addition
146 // Only the lower result lane is defined.
150 // Vector across-lanes min/max
151 // Only the lower result lane is defined.
157 // Vector bitwise negation
160 // Vector bitwise selection
163 // Compare-and-branch
172 // Custom prefetch handling
175 // {s|u}int to FP within a FP register.
179 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
180 /// world w.r.t vectors; which causes additional REV instructions to be
181 /// generated to compensate for the byte-swapping. But sometimes we do
182 /// need to re-interpret the data in SIMD vector registers in big-endian
183 /// mode without emitting such REV instructions.
189 // NEON Load/Store with post-increment base updates
190 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
215 } // end namespace AArch64ISD
217 class AArch64Subtarget;
218 class AArch64TargetMachine;
220 class AArch64TargetLowering : public TargetLowering {
222 explicit AArch64TargetLowering(const TargetMachine &TM,
223 const AArch64Subtarget &STI);
225 /// Selects the correct CCAssignFn for a given CallingConvention value.
226 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
228 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
229 /// Mask are known to be either zero or one and return them in the
230 /// KnownZero/KnownOne bitsets.
231 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
232 APInt &KnownOne, const SelectionDAG &DAG,
233 unsigned Depth = 0) const override;
235 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
237 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
238 /// unaligned memory accesses of the specified type.
239 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
241 bool *Fast = nullptr) const override;
243 /// LowerOperation - Provide custom lowering hooks for some operations.
244 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
250 /// getFunctionAlignment - Return the Log2 alignment of this function.
251 unsigned getFunctionAlignment(const Function *F) const;
253 /// Returns true if a cast between SrcAS and DestAS is a noop.
254 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
255 // Addrspacecasts are always noops.
259 /// createFastISel - This method returns a target specific FastISel object,
260 /// or null if the target does not support "fast" ISel.
261 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
262 const TargetLibraryInfo *libInfo) const override;
264 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
266 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
268 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
269 /// codegen'd directly, or if it should be stack expanded.
270 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
272 /// getSetCCResultType - Return the ISD::SETCC ValueType
273 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
274 EVT VT) const override;
276 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
278 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
279 MachineBasicBlock *BB) const;
282 EmitInstrWithCustomInserter(MachineInstr *MI,
283 MachineBasicBlock *MBB) const override;
285 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
286 unsigned Intrinsic) const override;
288 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
289 bool isTruncateFree(EVT VT1, EVT VT2) const override;
291 bool isProfitableToHoist(Instruction *I) const override;
293 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
294 bool isZExtFree(EVT VT1, EVT VT2) const override;
295 bool isZExtFree(SDValue Val, EVT VT2) const override;
297 bool hasPairedLoad(Type *LoadedType,
298 unsigned &RequiredAligment) const override;
299 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
301 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
303 bool lowerInterleavedLoad(LoadInst *LI,
304 ArrayRef<ShuffleVectorInst *> Shuffles,
305 ArrayRef<unsigned> Indices,
306 unsigned Factor) const override;
307 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
308 unsigned Factor) const override;
310 bool isLegalAddImmediate(int64_t) const override;
311 bool isLegalICmpImmediate(int64_t) const override;
313 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
314 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
315 MachineFunction &MF) const override;
317 /// isLegalAddressingMode - Return true if the addressing mode represented
318 /// by AM is legal for this target, for a load/store of the specified type.
319 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
320 unsigned AS) const override;
322 /// \brief Return the cost of the scaling factor used in the addressing
323 /// mode represented by AM for this target, for a load/store
324 /// of the specified type.
325 /// If the AM is supported, the return value must be >= 0.
326 /// If the AM is not supported, it returns a negative value.
327 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
328 unsigned AS) const override;
330 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
331 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
332 /// expanded to FMAs when this method returns true, otherwise fmuladd is
333 /// expanded to fmul + fadd.
334 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
336 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
338 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
339 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
341 /// \brief Returns true if it is beneficial to convert a load of a constant
342 /// to just the constant itself.
343 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
344 Type *Ty) const override;
346 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
347 AtomicOrdering Ord) const override;
348 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
349 Value *Addr, AtomicOrdering Ord) const override;
351 TargetLoweringBase::AtomicExpansionKind
352 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
353 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
354 TargetLoweringBase::AtomicExpansionKind
355 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
357 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
359 bool useLoadStackGuardNode() const override;
360 TargetLoweringBase::LegalizeTypeAction
361 getPreferredVectorAction(EVT VT) const override;
364 bool isExtFreeImpl(const Instruction *Ext) const override;
366 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
367 /// make the right decision when generating code for different targets.
368 const AArch64Subtarget *Subtarget;
370 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
371 void addDRTypeForNEON(MVT VT);
372 void addQRTypeForNEON(MVT VT);
375 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
376 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
378 SmallVectorImpl<SDValue> &InVals) const override;
380 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
381 SmallVectorImpl<SDValue> &InVals) const override;
383 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
384 CallingConv::ID CallConv, bool isVarArg,
385 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
386 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
387 bool isThisReturn, SDValue ThisVal) const;
389 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
391 bool isEligibleForTailCallOptimization(
392 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
393 bool isCalleeStructRet, bool isCallerStructRet,
394 const SmallVectorImpl<ISD::OutputArg> &Outs,
395 const SmallVectorImpl<SDValue> &OutVals,
396 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
398 /// Finds the incoming stack arguments which overlap the given fixed stack
399 /// object and incorporates their load into the current chain. This prevents
400 /// an upcoming store from clobbering the stack argument before it's used.
401 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
402 MachineFrameInfo *MFI, int ClobberedFI) const;
404 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
406 bool IsTailCallConvention(CallingConv::ID CallCC) const;
408 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
409 SDValue &Chain) const;
411 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
413 const SmallVectorImpl<ISD::OutputArg> &Outs,
414 LLVMContext &Context) const override;
416 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
417 const SmallVectorImpl<ISD::OutputArg> &Outs,
418 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
419 SelectionDAG &DAG) const override;
421 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
426 SelectionDAG &DAG) const;
427 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
432 SDValue TVal, SDValue FVal, SDLoc dl,
433 SelectionDAG &DAG) const;
434 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
450 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
456 RTLIB::Libcall Call) const;
457 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
467 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
468 std::vector<SDNode *> *Created) const override;
469 unsigned combineRepeatedFPDivisors() const override;
471 ConstraintType getConstraintType(StringRef Constraint) const override;
472 unsigned getRegisterByName(const char* RegName, EVT VT,
473 SelectionDAG &DAG) const override;
475 /// Examine constraint string and operand type and determine a weight value.
476 /// The operand object must already have been set up with the operand type.
478 getSingleConstraintMatchWeight(AsmOperandInfo &info,
479 const char *constraint) const override;
481 std::pair<unsigned, const TargetRegisterClass *>
482 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
483 StringRef Constraint, MVT VT) const override;
484 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
485 std::vector<SDValue> &Ops,
486 SelectionDAG &DAG) const override;
488 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
489 if (ConstraintCode == "Q")
490 return InlineAsm::Constraint_Q;
491 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
492 // followed by llvm_unreachable so we'll leave them unimplemented in
493 // the backend for now.
494 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
497 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
498 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
499 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
500 ISD::MemIndexedMode &AM, bool &IsInc,
501 SelectionDAG &DAG) const;
502 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
503 ISD::MemIndexedMode &AM,
504 SelectionDAG &DAG) const override;
505 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
506 SDValue &Offset, ISD::MemIndexedMode &AM,
507 SelectionDAG &DAG) const override;
509 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
510 SelectionDAG &DAG) const override;
512 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
513 CallingConv::ID CallConv,
514 bool isVarArg) const override;
516 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
520 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
521 const TargetLibraryInfo *libInfo);
522 } // end namespace AArch64
524 } // end namespace llvm