1 //===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64FrameLowering.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64InstrInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/MC/MachineLocation.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
32 void AArch64FrameLowering::splitSPAdjustments(uint64_t Total,
34 uint64_t &Residual) const {
35 // 0x1f0 here is a pessimistic (i.e. realistic) boundary: x-register LDP
36 // instructions have a 7-bit signed immediate scaled by 8, giving a reach of
37 // 0x1f8, but stack adjustment should always be a multiple of 16.
43 Residual = Total - Initial;
47 void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
48 AArch64MachineFunctionInfo *FuncInfo =
49 MF.getInfo<AArch64MachineFunctionInfo>();
50 MachineBasicBlock &MBB = MF.front();
51 MachineBasicBlock::iterator MBBI = MBB.begin();
52 MachineFrameInfo *MFI = MF.getFrameInfo();
53 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
54 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
56 MachineModuleInfo &MMI = MF.getMMI();
57 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
58 bool NeedsFrameMoves = MMI.hasDebugInfo()
59 || MF.getFunction()->needsUnwindTableEntry();
61 uint64_t NumInitialBytes, NumResidualBytes;
63 // Currently we expect the stack to be laid out by
64 // sub sp, sp, #initial
65 // stp x29, x30, [sp, #offset]
67 // str xxx, [sp, #offset]
68 // sub sp, sp, #rest (possibly via extra instructions).
69 if (MFI->getCalleeSavedInfo().size()) {
70 // If there are callee-saved registers, we want to store them efficiently as
71 // a block, and virtual base assignment happens too early to do it for us so
72 // we adjust the stack in two phases: first just for callee-saved fiddling,
73 // then to allocate the rest of the frame.
74 splitSPAdjustments(MFI->getStackSize(), NumInitialBytes, NumResidualBytes);
76 // If there aren't any callee-saved registers, two-phase adjustment is
77 // inefficient. It's more efficient to adjust with NumInitialBytes too
78 // because when we're in a "callee pops argument space" situation, that pop
79 // must be tacked onto Initial for correctness.
80 NumInitialBytes = MFI->getStackSize();
84 // Tell everyone else how much adjustment we're expecting them to use. In
85 // particular if an adjustment is required for a tail call the epilogue could
86 // have a different view of things.
87 FuncInfo->setInitialStackAdjust(NumInitialBytes);
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
90 MachineInstr::FrameSetup);
92 if (NeedsFrameMoves && NumInitialBytes) {
93 // We emit this update even if the CFA is set from a frame pointer later so
94 // that the CFA is valid in the interim.
95 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
96 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
99 MachineLocation Dst(MachineLocation::VirtualFP);
100 MachineLocation Src(AArch64::XSP, NumInitialBytes);
101 Moves.push_back(MachineMove(SPLabel, Dst, Src));
104 // Otherwise we need to set the frame pointer and/or add a second stack
107 bool FPNeedsSetting = hasFP(MF);
108 for (; MBBI != MBB.end(); ++MBBI) {
109 // Note that this search makes strong assumptions about the operation used
110 // to store the frame-pointer: it must be "STP x29, x30, ...". This could
111 // change in future, but until then there's no point in implementing
112 // untestable more generic cases.
113 if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
114 && MBBI->getOperand(0).getReg() == AArch64::X29) {
115 int64_t X29FrameIdx = MBBI->getOperand(2).getIndex();
116 FuncInfo->setFramePointerOffset(MFI->getObjectOffset(X29FrameIdx));
119 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
121 NumInitialBytes + MFI->getObjectOffset(X29FrameIdx),
122 MachineInstr::FrameSetup);
124 // The offset adjustment used when emitting debugging locations relative
125 // to whatever frame base is set. AArch64 uses the default frame base (FP
126 // or SP) and this adjusts the calculations to be correct.
127 MFI->setOffsetAdjustment(- MFI->getObjectOffset(X29FrameIdx)
128 - MFI->getStackSize());
130 if (NeedsFrameMoves) {
131 MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
132 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
134 MachineLocation Dst(MachineLocation::VirtualFP);
135 MachineLocation Src(AArch64::X29, -MFI->getObjectOffset(X29FrameIdx));
136 Moves.push_back(MachineMove(FPLabel, Dst, Src));
139 FPNeedsSetting = false;
142 if (!MBBI->getFlag(MachineInstr::FrameSetup))
146 assert(!FPNeedsSetting && "Frame pointer couldn't be set");
148 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
149 MachineInstr::FrameSetup);
151 // Now we emit the rest of the frame setup information, if necessary: we've
152 // already noted the FP and initial SP moves so we're left with the prologue's
153 // final SP update and callee-saved register locations.
154 if (!NeedsFrameMoves)
157 // Reuse the label if appropriate, so create it in this outer scope.
158 MCSymbol *CSLabel = 0;
160 // The rest of the stack adjustment
161 if (!hasFP(MF) && NumResidualBytes) {
162 CSLabel = MMI.getContext().CreateTempSymbol();
163 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
166 MachineLocation Dst(MachineLocation::VirtualFP);
167 MachineLocation Src(AArch64::XSP, NumResidualBytes + NumInitialBytes);
168 Moves.push_back(MachineMove(CSLabel, Dst, Src));
171 // And any callee-saved registers (it's fine to leave them to the end here,
172 // because the old values are still valid at this point.
173 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
176 CSLabel = MMI.getContext().CreateTempSymbol();
177 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
181 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
182 E = CSI.end(); I != E; ++I) {
183 MachineLocation Dst(MachineLocation::VirtualFP, MFI->getObjectOffset(I->getFrameIdx()));
184 MachineLocation Src(I->getReg());
185 Moves.push_back(MachineMove(CSLabel, Dst, Src));
191 AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
192 MachineBasicBlock &MBB) const {
193 AArch64MachineFunctionInfo *FuncInfo =
194 MF.getInfo<AArch64MachineFunctionInfo>();
196 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
197 DebugLoc DL = MBBI->getDebugLoc();
198 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
199 MachineFrameInfo &MFI = *MF.getFrameInfo();
200 unsigned RetOpcode = MBBI->getOpcode();
202 // Initial and residual are named for consitency with the prologue. Note that
203 // in the epilogue, the residual adjustment is executed first.
204 uint64_t NumInitialBytes = FuncInfo->getInitialStackAdjust();
205 uint64_t NumResidualBytes = MFI.getStackSize() - NumInitialBytes;
206 uint64_t ArgumentPopSize = 0;
207 if (RetOpcode == AArch64::TC_RETURNdi ||
208 RetOpcode == AArch64::TC_RETURNxi) {
209 MachineOperand &JumpTarget = MBBI->getOperand(0);
210 MachineOperand &StackAdjust = MBBI->getOperand(1);
212 MachineInstrBuilder MIB;
213 if (RetOpcode == AArch64::TC_RETURNdi) {
214 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
215 if (JumpTarget.isGlobal()) {
216 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
217 JumpTarget.getTargetFlags());
219 assert(JumpTarget.isSymbol() && "unexpected tail call destination");
220 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
221 JumpTarget.getTargetFlags());
224 assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
225 && "Unexpected tail call");
227 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
228 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
231 // Add the extra operands onto the new tail call instruction even though
232 // they're not used directly (so that liveness is tracked properly etc).
233 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
234 MIB->addOperand(MBBI->getOperand(i));
237 // Delete the pseudo instruction TC_RETURN.
238 MachineInstr *NewMI = prior(MBBI);
242 // For a tail-call in a callee-pops-arguments environment, some or all of
243 // the stack may actually be in use for the call's arguments, this is
244 // calculated during LowerCall and consumed here...
245 ArgumentPopSize = StackAdjust.getImm();
247 // ... otherwise the amount to pop is *all* of the argument space,
248 // conveniently stored in the MachineFunctionInfo by
249 // LowerFormalArguments. This will, of course, be zero for the C calling
251 ArgumentPopSize = FuncInfo->getArgumentStackToRestore();
254 assert(NumInitialBytes % 16 == 0 && NumResidualBytes % 16 == 0
255 && "refusing to adjust stack by misaligned amt");
257 // We may need to address callee-saved registers differently, so find out the
258 // bound on the frame indices.
259 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
264 MinCSFI = CSI[0].getFrameIdx();
265 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
268 // The "residual" stack update comes first from this direction and guarantees
269 // that SP is NumInitialBytes below its value on function entry, either by a
270 // direct update or restoring it from the frame pointer.
271 if (NumInitialBytes + ArgumentPopSize != 0) {
272 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
273 NumInitialBytes + ArgumentPopSize);
278 // MBBI now points to the instruction just past the last callee-saved
279 // restoration (either RET/B if NumInitialBytes == 0, or the "ADD sp, sp"
282 // Now we need to find out where to put the bulk of the stack adjustment
283 MachineBasicBlock::iterator FirstEpilogue = MBBI;
284 while (MBBI != MBB.begin()) {
288 for (FrameOp = 0; FrameOp < MBBI->getNumOperands(); ++FrameOp) {
289 if (MBBI->getOperand(FrameOp).isFI())
293 // If this instruction doesn't have a frame index we've reached the end of
294 // the callee-save restoration.
295 if (FrameOp == MBBI->getNumOperands())
298 // Likewise if it *is* a local reference, but not to a callee-saved object.
299 int FrameIdx = MBBI->getOperand(FrameOp).getIndex();
300 if (FrameIdx < MinCSFI || FrameIdx > MaxCSFI)
303 FirstEpilogue = MBBI;
306 if (MF.getFrameInfo()->hasVarSizedObjects()) {
307 int64_t StaticFrameBase;
308 StaticFrameBase = -(NumInitialBytes + FuncInfo->getFramePointerOffset());
309 emitRegUpdate(MBB, FirstEpilogue, DL, TII,
310 AArch64::XSP, AArch64::X29, AArch64::NoRegister,
313 emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
318 AArch64FrameLowering::resolveFrameIndexReference(MachineFunction &MF,
322 bool IsCalleeSaveOp) const {
323 AArch64MachineFunctionInfo *FuncInfo =
324 MF.getInfo<AArch64MachineFunctionInfo>();
325 MachineFrameInfo *MFI = MF.getFrameInfo();
327 int64_t TopOfFrameOffset = MFI->getObjectOffset(FrameIndex);
329 assert(!(IsCalleeSaveOp && FuncInfo->getInitialStackAdjust() == 0)
330 && "callee-saved register in unexpected place");
332 // If the frame for this function is particularly large, we adjust the stack
333 // in two phases which means the callee-save related operations see a
334 // different (intermediate) stack size.
336 if (IsCalleeSaveOp) {
337 FrameReg = AArch64::XSP;
338 FrameRegPos = -static_cast<int64_t>(FuncInfo->getInitialStackAdjust());
339 } else if (useFPForAddressing(MF)) {
340 // Have to use the frame pointer since we have no idea where SP is.
341 FrameReg = AArch64::X29;
342 FrameRegPos = FuncInfo->getFramePointerOffset();
344 FrameReg = AArch64::XSP;
345 FrameRegPos = -static_cast<int64_t>(MFI->getStackSize()) + SPAdj;
348 return TopOfFrameOffset - FrameRegPos;
351 /// Estimate and return the size of the frame.
352 static unsigned estimateStackSize(MachineFunction &MF) {
353 // FIXME: Make generic? Really consider after upstreaming. This code is now
354 // shared between PEI, ARM *and* here.
355 const MachineFrameInfo *MFI = MF.getFrameInfo();
356 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
357 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
358 unsigned MaxAlign = MFI->getMaxAlignment();
361 // This code is very, very similar to PEI::calculateFrameObjectOffsets().
362 // It really should be refactored to share code. Until then, changes
363 // should keep in mind that there's tight coupling between the two.
365 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) {
366 int FixedOff = -MFI->getObjectOffset(i);
367 if (FixedOff > Offset) Offset = FixedOff;
369 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
370 if (MFI->isDeadObjectIndex(i))
372 Offset += MFI->getObjectSize(i);
373 unsigned Align = MFI->getObjectAlignment(i);
374 // Adjust to alignment boundary
375 Offset = (Offset+Align-1)/Align*Align;
377 MaxAlign = std::max(Align, MaxAlign);
380 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF))
381 Offset += MFI->getMaxCallFrameSize();
383 // Round up the size to a multiple of the alignment. If the function has
384 // any calls or alloca's, align to the target's StackAlignment value to
385 // ensure that the callee's frame or the alloca data is suitably aligned;
386 // otherwise, for leaf functions, align to the TransientStackAlignment
389 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() ||
390 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0))
391 StackAlign = TFI->getStackAlignment();
393 StackAlign = TFI->getTransientStackAlignment();
395 // If the frame pointer is eliminated, all frame offsets will be relative to
396 // SP not FP. Align to MaxAlign so this works.
397 StackAlign = std::max(StackAlign, MaxAlign);
398 unsigned AlignMask = StackAlign - 1;
399 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
401 return (unsigned)Offset;
405 AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
406 RegScavenger *RS) const {
407 const AArch64RegisterInfo *RegInfo =
408 static_cast<const AArch64RegisterInfo *>(MF.getTarget().getRegisterInfo());
409 MachineFrameInfo *MFI = MF.getFrameInfo();
410 const AArch64InstrInfo &TII =
411 *static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
414 MF.getRegInfo().setPhysRegUsed(AArch64::X29);
415 MF.getRegInfo().setPhysRegUsed(AArch64::X30);
418 // If addressing of local variables is going to be more complicated than
419 // shoving a base register and an offset into the instruction then we may well
420 // need to scavenge registers. We should either specifically add an
421 // callee-save register for this purpose or allocate an extra spill slot.
424 (RS && estimateStackSize(MF) >= TII.estimateRSStackLimit(MF))
425 || MFI->hasVarSizedObjects() // Access will be from X29: messes things up
426 || (MFI->adjustsStack() && !hasReservedCallFrame(MF));
431 // We certainly need some slack space for the scavenger, preferably an extra
433 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
434 uint16_t ExtraReg = AArch64::NoRegister;
436 for (unsigned i = 0; CSRegs[i]; ++i) {
437 if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
438 !MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
439 ExtraReg = CSRegs[i];
445 MF.getRegInfo().setPhysRegUsed(ExtraReg);
447 // Create a stack slot for scavenging purposes. PrologEpilogInserter
448 // helpfully places it near either SP or FP for us to avoid
449 // infinitely-regression during scavenging.
450 const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
451 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
457 bool AArch64FrameLowering::determinePrologueDeath(MachineBasicBlock &MBB,
458 unsigned Reg) const {
459 // If @llvm.returnaddress is called then it will refer to X30 by some means;
460 // the prologue store does not kill the register.
461 if (Reg == AArch64::X30) {
462 if (MBB.getParent()->getFrameInfo()->isReturnAddressTaken()
463 && MBB.getParent()->getRegInfo().isLiveIn(Reg))
467 // In all other cases, physical registers are dead after they've been saved
468 // but live at the beginning of the prologue block.
474 AArch64FrameLowering::emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MBBI,
476 const std::vector<CalleeSavedInfo> &CSI,
477 const TargetRegisterInfo *TRI,
478 LoadStoreMethod PossClasses[],
479 unsigned NumClasses) const {
480 DebugLoc DL = MBB.findDebugLoc(MBBI);
481 MachineFunction &MF = *MBB.getParent();
482 MachineFrameInfo &MFI = *MF.getFrameInfo();
483 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
485 // A certain amount of implicit contract is present here. The actual stack
486 // offsets haven't been allocated officially yet, so for strictly correct code
487 // we rely on the fact that the elements of CSI are allocated in order
488 // starting at SP, purely as dictated by size and alignment. In practice since
489 // this function handles the only accesses to those slots it's not quite so
492 // We have also ordered the Callee-saved register list in AArch64CallingConv
493 // so that the above scheme puts registers in order: in particular we want
494 // &X30 to be &X29+8 for an ABI-correct frame record (PCS 5.2.2)
495 for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
496 unsigned Reg = CSI[i].getReg();
498 // First we need to find out which register class the register belongs to so
499 // that we can use the correct load/store instrucitons.
501 for (ClassIdx = 0; ClassIdx < NumClasses; ++ClassIdx) {
502 if (PossClasses[ClassIdx].RegClass->contains(Reg))
505 assert(ClassIdx != NumClasses
506 && "Asked to store register in unexpected class");
507 const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
509 // Now we need to decide whether it's possible to emit a paired instruction:
510 // for this we want the next register to be in the same class.
511 MachineInstrBuilder NewMI;
513 if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) {
515 unsigned StLow = 0, StHigh = 0;
517 // Most of these registers will be live-in to the MBB and killed by our
518 // store, though there are exceptions (see determinePrologueDeath).
519 StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
520 StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
522 StLow = RegState::Define;
523 StHigh = RegState::Define;
526 NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].PairOpcode))
527 .addReg(CSI[i+1].getReg(), StLow)
528 .addReg(CSI[i].getReg(), StHigh);
530 // If it's a paired op, we've consumed two registers
535 State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
537 State = RegState::Define;
540 NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].SingleOpcode))
541 .addReg(CSI[i].getReg(), State);
544 // Note that the FrameIdx refers to the second register in a pair: it will
545 // be allocated the smaller numeric address and so is the one an LDP/STP
547 int FrameIdx = CSI[i].getFrameIdx();
548 MachineMemOperand::MemOperandFlags Flags;
549 Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
550 MachineMemOperand *MMO =
551 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
553 Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
554 MFI.getObjectAlignment(FrameIdx));
556 NewMI.addFrameIndex(FrameIdx)
557 .addImm(0) // address-register offset
561 NewMI.setMIFlags(MachineInstr::FrameSetup);
563 // For aesthetic reasons, during an epilogue we want to emit complementary
564 // operations to the prologue, but in the opposite order. So we still
565 // iterate through the CalleeSavedInfo list in order, but we put the
566 // instructions successively earlier in the MBB.
573 AArch64FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
574 MachineBasicBlock::iterator MBBI,
575 const std::vector<CalleeSavedInfo> &CSI,
576 const TargetRegisterInfo *TRI) const {
580 static LoadStoreMethod PossibleClasses[] = {
581 {&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
582 {&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
584 unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
586 emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI,
587 PossibleClasses, NumClasses);
593 AArch64FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
594 MachineBasicBlock::iterator MBBI,
595 const std::vector<CalleeSavedInfo> &CSI,
596 const TargetRegisterInfo *TRI) const {
601 static LoadStoreMethod PossibleClasses[] = {
602 {&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
603 {&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
605 unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
607 emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI,
608 PossibleClasses, NumClasses);
614 AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
615 const MachineFrameInfo *MFI = MF.getFrameInfo();
616 const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
618 // This is a decision of ABI compliance. The AArch64 PCS gives various options
619 // for conformance, and even at the most stringent level more or less permits
620 // elimination for leaf functions because there's no loss of functionality
621 // (for debugging etc)..
622 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->hasCalls())
625 // The following are hard-limits: incorrect code will be generated if we try
626 // to omit the frame.
627 return (RI->needsStackRealignment(MF) ||
628 MFI->hasVarSizedObjects() ||
629 MFI->isFrameAddressTaken());
633 AArch64FrameLowering::useFPForAddressing(const MachineFunction &MF) const {
634 return MF.getFrameInfo()->hasVarSizedObjects();
638 AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
639 const MachineFrameInfo *MFI = MF.getFrameInfo();
641 // Of the various reasons for having a frame pointer, it's actually only
642 // variable-sized objects that prevent reservation of a call frame.
643 return !(hasFP(MF) && MFI->hasVarSizedObjects());