1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeatureV8_1a : SubtargetFeature<"v8.1a", "HasV8_1a", "true",
36 "Enable ARMv8.1a extensions", [FeatureCRC]>;
38 /// Cyclone has register move instructions which are "free".
39 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
40 "Has zero-cycle register moves">;
42 /// Cyclone has instructions which zero registers for "free".
43 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
44 "Has zero-cycle zeroing instructions">;
46 //===----------------------------------------------------------------------===//
47 // Register File Description
48 //===----------------------------------------------------------------------===//
50 include "AArch64RegisterInfo.td"
51 include "AArch64CallingConvention.td"
53 //===----------------------------------------------------------------------===//
54 // Instruction Descriptions
55 //===----------------------------------------------------------------------===//
57 include "AArch64Schedule.td"
58 include "AArch64InstrInfo.td"
60 def AArch64InstrInfo : InstrInfo;
62 //===----------------------------------------------------------------------===//
63 // AArch64 Processors supported.
65 include "AArch64SchedA53.td"
66 include "AArch64SchedA57.td"
67 include "AArch64SchedCyclone.td"
69 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
70 "Cortex-A53 ARM processors",
76 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
77 "Cortex-A57 ARM processors",
83 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
89 FeatureZCRegMove, FeatureZCZeroing]>;
91 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
95 def : ProcessorModel<"generic-armv8.1-a", NoSchedModel, [FeatureV8_1a,
99 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
100 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
101 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
102 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
103 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 def GenericAsmParserVariant : AsmParserVariant {
111 string Name = "generic";
114 def AppleAsmParserVariant : AsmParserVariant {
116 string Name = "apple-neon";
119 //===----------------------------------------------------------------------===//
121 //===----------------------------------------------------------------------===//
122 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
123 // AsmWriter bits get associated with the correct class.
124 def GenericAsmWriter : AsmWriter {
125 string AsmWriterClassName = "InstPrinter";
127 bit isMCAsmWriter = 1;
130 def AppleAsmWriter : AsmWriter {
131 let AsmWriterClassName = "AppleInstPrinter";
133 int isMCAsmWriter = 1;
136 //===----------------------------------------------------------------------===//
137 // Target Declaration
138 //===----------------------------------------------------------------------===//
140 def AArch64 : Target {
141 let InstructionSet = AArch64InstrInfo;
142 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
143 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];