lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  36   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  37
  38 /// Cyclone has register move instructions which are "free".
  39 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  40                                         "Has zero-cycle register moves">;
  41
  42 /// Cyclone has instructions which zero registers for "free".
  43 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  44                                         "Has zero-cycle zeroing instructions">;
  45
  46 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  47                                           "StrictAlign", "true",
  48                                           "Disallow all unaligned memory "
  49                                           "access">;
  50
  51 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  52                                          "Reserve X18, making it unavailable "
  53                                          "as a GPR">;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Architectures.
  57 //
  58
  59 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
  60   "Support ARM v8.1a instructions", [FeatureCRC]>;
  61
  62 //===----------------------------------------------------------------------===//
  63 // Register File Description
  64 //===----------------------------------------------------------------------===//
  65
  66 include "AArch64RegisterInfo.td"
  67 include "AArch64CallingConvention.td"
  68
  69 //===----------------------------------------------------------------------===//
  70 // Instruction Descriptions
  71 //===----------------------------------------------------------------------===//
  72
  73 include "AArch64Schedule.td"
  74 include "AArch64InstrInfo.td"
  75
  76 def AArch64InstrInfo : InstrInfo;
  77
  78 //===----------------------------------------------------------------------===//
  79 // AArch64 Processors supported.
  80 //
  81 include "AArch64SchedA53.td"
  82 include "AArch64SchedA57.td"
  83 include "AArch64SchedCyclone.td"
  84
  85 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
  86                                    "Cortex-A53 ARM processors",
  87                                    [FeatureFPARMv8,
  88                                    FeatureNEON,
  89                                    FeatureCrypto,
  90                                    FeatureCRC,
  91                                    FeaturePerfMon]>;
  92
  93 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
  94                                    "Cortex-A57 ARM processors",
  95                                    [FeatureFPARMv8,
  96                                    FeatureNEON,
  97                                    FeatureCrypto,
  98                                    FeatureCRC,
  99                                    FeaturePerfMon]>;
 100
 101 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 102                                    "Cyclone",
 103                                    [FeatureFPARMv8,
 104                                    FeatureNEON,
 105                                    FeatureCrypto,
 106                                    FeatureCRC,
 107                                    FeaturePerfMon,
 108                                    FeatureZCRegMove, FeatureZCZeroing]>;
 109
 110 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
 111                                               FeatureNEON,
 112                                               FeatureCRC,
 113                                               FeaturePerfMon]>;
 114
 115 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 116 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 117 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
 118 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
 119 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 120
 121 //===----------------------------------------------------------------------===//
 122 // Assembly parser
 123 //===----------------------------------------------------------------------===//
 124
 125 def GenericAsmParserVariant : AsmParserVariant {
 126   int Variant = 0;
 127   string Name = "generic";
 128 }
 129
 130 def AppleAsmParserVariant : AsmParserVariant {
 131   int Variant = 1;
 132   string Name = "apple-neon";
 133 }
 134
 135 //===----------------------------------------------------------------------===//
 136 // Assembly printer
 137 //===----------------------------------------------------------------------===//
 138 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 139 // AsmWriter bits get associated with the correct class.
 140 def GenericAsmWriter : AsmWriter {
 141   string AsmWriterClassName  = "InstPrinter";
 142   int PassSubtarget = 1;
 143   int Variant = 0;
 144   bit isMCAsmWriter = 1;
 145 }
 146
 147 def AppleAsmWriter : AsmWriter {
 148   let AsmWriterClassName = "AppleInstPrinter";
 149   int PassSubtarget = 1;
 150   int Variant = 1;
 151   int isMCAsmWriter = 1;
 152 }
 153
 154 //===----------------------------------------------------------------------===//
 155 // Target Declaration
 156 //===----------------------------------------------------------------------===//
 157
 158 def AArch64 : Target {
 159   let InstructionSet = AArch64InstrInfo;
 160   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 161   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 162 }