lib/MC/MCSubtargetInfo.cpp

   1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/MC/MCSubtargetInfo.h"
  11 #include "llvm/ADT/StringRef.h"
  12 #include "llvm/ADT/Triple.h"
  13 #include "llvm/MC/MCInstrItineraries.h"
  14 #include "llvm/MC/SubtargetFeature.h"
  15 #include "llvm/Support/raw_ostream.h"
  16 #include <algorithm>
  17
  18 using namespace llvm;
  19
  20 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
  21 /// with feature string). Recompute feature bits and scheduling model.
  22 void
  23 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
  24   SubtargetFeatures Features(FS);
  25   FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
  26   InitCPUSchedModel(CPU);
  27 }
  28
  29 void
  30 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
  31   if (!CPU.empty())
  32     CPUSchedModel = getSchedModelForCPU(CPU);
  33   else
  34     CPUSchedModel = MCSchedModel::GetDefaultSchedModel();
  35 }
  36
  37 void
  38 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS,
  39                                      ArrayRef<SubtargetFeatureKV> PF,
  40                                      ArrayRef<SubtargetFeatureKV> PD,
  41                                      const SubtargetInfoKV *ProcSched,
  42                                      const MCWriteProcResEntry *WPR,
  43                                      const MCWriteLatencyEntry *WL,
  44                                      const MCReadAdvanceEntry *RA,
  45                                      const InstrStage *IS,
  46                                      const unsigned *OC,
  47                                      const unsigned *FP) {
  48   TargetTriple = TT;
  49   CPU = C;
  50   ProcFeatures = PF;
  51   ProcDesc = PD;
  52   ProcSchedModels = ProcSched;
  53   WriteProcResTable = WPR;
  54   WriteLatencyTable = WL;
  55   ReadAdvanceTable = RA;
  56
  57   Stages = IS;
  58   OperandCycles = OC;
  59   ForwardingPaths = FP;
  60
  61   InitMCProcessorInfo(CPU, FS);
  62 }
  63
  64 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  65 /// bits. This version does not change the implied bits.
  66 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
  67   FeatureBits.flip(FB);
  68   return FeatureBits;
  69 }
  70
  71 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
  72   FeatureBits ^= FB;
  73   return FeatureBits;
  74 }
  75
  76 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  77 /// bits. This version will also change all implied bits.
  78 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
  79   SubtargetFeatures Features;
  80   FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
  81   return FeatureBits;
  82 }
  83
  84
  85 MCSchedModel
  86 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
  87   assert(ProcSchedModels && "Processor machine model not available!");
  88
  89   unsigned NumProcs = ProcDesc.size();
  90 #ifndef NDEBUG
  91   for (size_t i = 1; i < NumProcs; i++) {
  92     assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
  93            "Processor machine model table is not sorted");
  94   }
  95 #endif
  96
  97   // Find entry
  98   const SubtargetInfoKV *Found =
  99     std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
 100   if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
 101     if (CPU != "help") // Don't error if the user asked for help.
 102       errs() << "'" << CPU
 103              << "' is not a recognized processor for this target"
 104              << " (ignoring processor)\n";
 105     return MCSchedModel::GetDefaultSchedModel();
 106   }
 107   assert(Found->Value && "Missing processor SchedModel value");
 108   return *(const MCSchedModel *)Found->Value;
 109 }
 110
 111 InstrItineraryData
 112 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
 113   const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
 114   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 115 }
 116
 117 /// Initialize an InstrItineraryData instance.
 118 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
 119   InstrItins =
 120     InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
 121 }