1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 /// NOTE: The constructor takes ownership of TLOF.
38 TargetLowering::TargetLowering(const TargetMachine &tm,
39 const TargetLoweringObjectFile *tlof)
40 : TargetLoweringBase(tm, tlof) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = isSigned;
100 Entry.isZExt = !isSigned;
101 Args.push_back(Entry);
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
108 false, 0, getLibcallCallingConv(LC),
109 /*isTailCall=*/false,
110 doesNotReturn, isReturnValueUsed, Callee, Args,
112 return LowerCallTo(CLI);
116 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
117 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
118 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
119 SDValue &NewLHS, SDValue &NewRHS,
120 ISD::CondCode &CCCode,
122 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
123 && "Unsupported setcc type!");
125 // Expand into one or more soft-fp libcall(s).
126 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
130 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
135 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
140 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
145 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
150 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
155 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
159 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
163 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
164 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
167 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
171 // SETONE = SETOLT | SETOGT
172 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
180 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
184 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
188 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
192 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
195 default: llvm_unreachable("Do not know how to soften this setcc!");
199 // Use the target specific return value for comparions lib calls.
200 EVT RetVT = getCmpLibcallReturnType();
201 SDValue Ops[2] = { NewLHS, NewRHS };
202 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
204 NewRHS = DAG.getConstant(0, RetVT);
205 CCCode = getCmpLibcallCC(LC1);
206 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
207 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
208 getSetCCResultType(*DAG.getContext(), RetVT),
209 NewLHS, NewRHS, DAG.getCondCode(CCCode));
210 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
212 NewLHS = DAG.getNode(ISD::SETCC, dl,
213 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
214 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
215 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
220 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
221 /// current function. The returned value is a member of the
222 /// MachineJumpTableInfo::JTEntryKind enum.
223 unsigned TargetLowering::getJumpTableEncoding() const {
224 // In non-pic modes, just use the address of a block.
225 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 return MachineJumpTableInfo::EK_BlockAddress;
228 // In PIC mode, if the target supports a GPRel32 directive, use it.
229 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
230 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
232 // Otherwise, use a label difference.
233 return MachineJumpTableInfo::EK_LabelDifference32;
236 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
237 SelectionDAG &DAG) const {
238 // If our PIC model is GP relative, use the global offset table as the base.
239 unsigned JTEncoding = getJumpTableEncoding();
241 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
243 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
248 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
249 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
252 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
253 unsigned JTI,MCContext &Ctx) const{
254 // The normal PIC reloc base is the label at the start of the jump table.
255 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
259 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
260 // Assume that everything is safe in static mode.
261 if (getTargetMachine().getRelocationModel() == Reloc::Static)
264 // In dynamic-no-pic mode, assume that known defined values are safe.
265 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
267 !GA->getGlobal()->isDeclaration() &&
268 !GA->getGlobal()->isWeakForLinker())
271 // Otherwise assume nothing is safe.
275 //===----------------------------------------------------------------------===//
276 // Optimization Methods
277 //===----------------------------------------------------------------------===//
279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
280 /// specified instruction is a constant integer. If so, check to see if there
281 /// are any bits set in the constant that are not demanded. If so, shrink the
282 /// constant and return true.
283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
284 const APInt &Demanded) {
287 // FIXME: ISD::SELECT, ISD::SELECT_CC
288 switch (Op.getOpcode()) {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
294 if (!C) return false;
296 if (Op.getOpcode() == ISD::XOR &&
297 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
300 // if we can expand it to have all bits set, do it
301 if (C->getAPIntValue().intersects(~Demanded)) {
302 EVT VT = Op.getValueType();
303 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
304 DAG.getConstant(Demanded &
307 return CombineTo(Op, New);
317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
318 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
319 /// cast, but it could be generalized for targets with other types of
320 /// implicit widening casts.
322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
324 const APInt &Demanded,
326 assert(Op.getNumOperands() == 2 &&
327 "ShrinkDemandedOp only supports binary operators!");
328 assert(Op.getNode()->getNumValues() == 1 &&
329 "ShrinkDemandedOp only supports nodes with one result!");
331 // Don't do this if the node has another user, which may require the
333 if (!Op.getNode()->hasOneUse())
336 // Search for the smallest integer type with free casts to and from
337 // Op's type. For expedience, just check power-of-2 integer types.
338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
339 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
340 unsigned SmallVTBits = DemandedSize;
341 if (!isPowerOf2_32(SmallVTBits))
342 SmallVTBits = NextPowerOf2(SmallVTBits);
343 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
344 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
345 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
346 TLI.isZExtFree(SmallVT, Op.getValueType())) {
347 // We found a type with free casts.
348 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
349 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
350 Op.getNode()->getOperand(0)),
351 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
352 Op.getNode()->getOperand(1)));
353 bool NeedZext = DemandedSize > SmallVTBits;
354 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
355 dl, Op.getValueType(), X);
356 return CombineTo(Op, Z);
362 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
363 /// DemandedMask bits of the result of Op are ever used downstream. If we can
364 /// use this information to simplify Op, create a new simplified DAG node and
365 /// return true, returning the original and new nodes in Old and New. Otherwise,
366 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
367 /// the expression (used to simplify the caller). The KnownZero/One bits may
368 /// only be accurate for those bits in the DemandedMask.
369 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
370 const APInt &DemandedMask,
373 TargetLoweringOpt &TLO,
374 unsigned Depth) const {
375 unsigned BitWidth = DemandedMask.getBitWidth();
376 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
377 "Mask size mismatches value type size!");
378 APInt NewMask = DemandedMask;
381 // Don't know anything.
382 KnownZero = KnownOne = APInt(BitWidth, 0);
384 // Other users may use these bits.
385 if (!Op.getNode()->hasOneUse()) {
387 // If not at the root, Just compute the KnownZero/KnownOne bits to
388 // simplify things downstream.
389 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
392 // If this is the root being simplified, allow it to have multiple uses,
393 // just set the NewMask to all bits.
394 NewMask = APInt::getAllOnesValue(BitWidth);
395 } else if (DemandedMask == 0) {
396 // Not demanding any bits from Op.
397 if (Op.getOpcode() != ISD::UNDEF)
398 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
400 } else if (Depth == 6) { // Limit search depth.
404 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
405 switch (Op.getOpcode()) {
407 // We know all of the bits for a constant!
408 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
409 KnownZero = ~KnownOne;
410 return false; // Don't fall through, will infinitely loop.
412 // If the RHS is a constant, check to see if the LHS would be zero without
413 // using the bits from the RHS. Below, we use knowledge about the RHS to
414 // simplify the LHS, here we're using information from the LHS to simplify
416 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
417 APInt LHSZero, LHSOne;
418 // Do not increment Depth here; that can cause an infinite loop.
419 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
420 // If the LHS already has zeros where RHSC does, this and is dead.
421 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
422 return TLO.CombineTo(Op, Op.getOperand(0));
423 // If any of the set bits in the RHS are known zero on the LHS, shrink
425 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
430 KnownOne, TLO, Depth+1))
432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
433 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
434 KnownZero2, KnownOne2, TLO, Depth+1))
436 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
438 // If all of the demanded bits are known one on one side, return the other.
439 // These bits cannot contribute to the result of the 'and'.
440 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
441 return TLO.CombineTo(Op, Op.getOperand(0));
442 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
443 return TLO.CombineTo(Op, Op.getOperand(1));
444 // If all of the demanded bits in the inputs are known zeros, return zero.
445 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
446 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
447 // If the RHS is a constant, see if we can simplify it.
448 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
450 // If the operation can be done in a smaller type, do so.
451 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
454 // Output known-1 bits are only known if set in both the LHS & RHS.
455 KnownOne &= KnownOne2;
456 // Output known-0 are known to be clear if zero in either the LHS | RHS.
457 KnownZero |= KnownZero2;
460 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
461 KnownOne, TLO, Depth+1))
463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
464 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
465 KnownZero2, KnownOne2, TLO, Depth+1))
467 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
469 // If all of the demanded bits are known zero on one side, return the other.
470 // These bits cannot contribute to the result of the 'or'.
471 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
472 return TLO.CombineTo(Op, Op.getOperand(0));
473 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
474 return TLO.CombineTo(Op, Op.getOperand(1));
475 // If all of the potentially set bits on one side are known to be set on
476 // the other side, just use the 'other' side.
477 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(0));
479 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
480 return TLO.CombineTo(Op, Op.getOperand(1));
481 // If the RHS is a constant, see if we can simplify it.
482 if (TLO.ShrinkDemandedConstant(Op, NewMask))
484 // If the operation can be done in a smaller type, do so.
485 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
488 // Output known-0 bits are only known if clear in both the LHS & RHS.
489 KnownZero &= KnownZero2;
490 // Output known-1 are known to be set if set in either the LHS | RHS.
491 KnownOne |= KnownOne2;
494 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
495 KnownOne, TLO, Depth+1))
497 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
498 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
499 KnownOne2, TLO, Depth+1))
501 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
503 // If all of the demanded bits are known zero on one side, return the other.
504 // These bits cannot contribute to the result of the 'xor'.
505 if ((KnownZero & NewMask) == NewMask)
506 return TLO.CombineTo(Op, Op.getOperand(0));
507 if ((KnownZero2 & NewMask) == NewMask)
508 return TLO.CombineTo(Op, Op.getOperand(1));
509 // If the operation can be done in a smaller type, do so.
510 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
513 // If all of the unknown bits are known to be zero on one side or the other
514 // (but not both) turn this into an *inclusive* or.
515 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
516 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
517 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521 // Output known-0 bits are known if clear or set in both the LHS & RHS.
522 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
523 // Output known-1 are known to be set if set in only one of the LHS, RHS.
524 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
526 // If all of the demanded bits on one side are known, and all of the set
527 // bits on that side are also known to be set on the other side, turn this
528 // into an AND, as we know the bits will be cleared.
529 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
530 // NB: it is okay if more bits are known than are requested
531 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
532 if (KnownOne == KnownOne2) { // set bits are the same on both sides
533 EVT VT = Op.getValueType();
534 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
535 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
536 Op.getOperand(0), ANDC));
540 // If the RHS is a constant, see if we can simplify it.
541 // for XOR, we prefer to force bits to 1 if they will make a -1.
542 // if we can't force bits, try to shrink constant
543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
544 APInt Expanded = C->getAPIntValue() | (~NewMask);
545 // if we can expand it to have all bits set, do it
546 if (Expanded.isAllOnesValue()) {
547 if (Expanded != C->getAPIntValue()) {
548 EVT VT = Op.getValueType();
549 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
550 TLO.DAG.getConstant(Expanded, VT));
551 return TLO.CombineTo(Op, New);
553 // if it already has all the bits set, nothing to change
554 // but don't shrink either!
555 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
560 KnownZero = KnownZeroOut;
561 KnownOne = KnownOneOut;
564 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
565 KnownOne, TLO, Depth+1))
567 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
568 KnownOne2, TLO, Depth+1))
570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
573 // If the operands are constants, see if we can simplify them.
574 if (TLO.ShrinkDemandedConstant(Op, NewMask))
577 // Only known if known in both the LHS and RHS.
578 KnownOne &= KnownOne2;
579 KnownZero &= KnownZero2;
582 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
583 KnownOne, TLO, Depth+1))
585 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
586 KnownOne2, TLO, Depth+1))
588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
589 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
591 // If the operands are constants, see if we can simplify them.
592 if (TLO.ShrinkDemandedConstant(Op, NewMask))
595 // Only known if known in both the LHS and RHS.
596 KnownOne &= KnownOne2;
597 KnownZero &= KnownZero2;
600 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
601 unsigned ShAmt = SA->getZExtValue();
602 SDValue InOp = Op.getOperand(0);
604 // If the shift count is an invalid immediate, don't do anything.
605 if (ShAmt >= BitWidth)
608 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
609 // single shift. We can do this if the bottom bits (which are shifted
610 // out) are never demanded.
611 if (InOp.getOpcode() == ISD::SRL &&
612 isa<ConstantSDNode>(InOp.getOperand(1))) {
613 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
614 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
615 unsigned Opc = ISD::SHL;
623 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
624 EVT VT = Op.getValueType();
625 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
626 InOp.getOperand(0), NewSA));
630 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
631 KnownZero, KnownOne, TLO, Depth+1))
634 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
635 // are not demanded. This will likely allow the anyext to be folded away.
636 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
637 SDValue InnerOp = InOp.getNode()->getOperand(0);
638 EVT InnerVT = InnerOp.getValueType();
639 unsigned InnerBits = InnerVT.getSizeInBits();
640 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
641 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
642 EVT ShTy = getShiftAmountTy(InnerVT);
643 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
646 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
647 TLO.DAG.getConstant(ShAmt, ShTy));
650 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
653 // Repeat the SHL optimization above in cases where an extension
654 // intervenes: (shl (anyext (shr x, c1)), c2) to
655 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
656 // aren't demanded (as above) and that the shifted upper c1 bits of
657 // x aren't demanded.
658 if (InOp.hasOneUse() &&
659 InnerOp.getOpcode() == ISD::SRL &&
660 InnerOp.hasOneUse() &&
661 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
662 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
664 if (InnerShAmt < ShAmt &&
665 InnerShAmt < InnerBits &&
666 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
667 NewMask.trunc(ShAmt) == 0) {
669 TLO.DAG.getConstant(ShAmt - InnerShAmt,
670 Op.getOperand(1).getValueType());
671 EVT VT = Op.getValueType();
672 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
673 InnerOp.getOperand(0));
674 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
680 KnownZero <<= SA->getZExtValue();
681 KnownOne <<= SA->getZExtValue();
682 // low bits known zero.
683 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
688 EVT VT = Op.getValueType();
689 unsigned ShAmt = SA->getZExtValue();
690 unsigned VTSize = VT.getSizeInBits();
691 SDValue InOp = Op.getOperand(0);
693 // If the shift count is an invalid immediate, don't do anything.
694 if (ShAmt >= BitWidth)
697 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
698 // single shift. We can do this if the top bits (which are shifted out)
699 // are never demanded.
700 if (InOp.getOpcode() == ISD::SHL &&
701 isa<ConstantSDNode>(InOp.getOperand(1))) {
702 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
703 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
704 unsigned Opc = ISD::SRL;
712 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
713 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
714 InOp.getOperand(0), NewSA));
718 // Compute the new bits that are at the top now.
719 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
720 KnownZero, KnownOne, TLO, Depth+1))
722 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
723 KnownZero = KnownZero.lshr(ShAmt);
724 KnownOne = KnownOne.lshr(ShAmt);
726 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
727 KnownZero |= HighBits; // High bits known zero.
731 // If this is an arithmetic shift right and only the low-bit is set, we can
732 // always convert this into a logical shr, even if the shift amount is
733 // variable. The low bit of the shift cannot be an input sign bit unless
734 // the shift amount is >= the size of the datatype, which is undefined.
736 return TLO.CombineTo(Op,
737 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
738 Op.getOperand(0), Op.getOperand(1)));
740 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
741 EVT VT = Op.getValueType();
742 unsigned ShAmt = SA->getZExtValue();
744 // If the shift count is an invalid immediate, don't do anything.
745 if (ShAmt >= BitWidth)
748 APInt InDemandedMask = (NewMask << ShAmt);
750 // If any of the demanded bits are produced by the sign extension, we also
751 // demand the input sign bit.
752 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
753 if (HighBits.intersects(NewMask))
754 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
756 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
757 KnownZero, KnownOne, TLO, Depth+1))
759 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
760 KnownZero = KnownZero.lshr(ShAmt);
761 KnownOne = KnownOne.lshr(ShAmt);
763 // Handle the sign bit, adjusted to where it is now in the mask.
764 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
766 // If the input sign bit is known to be zero, or if none of the top bits
767 // are demanded, turn this into an unsigned shift right.
768 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
769 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773 int Log2 = NewMask.exactLogBase2();
775 // The bit must come from the sign.
777 TLO.DAG.getConstant(BitWidth - 1 - Log2,
778 Op.getOperand(1).getValueType());
779 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
780 Op.getOperand(0), NewSA));
783 if (KnownOne.intersects(SignBit))
784 // New bits are known one.
785 KnownOne |= HighBits;
788 case ISD::SIGN_EXTEND_INREG: {
789 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
791 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
792 // If we only care about the highest bit, don't bother shifting right.
793 if (MsbMask == DemandedMask) {
794 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
795 SDValue InOp = Op.getOperand(0);
797 // Compute the correct shift amount type, which must be getShiftAmountTy
798 // for scalar types after legalization.
799 EVT ShiftAmtTy = Op.getValueType();
800 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
801 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
803 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
804 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
805 Op.getValueType(), InOp, ShiftAmt));
808 // Sign extension. Compute the demanded bits in the result that are not
809 // present in the input.
811 APInt::getHighBitsSet(BitWidth,
812 BitWidth - ExVT.getScalarType().getSizeInBits());
814 // If none of the extended bits are demanded, eliminate the sextinreg.
815 if ((NewBits & NewMask) == 0)
816 return TLO.CombineTo(Op, Op.getOperand(0));
819 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
820 APInt InputDemandedBits =
821 APInt::getLowBitsSet(BitWidth,
822 ExVT.getScalarType().getSizeInBits()) &
825 // Since the sign extended bits are demanded, we know that the sign
827 InputDemandedBits |= InSignBit;
829 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
830 KnownZero, KnownOne, TLO, Depth+1))
832 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
834 // If the sign bit of the input is known set or clear, then we know the
835 // top bits of the result.
837 // If the input sign bit is known zero, convert this into a zero extension.
838 if (KnownZero.intersects(InSignBit))
839 return TLO.CombineTo(Op,
840 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
842 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
844 KnownZero &= ~NewBits;
845 } else { // Input sign bit unknown
846 KnownZero &= ~NewBits;
847 KnownOne &= ~NewBits;
851 case ISD::ZERO_EXTEND: {
852 unsigned OperandBitWidth =
853 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
854 APInt InMask = NewMask.trunc(OperandBitWidth);
856 // If none of the top bits are demanded, convert this into an any_extend.
858 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
859 if (!NewBits.intersects(NewMask))
860 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
864 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
865 KnownZero, KnownOne, TLO, Depth+1))
867 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
868 KnownZero = KnownZero.zext(BitWidth);
869 KnownOne = KnownOne.zext(BitWidth);
870 KnownZero |= NewBits;
873 case ISD::SIGN_EXTEND: {
874 EVT InVT = Op.getOperand(0).getValueType();
875 unsigned InBits = InVT.getScalarType().getSizeInBits();
876 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
877 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
878 APInt NewBits = ~InMask & NewMask;
880 // If none of the top bits are demanded, convert this into an any_extend.
882 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
886 // Since some of the sign extended bits are demanded, we know that the sign
888 APInt InDemandedBits = InMask & NewMask;
889 InDemandedBits |= InSignBit;
890 InDemandedBits = InDemandedBits.trunc(InBits);
892 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
893 KnownOne, TLO, Depth+1))
895 KnownZero = KnownZero.zext(BitWidth);
896 KnownOne = KnownOne.zext(BitWidth);
898 // If the sign bit is known zero, convert this to a zero extend.
899 if (KnownZero.intersects(InSignBit))
900 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
904 // If the sign bit is known one, the top bits match.
905 if (KnownOne.intersects(InSignBit)) {
907 assert((KnownZero & NewBits) == 0);
908 } else { // Otherwise, top bits aren't known.
909 assert((KnownOne & NewBits) == 0);
910 assert((KnownZero & NewBits) == 0);
914 case ISD::ANY_EXTEND: {
915 unsigned OperandBitWidth =
916 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
917 APInt InMask = NewMask.trunc(OperandBitWidth);
918 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
919 KnownZero, KnownOne, TLO, Depth+1))
921 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
922 KnownZero = KnownZero.zext(BitWidth);
923 KnownOne = KnownOne.zext(BitWidth);
926 case ISD::TRUNCATE: {
927 // Simplify the input, using demanded bit information, and compute the known
928 // zero/one bits live out.
929 unsigned OperandBitWidth =
930 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
931 APInt TruncMask = NewMask.zext(OperandBitWidth);
932 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
933 KnownZero, KnownOne, TLO, Depth+1))
935 KnownZero = KnownZero.trunc(BitWidth);
936 KnownOne = KnownOne.trunc(BitWidth);
938 // If the input is only used by this truncate, see if we can shrink it based
939 // on the known demanded bits.
940 if (Op.getOperand(0).getNode()->hasOneUse()) {
941 SDValue In = Op.getOperand(0);
942 switch (In.getOpcode()) {
945 // Shrink SRL by a constant if none of the high bits shifted in are
947 if (TLO.LegalTypes() &&
948 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
949 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
952 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
955 SDValue Shift = In.getOperand(1);
956 if (TLO.LegalTypes()) {
957 uint64_t ShVal = ShAmt->getZExtValue();
959 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
962 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
963 OperandBitWidth - BitWidth);
964 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
966 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
967 // None of the shifted in bits are needed. Add a truncate of the
968 // shift input, then shift it.
969 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
972 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
981 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
984 case ISD::AssertZext: {
985 // AssertZext demands all of the high bits, plus any of the low bits
986 // demanded by its users.
987 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
988 APInt InMask = APInt::getLowBitsSet(BitWidth,
990 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
991 KnownZero, KnownOne, TLO, Depth+1))
993 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
995 KnownZero |= ~InMask & NewMask;
999 // If this is an FP->Int bitcast and if the sign bit is the only
1000 // thing demanded, turn this into a FGETSIGN.
1001 if (!TLO.LegalOperations() &&
1002 !Op.getValueType().isVector() &&
1003 !Op.getOperand(0).getValueType().isVector() &&
1004 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1005 Op.getOperand(0).getValueType().isFloatingPoint()) {
1006 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1007 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1008 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1009 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1010 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1011 // place. We expect the SHL to be eliminated by other optimizations.
1012 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1013 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1014 if (!OpVTLegal && OpVTSizeInBits > 32)
1015 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1016 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1017 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1018 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1027 // Add, Sub, and Mul don't demand any bits in positions beyond that
1028 // of the highest bit demanded of them.
1029 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1030 BitWidth - NewMask.countLeadingZeros());
1031 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1032 KnownOne2, TLO, Depth+1))
1034 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1035 KnownOne2, TLO, Depth+1))
1037 // See if the operation should be performed at a smaller bit width.
1038 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1043 // Just use ComputeMaskedBits to compute output bits.
1044 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1048 // If we know the value of all of the demanded bits, return this as a
1050 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1051 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1056 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1057 /// in Mask are known to be either zero or one and return them in the
1058 /// KnownZero/KnownOne bitsets.
1059 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1062 const SelectionDAG &DAG,
1063 unsigned Depth) const {
1064 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1065 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1066 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1067 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1068 "Should use MaskedValueIsZero if you don't know whether Op"
1069 " is a target node!");
1070 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1073 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1074 /// targets that want to expose additional information about sign bits to the
1076 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1077 const SelectionDAG &,
1078 unsigned Depth) const {
1079 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1080 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1081 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1082 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1083 "Should use ComputeNumSignBits if you don't know whether Op"
1084 " is a target node!");
1088 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1089 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1090 /// determine which bit is set.
1092 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1093 // A left-shift of a constant one will have exactly one bit set, because
1094 // shifting the bit off the end is undefined.
1095 if (Val.getOpcode() == ISD::SHL)
1096 if (ConstantSDNode *C =
1097 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1098 if (C->getAPIntValue() == 1)
1101 // Similarly, a right-shift of a constant sign-bit will have exactly
1103 if (Val.getOpcode() == ISD::SRL)
1104 if (ConstantSDNode *C =
1105 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1106 if (C->getAPIntValue().isSignBit())
1109 // More could be done here, though the above checks are enough
1110 // to handle some common cases.
1112 // Fall back to ComputeMaskedBits to catch other known cases.
1113 EVT OpVT = Val.getValueType();
1114 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1115 APInt KnownZero, KnownOne;
1116 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1117 return (KnownZero.countPopulation() == BitWidth - 1) &&
1118 (KnownOne.countPopulation() == 1);
1121 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1126 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1128 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1133 CN = BV->getConstantSplatValue();
1136 switch (getBooleanContents(IsVec)) {
1137 case UndefinedBooleanContent:
1138 return CN->getAPIntValue()[0];
1139 case ZeroOrOneBooleanContent:
1141 case ZeroOrNegativeOneBooleanContent:
1142 return CN->isAllOnesValue();
1145 llvm_unreachable("Invalid boolean contents");
1148 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1153 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1155 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1160 CN = BV->getConstantSplatValue();
1163 if (getBooleanContents(IsVec) == UndefinedBooleanContent)
1164 return !CN->getAPIntValue()[0];
1166 return CN->isNullValue();
1169 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1170 /// and cc. If it is unable to simplify it, return a null SDValue.
1172 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1173 ISD::CondCode Cond, bool foldBooleans,
1174 DAGCombinerInfo &DCI, SDLoc dl) const {
1175 SelectionDAG &DAG = DCI.DAG;
1177 // These setcc operations always fold.
1181 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1183 case ISD::SETTRUE2: {
1184 TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector());
1185 return DAG.getConstant(
1186 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1190 // Ensure that the constant occurs on the RHS, and fold constant
1192 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1193 if (isa<ConstantSDNode>(N0.getNode()) &&
1194 (DCI.isBeforeLegalizeOps() ||
1195 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1196 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1198 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1199 const APInt &C1 = N1C->getAPIntValue();
1201 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1202 // equality comparison, then we're just comparing whether X itself is
1204 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1205 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1206 N0.getOperand(1).getOpcode() == ISD::Constant) {
1208 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1209 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1210 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1211 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1212 // (srl (ctlz x), 5) == 0 -> X != 0
1213 // (srl (ctlz x), 5) != 1 -> X != 0
1216 // (srl (ctlz x), 5) != 0 -> X == 0
1217 // (srl (ctlz x), 5) == 1 -> X == 0
1220 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1221 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1227 // Look through truncs that don't change the value of a ctpop.
1228 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1229 CTPOP = N0.getOperand(0);
1231 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1232 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1233 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1234 EVT CTVT = CTPOP.getValueType();
1235 SDValue CTOp = CTPOP.getOperand(0);
1237 // (ctpop x) u< 2 -> (x & x-1) == 0
1238 // (ctpop x) u> 1 -> (x & x-1) != 0
1239 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1240 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1241 DAG.getConstant(1, CTVT));
1242 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1243 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1244 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1247 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1250 // (zext x) == C --> x == (trunc C)
1251 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1252 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1253 unsigned MinBits = N0.getValueSizeInBits();
1255 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1257 MinBits = N0->getOperand(0).getValueSizeInBits();
1258 PreZExt = N0->getOperand(0);
1259 } else if (N0->getOpcode() == ISD::AND) {
1260 // DAGCombine turns costly ZExts into ANDs
1261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1262 if ((C->getAPIntValue()+1).isPowerOf2()) {
1263 MinBits = C->getAPIntValue().countTrailingOnes();
1264 PreZExt = N0->getOperand(0);
1266 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1268 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1269 MinBits = LN0->getMemoryVT().getSizeInBits();
1274 // Make sure we're not losing bits from the constant.
1276 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1277 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1278 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1279 // Will get folded away.
1280 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1281 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1282 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1287 // If the LHS is '(and load, const)', the RHS is 0,
1288 // the test is for equality or unsigned, and all 1 bits of the const are
1289 // in the same partial word, see if we can shorten the load.
1290 if (DCI.isBeforeLegalize() &&
1291 !ISD::isSignedIntSetCC(Cond) &&
1292 N0.getOpcode() == ISD::AND && C1 == 0 &&
1293 N0.getNode()->hasOneUse() &&
1294 isa<LoadSDNode>(N0.getOperand(0)) &&
1295 N0.getOperand(0).getNode()->hasOneUse() &&
1296 isa<ConstantSDNode>(N0.getOperand(1))) {
1297 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1299 unsigned bestWidth = 0, bestOffset = 0;
1300 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1301 unsigned origWidth = N0.getValueType().getSizeInBits();
1302 unsigned maskWidth = origWidth;
1303 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1304 // 8 bits, but have to be careful...
1305 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1306 origWidth = Lod->getMemoryVT().getSizeInBits();
1308 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1309 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1310 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1311 for (unsigned offset=0; offset<origWidth/width; offset++) {
1312 if ((newMask & Mask) == Mask) {
1313 if (!getDataLayout()->isLittleEndian())
1314 bestOffset = (origWidth/width - offset - 1) * (width/8);
1316 bestOffset = (uint64_t)offset * (width/8);
1317 bestMask = Mask.lshr(offset * (width/8) * 8);
1321 newMask = newMask << width;
1326 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1327 if (newVT.isRound()) {
1328 EVT PtrType = Lod->getOperand(1).getValueType();
1329 SDValue Ptr = Lod->getBasePtr();
1330 if (bestOffset != 0)
1331 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1332 DAG.getConstant(bestOffset, PtrType));
1333 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1334 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1335 Lod->getPointerInfo().getWithOffset(bestOffset),
1336 false, false, false, NewAlign);
1337 return DAG.getSetCC(dl, VT,
1338 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1339 DAG.getConstant(bestMask.trunc(bestWidth),
1341 DAG.getConstant(0LL, newVT), Cond);
1346 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1347 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1348 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1350 // If the comparison constant has bits in the upper part, the
1351 // zero-extended value could never match.
1352 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1353 C1.getBitWidth() - InSize))) {
1357 case ISD::SETEQ: return DAG.getConstant(0, VT);
1360 case ISD::SETNE: return DAG.getConstant(1, VT);
1363 // True if the sign bit of C1 is set.
1364 return DAG.getConstant(C1.isNegative(), VT);
1367 // True if the sign bit of C1 isn't set.
1368 return DAG.getConstant(C1.isNonNegative(), VT);
1374 // Otherwise, we can perform the comparison with the low bits.
1382 EVT newVT = N0.getOperand(0).getValueType();
1383 if (DCI.isBeforeLegalizeOps() ||
1384 (isOperationLegal(ISD::SETCC, newVT) &&
1385 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1386 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1387 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1389 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1391 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT);
1396 break; // todo, be more careful with signed comparisons
1398 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1399 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1400 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1401 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1402 EVT ExtDstTy = N0.getValueType();
1403 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1405 // If the constant doesn't fit into the number of bits for the source of
1406 // the sign extension, it is impossible for both sides to be equal.
1407 if (C1.getMinSignedBits() > ExtSrcTyBits)
1408 return DAG.getConstant(Cond == ISD::SETNE, VT);
1411 EVT Op0Ty = N0.getOperand(0).getValueType();
1412 if (Op0Ty == ExtSrcTy) {
1413 ZextOp = N0.getOperand(0);
1415 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1416 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1417 DAG.getConstant(Imm, Op0Ty));
1419 if (!DCI.isCalledByLegalizer())
1420 DCI.AddToWorklist(ZextOp.getNode());
1421 // Otherwise, make this a use of a zext.
1422 return DAG.getSetCC(dl, VT, ZextOp,
1423 DAG.getConstant(C1 & APInt::getLowBitsSet(
1428 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1429 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1430 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1431 if (N0.getOpcode() == ISD::SETCC &&
1432 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1433 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1435 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1436 // Invert the condition.
1437 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1438 CC = ISD::getSetCCInverse(CC,
1439 N0.getOperand(0).getValueType().isInteger());
1440 if (DCI.isBeforeLegalizeOps() ||
1441 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1442 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1445 if ((N0.getOpcode() == ISD::XOR ||
1446 (N0.getOpcode() == ISD::AND &&
1447 N0.getOperand(0).getOpcode() == ISD::XOR &&
1448 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1449 isa<ConstantSDNode>(N0.getOperand(1)) &&
1450 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1451 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1452 // can only do this if the top bits are known zero.
1453 unsigned BitWidth = N0.getValueSizeInBits();
1454 if (DAG.MaskedValueIsZero(N0,
1455 APInt::getHighBitsSet(BitWidth,
1457 // Okay, get the un-inverted input value.
1459 if (N0.getOpcode() == ISD::XOR)
1460 Val = N0.getOperand(0);
1462 assert(N0.getOpcode() == ISD::AND &&
1463 N0.getOperand(0).getOpcode() == ISD::XOR);
1464 // ((X^1)&1)^1 -> X & 1
1465 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1466 N0.getOperand(0).getOperand(0),
1470 return DAG.getSetCC(dl, VT, Val, N1,
1471 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1473 } else if (N1C->getAPIntValue() == 1 &&
1475 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
1477 if (Op0.getOpcode() == ISD::TRUNCATE)
1478 Op0 = Op0.getOperand(0);
1480 if ((Op0.getOpcode() == ISD::XOR) &&
1481 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1482 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1483 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1484 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1485 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1488 if (Op0.getOpcode() == ISD::AND &&
1489 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1490 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1491 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1492 if (Op0.getValueType().bitsGT(VT))
1493 Op0 = DAG.getNode(ISD::AND, dl, VT,
1494 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1495 DAG.getConstant(1, VT));
1496 else if (Op0.getValueType().bitsLT(VT))
1497 Op0 = DAG.getNode(ISD::AND, dl, VT,
1498 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1499 DAG.getConstant(1, VT));
1501 return DAG.getSetCC(dl, VT, Op0,
1502 DAG.getConstant(0, Op0.getValueType()),
1503 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1505 if (Op0.getOpcode() == ISD::AssertZext &&
1506 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1507 return DAG.getSetCC(dl, VT, Op0,
1508 DAG.getConstant(0, Op0.getValueType()),
1509 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1513 APInt MinVal, MaxVal;
1514 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1515 if (ISD::isSignedIntSetCC(Cond)) {
1516 MinVal = APInt::getSignedMinValue(OperandBitSize);
1517 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1519 MinVal = APInt::getMinValue(OperandBitSize);
1520 MaxVal = APInt::getMaxValue(OperandBitSize);
1523 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1524 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1525 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1526 // X >= C0 --> X > (C0 - 1)
1528 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1529 if ((DCI.isBeforeLegalizeOps() ||
1530 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1531 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1532 isLegalICmpImmediate(C.getSExtValue())))) {
1533 return DAG.getSetCC(dl, VT, N0,
1534 DAG.getConstant(C, N1.getValueType()),
1539 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1540 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1541 // X <= C0 --> X < (C0 + 1)
1543 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1544 if ((DCI.isBeforeLegalizeOps() ||
1545 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1546 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1547 isLegalICmpImmediate(C.getSExtValue())))) {
1548 return DAG.getSetCC(dl, VT, N0,
1549 DAG.getConstant(C, N1.getValueType()),
1554 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1555 return DAG.getConstant(0, VT); // X < MIN --> false
1556 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1557 return DAG.getConstant(1, VT); // X >= MIN --> true
1558 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1559 return DAG.getConstant(0, VT); // X > MAX --> false
1560 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1561 return DAG.getConstant(1, VT); // X <= MAX --> true
1563 // Canonicalize setgt X, Min --> setne X, Min
1564 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1565 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1566 // Canonicalize setlt X, Max --> setne X, Max
1567 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1568 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1570 // If we have setult X, 1, turn it into seteq X, 0
1571 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1572 return DAG.getSetCC(dl, VT, N0,
1573 DAG.getConstant(MinVal, N0.getValueType()),
1575 // If we have setugt X, Max-1, turn it into seteq X, Max
1576 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1577 return DAG.getSetCC(dl, VT, N0,
1578 DAG.getConstant(MaxVal, N0.getValueType()),
1581 // If we have "setcc X, C0", check to see if we can shrink the immediate
1584 // SETUGT X, SINTMAX -> SETLT X, 0
1585 if (Cond == ISD::SETUGT &&
1586 C1 == APInt::getSignedMaxValue(OperandBitSize))
1587 return DAG.getSetCC(dl, VT, N0,
1588 DAG.getConstant(0, N1.getValueType()),
1591 // SETULT X, SINTMIN -> SETGT X, -1
1592 if (Cond == ISD::SETULT &&
1593 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1594 SDValue ConstMinusOne =
1595 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1597 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1600 // Fold bit comparisons when we can.
1601 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1602 (VT == N0.getValueType() ||
1603 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1604 N0.getOpcode() == ISD::AND)
1605 if (ConstantSDNode *AndRHS =
1606 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1607 EVT ShiftTy = DCI.isBeforeLegalize() ?
1608 getPointerTy() : getShiftAmountTy(N0.getValueType());
1609 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1610 // Perform the xform if the AND RHS is a single bit.
1611 if (AndRHS->getAPIntValue().isPowerOf2()) {
1612 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1613 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1614 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1616 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1617 // (X & 8) == 8 --> (X & 8) >> 3
1618 // Perform the xform if C1 is a single bit.
1619 if (C1.isPowerOf2()) {
1620 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1621 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1622 DAG.getConstant(C1.logBase2(), ShiftTy)));
1627 if (C1.getMinSignedBits() <= 64 &&
1628 !isLegalICmpImmediate(C1.getSExtValue())) {
1629 // (X & -256) == 256 -> (X >> 8) == 1
1630 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1631 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1632 if (ConstantSDNode *AndRHS =
1633 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1634 const APInt &AndRHSC = AndRHS->getAPIntValue();
1635 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1636 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1637 EVT ShiftTy = DCI.isBeforeLegalize() ?
1638 getPointerTy() : getShiftAmountTy(N0.getValueType());
1639 EVT CmpTy = N0.getValueType();
1640 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1641 DAG.getConstant(ShiftBits, ShiftTy));
1642 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1643 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1646 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1647 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1648 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1649 // X < 0x100000000 -> (X >> 32) < 1
1650 // X >= 0x100000000 -> (X >> 32) >= 1
1651 // X <= 0x0ffffffff -> (X >> 32) < 1
1652 // X > 0x0ffffffff -> (X >> 32) >= 1
1655 ISD::CondCode NewCond = Cond;
1657 ShiftBits = C1.countTrailingOnes();
1659 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1661 ShiftBits = C1.countTrailingZeros();
1663 NewC = NewC.lshr(ShiftBits);
1664 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1665 EVT ShiftTy = DCI.isBeforeLegalize() ?
1666 getPointerTy() : getShiftAmountTy(N0.getValueType());
1667 EVT CmpTy = N0.getValueType();
1668 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1669 DAG.getConstant(ShiftBits, ShiftTy));
1670 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1671 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1677 if (isa<ConstantFPSDNode>(N0.getNode())) {
1678 // Constant fold or commute setcc.
1679 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1680 if (O.getNode()) return O;
1681 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1682 // If the RHS of an FP comparison is a constant, simplify it away in
1684 if (CFP->getValueAPF().isNaN()) {
1685 // If an operand is known to be a nan, we can fold it.
1686 switch (ISD::getUnorderedFlavor(Cond)) {
1687 default: llvm_unreachable("Unknown flavor!");
1688 case 0: // Known false.
1689 return DAG.getConstant(0, VT);
1690 case 1: // Known true.
1691 return DAG.getConstant(1, VT);
1692 case 2: // Undefined.
1693 return DAG.getUNDEF(VT);
1697 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1698 // constant if knowing that the operand is non-nan is enough. We prefer to
1699 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1701 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1702 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1704 // If the condition is not legal, see if we can find an equivalent one
1706 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1707 // If the comparison was an awkward floating-point == or != and one of
1708 // the comparison operands is infinity or negative infinity, convert the
1709 // condition to a less-awkward <= or >=.
1710 if (CFP->getValueAPF().isInfinity()) {
1711 if (CFP->getValueAPF().isNegative()) {
1712 if (Cond == ISD::SETOEQ &&
1713 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1714 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1715 if (Cond == ISD::SETUEQ &&
1716 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1717 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1718 if (Cond == ISD::SETUNE &&
1719 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1720 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1721 if (Cond == ISD::SETONE &&
1722 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1723 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1725 if (Cond == ISD::SETOEQ &&
1726 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1727 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1728 if (Cond == ISD::SETUEQ &&
1729 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1730 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1731 if (Cond == ISD::SETUNE &&
1732 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1733 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1734 if (Cond == ISD::SETONE &&
1735 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1736 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1743 // The sext(setcc()) => setcc() optimization relies on the appropriate
1744 // constant being emitted.
1746 switch (getBooleanContents(N0.getValueType().isVector())) {
1747 case UndefinedBooleanContent:
1748 case ZeroOrOneBooleanContent:
1749 EqVal = ISD::isTrueWhenEqual(Cond);
1751 case ZeroOrNegativeOneBooleanContent:
1752 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1756 // We can always fold X == X for integer setcc's.
1757 if (N0.getValueType().isInteger()) {
1758 return DAG.getConstant(EqVal, VT);
1760 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1761 if (UOF == 2) // FP operators that are undefined on NaNs.
1762 return DAG.getConstant(EqVal, VT);
1763 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1764 return DAG.getConstant(EqVal, VT);
1765 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1766 // if it is not already.
1767 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1768 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1769 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1770 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1773 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1774 N0.getValueType().isInteger()) {
1775 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1776 N0.getOpcode() == ISD::XOR) {
1777 // Simplify (X+Y) == (X+Z) --> Y == Z
1778 if (N0.getOpcode() == N1.getOpcode()) {
1779 if (N0.getOperand(0) == N1.getOperand(0))
1780 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1781 if (N0.getOperand(1) == N1.getOperand(1))
1782 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1783 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1784 // If X op Y == Y op X, try other combinations.
1785 if (N0.getOperand(0) == N1.getOperand(1))
1786 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1788 if (N0.getOperand(1) == N1.getOperand(0))
1789 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1794 // If RHS is a legal immediate value for a compare instruction, we need
1795 // to be careful about increasing register pressure needlessly.
1796 bool LegalRHSImm = false;
1798 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1799 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1800 // Turn (X+C1) == C2 --> X == C2-C1
1801 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1802 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1803 DAG.getConstant(RHSC->getAPIntValue()-
1804 LHSR->getAPIntValue(),
1805 N0.getValueType()), Cond);
1808 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1809 if (N0.getOpcode() == ISD::XOR)
1810 // If we know that all of the inverted bits are zero, don't bother
1811 // performing the inversion.
1812 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1814 DAG.getSetCC(dl, VT, N0.getOperand(0),
1815 DAG.getConstant(LHSR->getAPIntValue() ^
1816 RHSC->getAPIntValue(),
1821 // Turn (C1-X) == C2 --> X == C1-C2
1822 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1823 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1825 DAG.getSetCC(dl, VT, N0.getOperand(1),
1826 DAG.getConstant(SUBC->getAPIntValue() -
1827 RHSC->getAPIntValue(),
1833 // Could RHSC fold directly into a compare?
1834 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1835 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1838 // Simplify (X+Z) == X --> Z == 0
1839 // Don't do this if X is an immediate that can fold into a cmp
1840 // instruction and X+Z has other uses. It could be an induction variable
1841 // chain, and the transform would increase register pressure.
1842 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1843 if (N0.getOperand(0) == N1)
1844 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1845 DAG.getConstant(0, N0.getValueType()), Cond);
1846 if (N0.getOperand(1) == N1) {
1847 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1848 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1849 DAG.getConstant(0, N0.getValueType()), Cond);
1850 if (N0.getNode()->hasOneUse()) {
1851 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1852 // (Z-X) == X --> Z == X<<1
1853 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1854 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1855 if (!DCI.isCalledByLegalizer())
1856 DCI.AddToWorklist(SH.getNode());
1857 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1863 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1864 N1.getOpcode() == ISD::XOR) {
1865 // Simplify X == (X+Z) --> Z == 0
1866 if (N1.getOperand(0) == N0)
1867 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1868 DAG.getConstant(0, N1.getValueType()), Cond);
1869 if (N1.getOperand(1) == N0) {
1870 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1871 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1872 DAG.getConstant(0, N1.getValueType()), Cond);
1873 if (N1.getNode()->hasOneUse()) {
1874 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1875 // X == (Z-X) --> X<<1 == Z
1876 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1877 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1878 if (!DCI.isCalledByLegalizer())
1879 DCI.AddToWorklist(SH.getNode());
1880 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1885 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1886 // Note that where y is variable and is known to have at most
1887 // one bit set (for example, if it is z&1) we cannot do this;
1888 // the expressions are not equivalent when y==0.
1889 if (N0.getOpcode() == ISD::AND)
1890 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1891 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1892 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1893 if (DCI.isBeforeLegalizeOps() ||
1894 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1895 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1896 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1900 if (N1.getOpcode() == ISD::AND)
1901 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1902 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1903 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1904 if (DCI.isBeforeLegalizeOps() ||
1905 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1906 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1907 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1913 // Fold away ALL boolean setcc's.
1915 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1917 default: llvm_unreachable("Unknown integer setcc!");
1918 case ISD::SETEQ: // X == Y -> ~(X^Y)
1919 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1920 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1921 if (!DCI.isCalledByLegalizer())
1922 DCI.AddToWorklist(Temp.getNode());
1924 case ISD::SETNE: // X != Y --> (X^Y)
1925 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1927 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1928 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1929 Temp = DAG.getNOT(dl, N0, MVT::i1);
1930 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1931 if (!DCI.isCalledByLegalizer())
1932 DCI.AddToWorklist(Temp.getNode());
1934 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1935 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1936 Temp = DAG.getNOT(dl, N1, MVT::i1);
1937 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1938 if (!DCI.isCalledByLegalizer())
1939 DCI.AddToWorklist(Temp.getNode());
1941 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1942 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1943 Temp = DAG.getNOT(dl, N0, MVT::i1);
1944 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1945 if (!DCI.isCalledByLegalizer())
1946 DCI.AddToWorklist(Temp.getNode());
1948 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1949 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1950 Temp = DAG.getNOT(dl, N1, MVT::i1);
1951 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1954 if (VT != MVT::i1) {
1955 if (!DCI.isCalledByLegalizer())
1956 DCI.AddToWorklist(N0.getNode());
1957 // FIXME: If running after legalize, we probably can't do this.
1958 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1963 // Could not fold it.
1967 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1968 /// node is a GlobalAddress + offset.
1969 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
1970 int64_t &Offset) const {
1971 if (isa<GlobalAddressSDNode>(N)) {
1972 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
1973 GA = GASD->getGlobal();
1974 Offset += GASD->getOffset();
1978 if (N->getOpcode() == ISD::ADD) {
1979 SDValue N1 = N->getOperand(0);
1980 SDValue N2 = N->getOperand(1);
1981 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
1982 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
1984 Offset += V->getSExtValue();
1987 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
1988 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
1990 Offset += V->getSExtValue();
2000 SDValue TargetLowering::
2001 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2002 // Default implementation: no optimization.
2006 //===----------------------------------------------------------------------===//
2007 // Inline Assembler Implementation Methods
2008 //===----------------------------------------------------------------------===//
2011 TargetLowering::ConstraintType
2012 TargetLowering::getConstraintType(const std::string &Constraint) const {
2013 unsigned S = Constraint.size();
2016 switch (Constraint[0]) {
2018 case 'r': return C_RegisterClass;
2020 case 'o': // offsetable
2021 case 'V': // not offsetable
2023 case 'i': // Simple Integer or Relocatable Constant
2024 case 'n': // Simple Integer
2025 case 'E': // Floating Point Constant
2026 case 'F': // Floating Point Constant
2027 case 's': // Relocatable Constant
2028 case 'p': // Address.
2029 case 'X': // Allow ANY value.
2030 case 'I': // Target registers.
2044 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2045 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2052 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2053 /// with another that has more specific requirements based on the type of the
2054 /// corresponding operand.
2055 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2056 if (ConstraintVT.isInteger())
2058 if (ConstraintVT.isFloatingPoint())
2059 return "f"; // works for many targets
2063 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2064 /// vector. If it is invalid, don't add anything to Ops.
2065 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2066 std::string &Constraint,
2067 std::vector<SDValue> &Ops,
2068 SelectionDAG &DAG) const {
2070 if (Constraint.length() > 1) return;
2072 char ConstraintLetter = Constraint[0];
2073 switch (ConstraintLetter) {
2075 case 'X': // Allows any operand; labels (basic block) use this.
2076 if (Op.getOpcode() == ISD::BasicBlock) {
2081 case 'i': // Simple Integer or Relocatable Constant
2082 case 'n': // Simple Integer
2083 case 's': { // Relocatable Constant
2084 // These operands are interested in values of the form (GV+C), where C may
2085 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2086 // is possible and fine if either GV or C are missing.
2087 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2088 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2090 // If we have "(add GV, C)", pull out GV/C
2091 if (Op.getOpcode() == ISD::ADD) {
2092 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2093 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2095 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2096 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2099 C = nullptr, GA = nullptr;
2102 // If we find a valid operand, map to the TargetXXX version so that the
2103 // value itself doesn't get selected.
2104 if (GA) { // Either &GV or &GV+C
2105 if (ConstraintLetter != 'n') {
2106 int64_t Offs = GA->getOffset();
2107 if (C) Offs += C->getZExtValue();
2108 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2109 C ? SDLoc(C) : SDLoc(),
2110 Op.getValueType(), Offs));
2114 if (C) { // just C, no GV.
2115 // Simple constants are not allowed for 's'.
2116 if (ConstraintLetter != 's') {
2117 // gcc prints these as sign extended. Sign extend value to 64 bits
2118 // now; without this it would get ZExt'd later in
2119 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2120 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2130 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2131 getRegForInlineAsmConstraint(const std::string &Constraint,
2133 if (Constraint.empty() || Constraint[0] != '{')
2134 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2135 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2137 // Remove the braces from around the name.
2138 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2140 std::pair<unsigned, const TargetRegisterClass*> R =
2141 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2143 // Figure out which register class contains this reg.
2144 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo();
2145 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2146 E = RI->regclass_end(); RCI != E; ++RCI) {
2147 const TargetRegisterClass *RC = *RCI;
2149 // If none of the value types for this register class are valid, we
2150 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2154 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2156 if (RegName.equals_lower(RI->getName(*I))) {
2157 std::pair<unsigned, const TargetRegisterClass*> S =
2158 std::make_pair(*I, RC);
2160 // If this register class has the requested value type, return it,
2161 // otherwise keep searching and return the first class found
2162 // if no other is found which explicitly has the requested type.
2163 if (RC->hasType(VT))
2174 //===----------------------------------------------------------------------===//
2175 // Constraint Selection.
2177 /// isMatchingInputConstraint - Return true of this is an input operand that is
2178 /// a matching constraint like "4".
2179 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2180 assert(!ConstraintCode.empty() && "No known constraint!");
2181 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2184 /// getMatchedOperand - If this is an input matching constraint, this method
2185 /// returns the output operand it matches.
2186 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2187 assert(!ConstraintCode.empty() && "No known constraint!");
2188 return atoi(ConstraintCode.c_str());
2192 /// ParseConstraints - Split up the constraint string from the inline
2193 /// assembly value into the specific constraints and their prefixes,
2194 /// and also tie in the associated operand values.
2195 /// If this returns an empty vector, and if the constraint string itself
2196 /// isn't empty, there was an error parsing.
2197 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2198 ImmutableCallSite CS) const {
2199 /// ConstraintOperands - Information about all of the constraints.
2200 AsmOperandInfoVector ConstraintOperands;
2201 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2202 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2204 // Do a prepass over the constraints, canonicalizing them, and building up the
2205 // ConstraintOperands list.
2206 InlineAsm::ConstraintInfoVector
2207 ConstraintInfos = IA->ParseConstraints();
2209 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2210 unsigned ResNo = 0; // ResNo - The result number of the next output.
2212 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2213 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2214 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2216 // Update multiple alternative constraint count.
2217 if (OpInfo.multipleAlternatives.size() > maCount)
2218 maCount = OpInfo.multipleAlternatives.size();
2220 OpInfo.ConstraintVT = MVT::Other;
2222 // Compute the value type for each operand.
2223 switch (OpInfo.Type) {
2224 case InlineAsm::isOutput:
2225 // Indirect outputs just consume an argument.
2226 if (OpInfo.isIndirect) {
2227 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2231 // The return value of the call is this value. As such, there is no
2232 // corresponding argument.
2233 assert(!CS.getType()->isVoidTy() &&
2235 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2236 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2238 assert(ResNo == 0 && "Asm only has one result!");
2239 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2243 case InlineAsm::isInput:
2244 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2246 case InlineAsm::isClobber:
2251 if (OpInfo.CallOperandVal) {
2252 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2253 if (OpInfo.isIndirect) {
2254 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2256 report_fatal_error("Indirect operand for inline asm not a pointer!");
2257 OpTy = PtrTy->getElementType();
2260 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2261 if (StructType *STy = dyn_cast<StructType>(OpTy))
2262 if (STy->getNumElements() == 1)
2263 OpTy = STy->getElementType(0);
2265 // If OpTy is not a single value, it may be a struct/union that we
2266 // can tile with integers.
2267 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2268 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2277 OpInfo.ConstraintVT =
2278 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2281 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2283 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2284 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2286 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2291 // If we have multiple alternative constraints, select the best alternative.
2292 if (ConstraintInfos.size()) {
2294 unsigned bestMAIndex = 0;
2295 int bestWeight = -1;
2296 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2299 // Compute the sums of the weights for each alternative, keeping track
2300 // of the best (highest weight) one so far.
2301 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2303 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2304 cIndex != eIndex; ++cIndex) {
2305 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2306 if (OpInfo.Type == InlineAsm::isClobber)
2309 // If this is an output operand with a matching input operand,
2310 // look up the matching input. If their types mismatch, e.g. one
2311 // is an integer, the other is floating point, or their sizes are
2312 // different, flag it as an maCantMatch.
2313 if (OpInfo.hasMatchingInput()) {
2314 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2315 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2316 if ((OpInfo.ConstraintVT.isInteger() !=
2317 Input.ConstraintVT.isInteger()) ||
2318 (OpInfo.ConstraintVT.getSizeInBits() !=
2319 Input.ConstraintVT.getSizeInBits())) {
2320 weightSum = -1; // Can't match.
2325 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2330 weightSum += weight;
2333 if (weightSum > bestWeight) {
2334 bestWeight = weightSum;
2335 bestMAIndex = maIndex;
2339 // Now select chosen alternative in each constraint.
2340 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2341 cIndex != eIndex; ++cIndex) {
2342 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2343 if (cInfo.Type == InlineAsm::isClobber)
2345 cInfo.selectAlternative(bestMAIndex);
2350 // Check and hook up tied operands, choose constraint code to use.
2351 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2352 cIndex != eIndex; ++cIndex) {
2353 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2355 // If this is an output operand with a matching input operand, look up the
2356 // matching input. If their types mismatch, e.g. one is an integer, the
2357 // other is floating point, or their sizes are different, flag it as an
2359 if (OpInfo.hasMatchingInput()) {
2360 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2362 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2363 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2364 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2365 OpInfo.ConstraintVT);
2366 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2367 getRegForInlineAsmConstraint(Input.ConstraintCode,
2368 Input.ConstraintVT);
2369 if ((OpInfo.ConstraintVT.isInteger() !=
2370 Input.ConstraintVT.isInteger()) ||
2371 (MatchRC.second != InputRC.second)) {
2372 report_fatal_error("Unsupported asm: input constraint"
2373 " with a matching output constraint of"
2374 " incompatible type!");
2381 return ConstraintOperands;
2385 /// getConstraintGenerality - Return an integer indicating how general CT
2387 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2389 case TargetLowering::C_Other:
2390 case TargetLowering::C_Unknown:
2392 case TargetLowering::C_Register:
2394 case TargetLowering::C_RegisterClass:
2396 case TargetLowering::C_Memory:
2399 llvm_unreachable("Invalid constraint type");
2402 /// Examine constraint type and operand type and determine a weight value.
2403 /// This object must already have been set up with the operand type
2404 /// and the current alternative constraint selected.
2405 TargetLowering::ConstraintWeight
2406 TargetLowering::getMultipleConstraintMatchWeight(
2407 AsmOperandInfo &info, int maIndex) const {
2408 InlineAsm::ConstraintCodeVector *rCodes;
2409 if (maIndex >= (int)info.multipleAlternatives.size())
2410 rCodes = &info.Codes;
2412 rCodes = &info.multipleAlternatives[maIndex].Codes;
2413 ConstraintWeight BestWeight = CW_Invalid;
2415 // Loop over the options, keeping track of the most general one.
2416 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2417 ConstraintWeight weight =
2418 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2419 if (weight > BestWeight)
2420 BestWeight = weight;
2426 /// Examine constraint type and operand type and determine a weight value.
2427 /// This object must already have been set up with the operand type
2428 /// and the current alternative constraint selected.
2429 TargetLowering::ConstraintWeight
2430 TargetLowering::getSingleConstraintMatchWeight(
2431 AsmOperandInfo &info, const char *constraint) const {
2432 ConstraintWeight weight = CW_Invalid;
2433 Value *CallOperandVal = info.CallOperandVal;
2434 // If we don't have a value, we can't do a match,
2435 // but allow it at the lowest weight.
2436 if (!CallOperandVal)
2438 // Look at the constraint type.
2439 switch (*constraint) {
2440 case 'i': // immediate integer.
2441 case 'n': // immediate integer with a known value.
2442 if (isa<ConstantInt>(CallOperandVal))
2443 weight = CW_Constant;
2445 case 's': // non-explicit intregal immediate.
2446 if (isa<GlobalValue>(CallOperandVal))
2447 weight = CW_Constant;
2449 case 'E': // immediate float if host format.
2450 case 'F': // immediate float.
2451 if (isa<ConstantFP>(CallOperandVal))
2452 weight = CW_Constant;
2454 case '<': // memory operand with autodecrement.
2455 case '>': // memory operand with autoincrement.
2456 case 'm': // memory operand.
2457 case 'o': // offsettable memory operand
2458 case 'V': // non-offsettable memory operand
2461 case 'r': // general register.
2462 case 'g': // general register, memory operand or immediate integer.
2463 // note: Clang converts "g" to "imr".
2464 if (CallOperandVal->getType()->isIntegerTy())
2465 weight = CW_Register;
2467 case 'X': // any operand.
2469 weight = CW_Default;
2475 /// ChooseConstraint - If there are multiple different constraints that we
2476 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2477 /// This is somewhat tricky: constraints fall into four classes:
2478 /// Other -> immediates and magic values
2479 /// Register -> one specific register
2480 /// RegisterClass -> a group of regs
2481 /// Memory -> memory
2482 /// Ideally, we would pick the most specific constraint possible: if we have
2483 /// something that fits into a register, we would pick it. The problem here
2484 /// is that if we have something that could either be in a register or in
2485 /// memory that use of the register could cause selection of *other*
2486 /// operands to fail: they might only succeed if we pick memory. Because of
2487 /// this the heuristic we use is:
2489 /// 1) If there is an 'other' constraint, and if the operand is valid for
2490 /// that constraint, use it. This makes us take advantage of 'i'
2491 /// constraints when available.
2492 /// 2) Otherwise, pick the most general constraint present. This prefers
2493 /// 'm' over 'r', for example.
2495 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2496 const TargetLowering &TLI,
2497 SDValue Op, SelectionDAG *DAG) {
2498 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2499 unsigned BestIdx = 0;
2500 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2501 int BestGenerality = -1;
2503 // Loop over the options, keeping track of the most general one.
2504 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2505 TargetLowering::ConstraintType CType =
2506 TLI.getConstraintType(OpInfo.Codes[i]);
2508 // If this is an 'other' constraint, see if the operand is valid for it.
2509 // For example, on X86 we might have an 'rI' constraint. If the operand
2510 // is an integer in the range [0..31] we want to use I (saving a load
2511 // of a register), otherwise we must use 'r'.
2512 if (CType == TargetLowering::C_Other && Op.getNode()) {
2513 assert(OpInfo.Codes[i].size() == 1 &&
2514 "Unhandled multi-letter 'other' constraint");
2515 std::vector<SDValue> ResultOps;
2516 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2518 if (!ResultOps.empty()) {
2525 // Things with matching constraints can only be registers, per gcc
2526 // documentation. This mainly affects "g" constraints.
2527 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2530 // This constraint letter is more general than the previous one, use it.
2531 int Generality = getConstraintGenerality(CType);
2532 if (Generality > BestGenerality) {
2535 BestGenerality = Generality;
2539 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2540 OpInfo.ConstraintType = BestType;
2543 /// ComputeConstraintToUse - Determines the constraint code and constraint
2544 /// type to use for the specific AsmOperandInfo, setting
2545 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2546 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2548 SelectionDAG *DAG) const {
2549 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2551 // Single-letter constraints ('r') are very common.
2552 if (OpInfo.Codes.size() == 1) {
2553 OpInfo.ConstraintCode = OpInfo.Codes[0];
2554 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2556 ChooseConstraint(OpInfo, *this, Op, DAG);
2559 // 'X' matches anything.
2560 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2561 // Labels and constants are handled elsewhere ('X' is the only thing
2562 // that matches labels). For Functions, the type here is the type of
2563 // the result, which is not what we want to look at; leave them alone.
2564 Value *v = OpInfo.CallOperandVal;
2565 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2566 OpInfo.CallOperandVal = v;
2570 // Otherwise, try to resolve it to something we know about by looking at
2571 // the actual operand type.
2572 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2573 OpInfo.ConstraintCode = Repl;
2574 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2579 /// \brief Given an exact SDIV by a constant, create a multiplication
2580 /// with the multiplicative inverse of the constant.
2581 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2582 SelectionDAG &DAG) const {
2583 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2584 APInt d = C->getAPIntValue();
2585 assert(d != 0 && "Division by zero!");
2587 // Shift the value upfront if it is even, so the LSB is one.
2588 unsigned ShAmt = d.countTrailingZeros();
2590 // TODO: For UDIV use SRL instead of SRA.
2591 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2592 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
2596 // Calculate the multiplicative inverse, using Newton's method.
2598 while ((t = d*xn) != 1)
2599 xn *= APInt(d.getBitWidth(), 2) - t;
2601 Op2 = DAG.getConstant(xn, Op1.getValueType());
2602 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2605 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2606 /// return a DAG expression to select that will generate the same value by
2607 /// multiplying by a magic number. See:
2608 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2609 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2610 SelectionDAG &DAG, bool IsAfterLegalization,
2611 std::vector<SDNode *> *Created) const {
2612 EVT VT = N->getValueType(0);
2615 // Check to see if we can do this.
2616 // FIXME: We should be more aggressive here.
2617 if (!isTypeLegal(VT))
2620 APInt::ms magics = Divisor.magic();
2622 // Multiply the numerator (operand 0) by the magic value
2623 // FIXME: We should support doing a MUL in a wider type
2625 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2626 isOperationLegalOrCustom(ISD::MULHS, VT))
2627 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2628 DAG.getConstant(magics.m, VT));
2629 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2630 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2631 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2633 DAG.getConstant(magics.m, VT)).getNode(), 1);
2635 return SDValue(); // No mulhs or equvialent
2636 // If d > 0 and m < 0, add the numerator
2637 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2638 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2640 Created->push_back(Q.getNode());
2642 // If d < 0 and m > 0, subtract the numerator.
2643 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2644 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2646 Created->push_back(Q.getNode());
2648 // Shift right algebraic if shift value is nonzero
2650 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2651 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2653 Created->push_back(Q.getNode());
2655 // Extract the sign bit and add it to the quotient
2656 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2657 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2658 getShiftAmountTy(Q.getValueType())));
2660 Created->push_back(T.getNode());
2661 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2664 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2665 /// return a DAG expression to select that will generate the same value by
2666 /// multiplying by a magic number. See:
2667 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2668 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2669 SelectionDAG &DAG, bool IsAfterLegalization,
2670 std::vector<SDNode *> *Created) const {
2671 EVT VT = N->getValueType(0);
2674 // Check to see if we can do this.
2675 // FIXME: We should be more aggressive here.
2676 if (!isTypeLegal(VT))
2679 // FIXME: We should use a narrower constant when the upper
2680 // bits are known to be zero.
2681 APInt::mu magics = Divisor.magicu();
2683 SDValue Q = N->getOperand(0);
2685 // If the divisor is even, we can avoid using the expensive fixup by shifting
2686 // the divided value upfront.
2687 if (magics.a != 0 && !Divisor[0]) {
2688 unsigned Shift = Divisor.countTrailingZeros();
2689 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2690 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2692 Created->push_back(Q.getNode());
2694 // Get magic number for the shifted divisor.
2695 magics = Divisor.lshr(Shift).magicu(Shift);
2696 assert(magics.a == 0 && "Should use cheap fixup now");
2699 // Multiply the numerator (operand 0) by the magic value
2700 // FIXME: We should support doing a MUL in a wider type
2701 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2702 isOperationLegalOrCustom(ISD::MULHU, VT))
2703 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2704 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2705 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2706 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2707 DAG.getConstant(magics.m, VT)).getNode(), 1);
2709 return SDValue(); // No mulhu or equvialent
2711 Created->push_back(Q.getNode());
2713 if (magics.a == 0) {
2714 assert(magics.s < Divisor.getBitWidth() &&
2715 "We shouldn't generate an undefined shift!");
2716 return DAG.getNode(ISD::SRL, dl, VT, Q,
2717 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2719 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2721 Created->push_back(NPQ.getNode());
2722 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2723 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2725 Created->push_back(NPQ.getNode());
2726 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2728 Created->push_back(NPQ.getNode());
2729 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2730 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2734 bool TargetLowering::
2735 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2736 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2737 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2738 "be a constant integer");
2745 //===----------------------------------------------------------------------===//
2746 // Legalization Utilities
2747 //===----------------------------------------------------------------------===//
2749 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2750 SelectionDAG &DAG, SDValue LL, SDValue LH,
2751 SDValue RL, SDValue RH) const {
2752 EVT VT = N->getValueType(0);
2755 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2756 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2757 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2758 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2759 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2760 unsigned OuterBitSize = VT.getSizeInBits();
2761 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2762 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2763 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2765 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2766 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2767 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2769 if (!LL.getNode() && !RL.getNode() &&
2770 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2771 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2772 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2778 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2779 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2780 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2781 // The inputs are both zero-extended.
2783 // We can emit a umul_lohi.
2784 Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2785 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2786 Hi = SDValue(Lo.getNode(), 1);
2790 // We can emit a mulhu+mul.
2791 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2792 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2796 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2797 // The input values are both sign-extended.
2799 // We can emit a smul_lohi.
2800 Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2801 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2802 Hi = SDValue(Lo.getNode(), 1);
2806 // We can emit a mulhs+mul.
2807 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2808 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2813 if (!LH.getNode() && !RH.getNode() &&
2814 isOperationLegalOrCustom(ISD::SRL, VT) &&
2815 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2816 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2817 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2818 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2819 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2820 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2821 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2828 // Lo,Hi = umul LHS, RHS.
2829 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2830 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2832 Hi = UMulLOHI.getValue(1);
2833 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2834 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2835 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2836 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2840 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2841 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2842 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2843 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2844 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2845 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);