1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/LLVMContext.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetIntrinsicInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include "llvm/Target/TargetSubtargetInfo.h"
59 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
63 #define DEBUG_TYPE "isel"
65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
71 STATISTIC(NumFastIselFailLowerArguments,
72 "Number of entry blocks where fast isel failed to lower arguments");
76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
77 cl::desc("Enable extra verbose messages in the \"fast\" "
78 "instruction selector"));
81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
89 // Standard binary operators...
90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
103 // Logical operators...
104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
108 // Memory instructions...
109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
117 // Convert instructions...
118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
131 // Other instructions...
132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
148 // Intrinsic instructions...
149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
150 STATISTIC(NumFastIselFailSAddWithOverflow,
151 "Fast isel fails on sadd.with.overflow");
152 STATISTIC(NumFastIselFailUAddWithOverflow,
153 "Fast isel fails on uadd.with.overflow");
154 STATISTIC(NumFastIselFailSSubWithOverflow,
155 "Fast isel fails on ssub.with.overflow");
156 STATISTIC(NumFastIselFailUSubWithOverflow,
157 "Fast isel fails on usub.with.overflow");
158 STATISTIC(NumFastIselFailSMulWithOverflow,
159 "Fast isel fails on smul.with.overflow");
160 STATISTIC(NumFastIselFailUMulWithOverflow,
161 "Fast isel fails on umul.with.overflow");
162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
170 cl::desc("Enable verbose messages in the \"fast\" "
171 "instruction selector"));
172 static cl::opt<int> EnableFastISelAbort(
173 "fast-isel-abort", cl::Hidden,
174 cl::desc("Enable abort calls when \"fast\" instruction selection "
175 "fails to lower an instruction: 0 disable the abort, 1 will "
176 "abort but for args, calls and terminators, 2 will also "
177 "abort for argument lowering, and 3 will never fallback "
178 "to SelectionDAG."));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None ||
297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
298 TLI->getSchedulingPreference() == Sched::Source)
299 return createSourceListDAGScheduler(IS, OptLevel);
300 if (TLI->getSchedulingPreference() == Sched::RegPressure)
301 return createBURRListDAGScheduler(IS, OptLevel);
302 if (TLI->getSchedulingPreference() == Sched::Hybrid)
303 return createHybridListDAGScheduler(IS, OptLevel);
304 if (TLI->getSchedulingPreference() == Sched::VLIW)
305 return createVLIWDAGScheduler(IS, OptLevel);
306 assert(TLI->getSchedulingPreference() == Sched::ILP &&
307 "Unknown sched type!");
308 return createILPListDAGScheduler(IS, OptLevel);
312 // EmitInstrWithCustomInserter - This method should be implemented by targets
313 // that mark instructions with the 'usesCustomInserter' flag. These
314 // instructions are special in various ways, which require special support to
315 // insert. The specified MachineInstr is created but not inserted into any
316 // basic blocks, and this method is called to expand it into a sequence of
317 // instructions, potentially also creating new basic blocks and control flow.
318 // When new basic blocks are inserted and the edges from MBB to its successors
319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
323 MachineBasicBlock *MBB) const {
325 dbgs() << "If a target marks an instruction with "
326 "'usesCustomInserter', it must implement "
327 "TargetLowering::EmitInstrWithCustomInserter!";
329 llvm_unreachable(nullptr);
332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
333 SDNode *Node) const {
334 assert(!MI->hasPostISelHook() &&
335 "If a target marks an instruction with 'hasPostISelHook', "
336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
339 //===----------------------------------------------------------------------===//
340 // SelectionDAGISel code
341 //===----------------------------------------------------------------------===//
343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
344 CodeGenOpt::Level OL) :
345 MachineFunctionPass(ID), TM(tm),
346 FuncInfo(new FunctionLoweringInfo()),
347 CurDAG(new SelectionDAG(tm, OL)),
348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
355 initializeTargetLibraryInfoWrapperPassPass(
356 *PassRegistry::getPassRegistry());
359 SelectionDAGISel::~SelectionDAGISel() {
365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.addRequired<AliasAnalysis>();
367 AU.addPreserved<AliasAnalysis>();
368 AU.addRequired<GCModuleInfo>();
369 AU.addPreserved<GCModuleInfo>();
370 AU.addRequired<TargetLibraryInfoWrapperPass>();
371 if (UseMBPI && OptLevel != CodeGenOpt::None)
372 AU.addRequired<BranchProbabilityInfo>();
373 MachineFunctionPass::getAnalysisUsage(AU);
376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
377 /// may trap on it. In this case we have to split the edge so that the path
378 /// through the predecessor block that doesn't go to the phi block doesn't
379 /// execute the possibly trapping instruction.
381 /// This is required for correctness, so it must be done at -O0.
383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
384 // Loop for blocks with phi nodes.
385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
386 PHINode *PN = dyn_cast<PHINode>(BB->begin());
390 // For each block with a PHI node, check to see if any of the input values
391 // are potentially trapping constant expressions. Constant expressions are
392 // the only potentially trapping value that can occur as the argument to a
394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
397 if (!CE || !CE->canTrap()) continue;
399 // The only case we have to worry about is when the edge is critical.
400 // Since this block has a PHI Node, we assume it has multiple input
401 // edges: check to see if the pred has multiple successors.
402 BasicBlock *Pred = PN->getIncomingBlock(i);
403 if (Pred->getTerminator()->getNumSuccessors() == 1)
406 // Okay, we have to split this edge.
408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
416 // Do some sanity-checking on the command-line options.
417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
418 "-fast-isel-verbose requires -fast-isel");
419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
420 "-fast-isel-abort > 0 requires -fast-isel");
422 const Function &Fn = *mf.getFunction();
425 // Reset the target options before resetting the optimization
427 // FIXME: This is a horrible hack and should be processed via
428 // codegen looking at the optimization level explicitly when
429 // it wants to look at it.
430 TM.resetTargetOptions(Fn);
431 // Reset OptLevel to None for optnone functions.
432 CodeGenOpt::Level NewOptLevel = OptLevel;
433 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
434 NewOptLevel = CodeGenOpt::None;
435 OptLevelChanger OLC(*this, NewOptLevel);
437 TII = MF->getSubtarget().getInstrInfo();
438 TLI = MF->getSubtarget().getTargetLowering();
439 RegInfo = &MF->getRegInfo();
440 AA = &getAnalysis<AliasAnalysis>();
441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
449 FuncInfo->set(Fn, *MF, CurDAG);
451 if (UseMBPI && OptLevel != CodeGenOpt::None)
452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
454 FuncInfo->BPI = nullptr;
456 SDB->init(GFI, *AA, LibInfo);
458 MF->setHasInlineAsm(false);
460 SelectAllBasicBlocks(Fn);
462 // If the first basic block in the function has live ins that need to be
463 // copied into vregs, emit the copies into the top of the block before
464 // emitting the code for the block.
465 MachineBasicBlock *EntryMBB = MF->begin();
466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
469 DenseMap<unsigned, unsigned> LiveInMap;
470 if (!FuncInfo->ArgDbgValues.empty())
471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
472 E = RegInfo->livein_end(); LI != E; ++LI)
474 LiveInMap.insert(std::make_pair(LI->first, LI->second));
476 // Insert DBG_VALUE instructions for function arguments to the entry block.
477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
479 bool hasFI = MI->getOperand(0).isFI();
481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
482 if (TargetRegisterInfo::isPhysicalRegister(Reg))
483 EntryMBB->insert(EntryMBB->begin(), MI);
485 MachineInstr *Def = RegInfo->getVRegDef(Reg);
487 MachineBasicBlock::iterator InsertPos = Def;
488 // FIXME: VR def may not be in entry block.
489 Def->getParent()->insert(std::next(InsertPos), MI);
491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
495 // If Reg is live-in then update debug info to track its copy in a vreg.
496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
497 if (LDI != LiveInMap.end()) {
498 assert(!hasFI && "There's no handling of frame pointer updating here yet "
500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
501 MachineBasicBlock::iterator InsertPos = Def;
502 const MDNode *Variable = MI->getDebugVariable();
503 const MDNode *Expr = MI->getDebugExpression();
504 DebugLoc DL = MI->getDebugLoc();
505 bool IsIndirect = MI->isIndirectDebugValue();
506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
508 "Expected inlined-at fields to agree");
509 // Def is never a terminator here, so it is ok to increment InsertPos.
510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
511 IsIndirect, LDI->second, Offset, Variable, Expr);
513 // If this vreg is directly copied into an exported register then
514 // that COPY instructions also need DBG_VALUE, if it is the only
515 // user of LDI->second.
516 MachineInstr *CopyUseMI = nullptr;
517 for (MachineRegisterInfo::use_instr_iterator
518 UI = RegInfo->use_instr_begin(LDI->second),
519 E = RegInfo->use_instr_end(); UI != E; ) {
520 MachineInstr *UseMI = &*(UI++);
521 if (UseMI->isDebugValue()) continue;
522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
523 CopyUseMI = UseMI; continue;
525 // Otherwise this is another use or second copy use.
526 CopyUseMI = nullptr; break;
529 // Use MI's debug location, which describes where Variable was
530 // declared, rather than whatever is attached to CopyUseMI.
531 MachineInstr *NewMI =
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
534 MachineBasicBlock::iterator Pos = CopyUseMI;
535 EntryMBB->insertAfter(Pos, NewMI);
540 // Determine if there are any calls in this machine function.
541 MachineFrameInfo *MFI = MF->getFrameInfo();
542 for (const auto &MBB : *MF) {
543 if (MFI->hasCalls() && MF->hasInlineAsm())
546 for (const auto &MI : MBB) {
547 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
548 if ((MCID.isCall() && !MCID.isReturn()) ||
549 MI.isStackAligningInlineAsm()) {
550 MFI->setHasCalls(true);
552 if (MI.isInlineAsm()) {
553 MF->setHasInlineAsm(true);
558 // Determine if there is a call to setjmp in the machine function.
559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
561 // Replace forward-declared registers with the registers containing
562 // the desired value.
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 for (DenseMap<unsigned, unsigned>::iterator
565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
567 unsigned From = I->first;
568 unsigned To = I->second;
569 // If To is also scheduled to be replaced, find what its ultimate
572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
576 // Make sure the new register has a sufficiently constrained register class.
577 if (TargetRegisterInfo::isVirtualRegister(From) &&
578 TargetRegisterInfo::isVirtualRegister(To))
579 MRI.constrainRegClass(To, MRI.getRegClass(From));
581 MRI.replaceRegWith(From, To);
584 // Freeze the set of reserved registers now that MachineFrameInfo has been
585 // set up. All the information required by getReservedRegs() should be
587 MRI.freezeReservedRegs(*MF);
589 // Release function-specific state. SDB and CurDAG are already cleared
593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
594 DEBUG(MF->print(dbgs()));
599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
600 BasicBlock::const_iterator End,
602 // Lower the instructions. If a call is emitted as a tail call, cease emitting
603 // nodes for this block.
604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
607 // Make sure the root of the DAG is up-to-date.
608 CurDAG->setRoot(SDB->getControlRoot());
609 HadTailCall = SDB->HasTailCall;
612 // Final step, emit the lowered DAG as machine code.
616 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
617 SmallPtrSet<SDNode*, 128> VisitedNodes;
618 SmallVector<SDNode*, 128> Worklist;
620 Worklist.push_back(CurDAG->getRoot().getNode());
626 SDNode *N = Worklist.pop_back_val();
628 // If we've already seen this node, ignore it.
629 if (!VisitedNodes.insert(N).second)
632 // Otherwise, add all chain operands to the worklist.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
634 if (N->getOperand(i).getValueType() == MVT::Other)
635 Worklist.push_back(N->getOperand(i).getNode());
637 // If this is a CopyToReg with a vreg dest, process it.
638 if (N->getOpcode() != ISD::CopyToReg)
641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
642 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
645 // Ignore non-scalar or non-integer values.
646 SDValue Src = N->getOperand(2);
647 EVT SrcVT = Src.getValueType();
648 if (!SrcVT.isInteger() || SrcVT.isVector())
651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
654 } while (!Worklist.empty());
657 void SelectionDAGISel::CodeGenAndEmitDAG() {
658 std::string GroupName;
659 if (TimePassesIsEnabled)
660 GroupName = "Instruction Selection and Scheduling";
661 std::string BlockName;
662 int BlockNumber = -1;
664 bool MatchFilterBB = false; (void)MatchFilterBB;
666 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
667 FilterDAGBasicBlockName ==
668 FuncInfo->MBB->getBasicBlock()->getName().str());
671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
676 BlockNumber = FuncInfo->MBB->getNumber();
678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
681 << " '" << BlockName << "'\n"; CurDAG->dump());
683 if (ViewDAGCombine1 && MatchFilterBB)
684 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
686 // Run the DAG combiner in pre-legalize mode.
688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
693 << " '" << BlockName << "'\n"; CurDAG->dump());
695 // Second step, hack on the DAG until it only uses operations and types that
696 // the target supports.
697 if (ViewLegalizeTypesDAGs && MatchFilterBB)
698 CurDAG->viewGraph("legalize-types input for " + BlockName);
702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
703 Changed = CurDAG->LegalizeTypes();
706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
707 << " '" << BlockName << "'\n"; CurDAG->dump());
709 CurDAG->NewNodesMustHaveLegalTypes = true;
712 if (ViewDAGCombineLT && MatchFilterBB)
713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
715 // Run the DAG combiner in post-type-legalize mode.
717 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
718 TimePassesIsEnabled);
719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
723 << " '" << BlockName << "'\n"; CurDAG->dump());
728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
729 Changed = CurDAG->LegalizeVectors();
734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
735 CurDAG->LegalizeTypes();
738 if (ViewDAGCombineLT && MatchFilterBB)
739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
741 // Run the DAG combiner in post-type-legalize mode.
743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
744 TimePassesIsEnabled);
745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
752 if (ViewLegalizeDAGs && MatchFilterBB)
753 CurDAG->viewGraph("legalize input for " + BlockName);
756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
761 << " '" << BlockName << "'\n"; CurDAG->dump());
763 if (ViewDAGCombine2 && MatchFilterBB)
764 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
766 // Run the DAG combiner in post-legalize mode.
768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
775 if (OptLevel != CodeGenOpt::None)
776 ComputeLiveOutVRegInfo();
778 if (ViewISelDAGs && MatchFilterBB)
779 CurDAG->viewGraph("isel input for " + BlockName);
781 // Third, instruction select all of the operations to machine code, adding the
782 // code to the MachineBasicBlock.
784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
785 DoInstructionSelection();
788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
791 if (ViewSchedDAGs && MatchFilterBB)
792 CurDAG->viewGraph("scheduler input for " + BlockName);
794 // Schedule machine code.
795 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
797 NamedRegionTimer T("Instruction Scheduling", GroupName,
798 TimePassesIsEnabled);
799 Scheduler->Run(CurDAG, FuncInfo->MBB);
802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
804 // Emit machine code to BB. This can change 'BB' to the last block being
806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
810 // FuncInfo->InsertPt is passed by reference and set to the end of the
811 // scheduled instructions.
812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
815 // If the block was split, make sure we update any references that are used to
816 // update PHI nodes later on.
817 if (FirstMBB != LastMBB)
818 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
820 // Free the scheduler state.
822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
823 TimePassesIsEnabled);
827 // Free the SelectionDAG state, now that we're finished with it.
832 /// ISelUpdater - helper class to handle updates of the instruction selection
834 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
835 SelectionDAG::allnodes_iterator &ISelPosition;
837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
841 /// deleted is the current ISelPosition node, update ISelPosition.
843 void NodeDeleted(SDNode *N, SDNode *E) override {
844 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
848 } // end anonymous namespace
850 void SelectionDAGISel::DoInstructionSelection() {
851 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
852 << FuncInfo->MBB->getNumber()
853 << " '" << FuncInfo->MBB->getName() << "'\n");
857 // Select target instructions for the DAG.
859 // Number all nodes with a topological order and set DAGSize.
860 DAGSize = CurDAG->AssignTopologicalOrder();
862 // Create a dummy node (which is not added to allnodes), that adds
863 // a reference to the root node, preventing it from being deleted,
864 // and tracking any changes of the root.
865 HandleSDNode Dummy(CurDAG->getRoot());
866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
869 // Make sure that ISelPosition gets properly updated when nodes are deleted
870 // in calls made from this function.
871 ISelUpdater ISU(*CurDAG, ISelPosition);
873 // The AllNodes list is now topological-sorted. Visit the
874 // nodes by starting at the end of the list (the root of the
875 // graph) and preceding back toward the beginning (the entry
877 while (ISelPosition != CurDAG->allnodes_begin()) {
878 SDNode *Node = --ISelPosition;
879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
880 // but there are currently some corner cases that it misses. Also, this
881 // makes it theoretically possible to disable the DAGCombiner.
882 if (Node->use_empty())
885 SDNode *ResNode = Select(Node);
887 // FIXME: This is pretty gross. 'Select' should be changed to not return
888 // anything at all and this code should be nuked with a tactical strike.
890 // If node should not be replaced, continue with the next one.
891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
895 ReplaceUses(Node, ResNode);
898 // If after the replacement this node is not used any more,
899 // remove this dead node.
900 if (Node->use_empty()) // Don't delete EntryToken, etc.
901 CurDAG->RemoveDeadNode(Node);
904 CurDAG->setRoot(Dummy.getValue());
907 DEBUG(dbgs() << "===== Instruction selection ends:\n");
909 PostprocessISelDAG();
912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
913 /// do other setup for EH landing-pad blocks.
914 bool SelectionDAGISel::PrepareEHLandingPad() {
915 MachineBasicBlock *MBB = FuncInfo->MBB;
917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
919 // Add a label to mark the beginning of the landing pad. Deletion of the
920 // landing pad can thus be detected via the MachineModuleInfo.
921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
923 // Assign the call site to the landing pad's begin label.
924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
930 // If this is an MSVC-style personality function, we need to split the landing
931 // pad into several BBs.
932 const BasicBlock *LLVMBB = MBB->getBasicBlock();
933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
934 MF->getMMI().addPersonality(
935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts()));
936 EHPersonality Personality = MF->getMMI().getPersonalityType();
938 if (isMSVCEHPersonality(Personality)) {
939 SmallVector<MachineBasicBlock *, 4> ClauseBBs;
940 const IntrinsicInst *ActionsCall =
941 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt());
942 // Get all invoke BBs that unwind to this landingpad.
943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
945 if (ActionsCall && ActionsCall->getIntrinsicID() == Intrinsic::eh_actions) {
946 // If this is a call to llvm.eh.actions followed by indirectbr, then we've
947 // run WinEHPrepare, and we should remove this block from the machine CFG.
948 // Mark the targets of the indirectbr as landingpads instead.
949 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) {
950 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc];
951 // Add the edge from the invoke to the clause.
952 for (MachineBasicBlock *InvokeBB : InvokeBBs)
953 InvokeBB->addSuccessor(ClauseBB);
955 // Mark the clause as a landing pad or MI passes will delete it.
956 ClauseBB->setIsLandingPad();
959 // Otherwise, we haven't done the preparation, and we need to invent some
960 // clause basic blocks that branch into the landingpad.
961 // FIXME: Remove this code once SEH preparation works.
962 ActionsCall = nullptr;
964 // Make virtual registers and a series of labels that fill in values for
966 auto &RI = MF->getRegInfo();
967 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
969 // Emit separate machine basic blocks with separate labels for each clause
970 // before the main landing pad block.
971 MachineInstrBuilder SelectorPHI = BuildMI(
972 *MBB, MBB->begin(), SDB->getCurDebugLoc(),
973 TII->get(TargetOpcode::PHI), FuncInfo->ExceptionSelectorVirtReg);
974 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
975 // Skip filter clauses, we can't implement them.
976 if (LPadInst->isFilter(I))
979 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
980 MF->insert(MBB, ClauseBB);
982 // Add the edge from the invoke to the clause.
983 for (MachineBasicBlock *InvokeBB : InvokeBBs)
984 InvokeBB->addSuccessor(ClauseBB);
986 // Mark the clause as a landing pad or MI passes will delete it.
987 ClauseBB->setIsLandingPad();
989 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
991 // Start the BB with a label.
992 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
993 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
994 .addSym(ClauseLabel);
996 // Construct a simple BB that defines a register with the typeid
998 FuncInfo->MBB = ClauseBB;
999 FuncInfo->InsertPt = ClauseBB->end();
1000 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
1001 CurDAG->setRoot(SDB->getRoot());
1003 CodeGenAndEmitDAG();
1005 // Add the typeid virtual register to the phi in the main landing pad.
1006 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
1010 // Remove the edge from the invoke to the lpad.
1011 for (MachineBasicBlock *InvokeBB : InvokeBBs)
1012 InvokeBB->removeSuccessor(MBB);
1014 // Restore FuncInfo back to its previous state and select the main landing
1016 FuncInfo->MBB = MBB;
1017 FuncInfo->InsertPt = MBB->end();
1019 // Transfer EH state number assigned to the IR block to the MBB.
1020 if (Personality == EHPersonality::MSVC_CXX) {
1021 WinEHFuncInfo &FI = MF->getMMI().getWinEHFuncInfo(MF->getFunction());
1022 MF->getMMI().addWinEHState(MBB, FI.LandingPadStateMap[LPadInst]);
1025 // Select instructions for the landingpad if there was no llvm.eh.actions
1027 return ActionsCall == nullptr;
1030 // Mark exception register as live in.
1031 if (unsigned Reg = TLI->getExceptionPointerRegister())
1032 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1034 // Mark exception selector register as live in.
1035 if (unsigned Reg = TLI->getExceptionSelectorRegister())
1036 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1041 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1042 /// side-effect free and is either dead or folded into a generated instruction.
1043 /// Return false if it needs to be emitted.
1044 static bool isFoldedOrDeadInstruction(const Instruction *I,
1045 FunctionLoweringInfo *FuncInfo) {
1046 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1047 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1048 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1049 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1050 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1054 // Collect per Instruction statistics for fast-isel misses. Only those
1055 // instructions that cause the bail are accounted for. It does not account for
1056 // instructions higher in the block. Thus, summing the per instructions stats
1057 // will not add up to what is reported by NumFastIselFailures.
1058 static void collectFailStats(const Instruction *I) {
1059 switch (I->getOpcode()) {
1060 default: assert (0 && "<Invalid operator> ");
1063 case Instruction::Ret: NumFastIselFailRet++; return;
1064 case Instruction::Br: NumFastIselFailBr++; return;
1065 case Instruction::Switch: NumFastIselFailSwitch++; return;
1066 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1067 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1068 case Instruction::Resume: NumFastIselFailResume++; return;
1069 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1071 // Standard binary operators...
1072 case Instruction::Add: NumFastIselFailAdd++; return;
1073 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1074 case Instruction::Sub: NumFastIselFailSub++; return;
1075 case Instruction::FSub: NumFastIselFailFSub++; return;
1076 case Instruction::Mul: NumFastIselFailMul++; return;
1077 case Instruction::FMul: NumFastIselFailFMul++; return;
1078 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1079 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1080 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1081 case Instruction::URem: NumFastIselFailURem++; return;
1082 case Instruction::SRem: NumFastIselFailSRem++; return;
1083 case Instruction::FRem: NumFastIselFailFRem++; return;
1085 // Logical operators...
1086 case Instruction::And: NumFastIselFailAnd++; return;
1087 case Instruction::Or: NumFastIselFailOr++; return;
1088 case Instruction::Xor: NumFastIselFailXor++; return;
1090 // Memory instructions...
1091 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1092 case Instruction::Load: NumFastIselFailLoad++; return;
1093 case Instruction::Store: NumFastIselFailStore++; return;
1094 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1095 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1096 case Instruction::Fence: NumFastIselFailFence++; return;
1097 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1099 // Convert instructions...
1100 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1101 case Instruction::ZExt: NumFastIselFailZExt++; return;
1102 case Instruction::SExt: NumFastIselFailSExt++; return;
1103 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1104 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1105 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1106 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1107 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1108 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1109 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1110 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1111 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1113 // Other instructions...
1114 case Instruction::ICmp: NumFastIselFailICmp++; return;
1115 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1116 case Instruction::PHI: NumFastIselFailPHI++; return;
1117 case Instruction::Select: NumFastIselFailSelect++; return;
1118 case Instruction::Call: {
1119 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1120 switch (Intrinsic->getIntrinsicID()) {
1122 NumFastIselFailIntrinsicCall++; return;
1123 case Intrinsic::sadd_with_overflow:
1124 NumFastIselFailSAddWithOverflow++; return;
1125 case Intrinsic::uadd_with_overflow:
1126 NumFastIselFailUAddWithOverflow++; return;
1127 case Intrinsic::ssub_with_overflow:
1128 NumFastIselFailSSubWithOverflow++; return;
1129 case Intrinsic::usub_with_overflow:
1130 NumFastIselFailUSubWithOverflow++; return;
1131 case Intrinsic::smul_with_overflow:
1132 NumFastIselFailSMulWithOverflow++; return;
1133 case Intrinsic::umul_with_overflow:
1134 NumFastIselFailUMulWithOverflow++; return;
1135 case Intrinsic::frameaddress:
1136 NumFastIselFailFrameaddress++; return;
1137 case Intrinsic::sqrt:
1138 NumFastIselFailSqrt++; return;
1139 case Intrinsic::experimental_stackmap:
1140 NumFastIselFailStackMap++; return;
1141 case Intrinsic::experimental_patchpoint_void: // fall-through
1142 case Intrinsic::experimental_patchpoint_i64:
1143 NumFastIselFailPatchPoint++; return;
1146 NumFastIselFailCall++;
1149 case Instruction::Shl: NumFastIselFailShl++; return;
1150 case Instruction::LShr: NumFastIselFailLShr++; return;
1151 case Instruction::AShr: NumFastIselFailAShr++; return;
1152 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1153 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1154 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1155 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1156 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1157 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1158 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1163 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1164 // Initialize the Fast-ISel state, if needed.
1165 FastISel *FastIS = nullptr;
1166 if (TM.Options.EnableFastISel)
1167 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1169 // Iterate over all basic blocks in the function.
1170 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1171 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1172 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1173 const BasicBlock *LLVMBB = *I;
1175 if (OptLevel != CodeGenOpt::None) {
1176 bool AllPredsVisited = true;
1177 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1179 if (!FuncInfo->VisitedBBs.count(*PI)) {
1180 AllPredsVisited = false;
1185 if (AllPredsVisited) {
1186 for (BasicBlock::const_iterator I = LLVMBB->begin();
1187 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1188 FuncInfo->ComputePHILiveOutRegInfo(PN);
1190 for (BasicBlock::const_iterator I = LLVMBB->begin();
1191 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1192 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1195 FuncInfo->VisitedBBs.insert(LLVMBB);
1198 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1199 BasicBlock::const_iterator const End = LLVMBB->end();
1200 BasicBlock::const_iterator BI = End;
1202 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1203 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1205 // Setup an EH landing-pad block.
1206 FuncInfo->ExceptionPointerVirtReg = 0;
1207 FuncInfo->ExceptionSelectorVirtReg = 0;
1208 if (LLVMBB->isLandingPad())
1209 if (!PrepareEHLandingPad())
1212 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1214 FastIS->startNewBlock();
1216 // Emit code for any incoming arguments. This must happen before
1217 // beginning FastISel on the entry block.
1218 if (LLVMBB == &Fn.getEntryBlock()) {
1221 // Lower any arguments needed in this block if this is the entry block.
1222 if (!FastIS->lowerArguments()) {
1223 // Fast isel failed to lower these arguments
1224 ++NumFastIselFailLowerArguments;
1225 if (EnableFastISelAbort > 1)
1226 report_fatal_error("FastISel didn't lower all arguments");
1228 // Use SelectionDAG argument lowering
1230 CurDAG->setRoot(SDB->getControlRoot());
1232 CodeGenAndEmitDAG();
1235 // If we inserted any instructions at the beginning, make a note of
1236 // where they are, so we can be sure to emit subsequent instructions
1238 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1239 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1241 FastIS->setLastLocalValue(nullptr);
1244 unsigned NumFastIselRemaining = std::distance(Begin, End);
1245 // Do FastISel on as many instructions as possible.
1246 for (; BI != Begin; --BI) {
1247 const Instruction *Inst = std::prev(BI);
1249 // If we no longer require this instruction, skip it.
1250 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1251 --NumFastIselRemaining;
1255 // Bottom-up: reset the insert pos at the top, after any local-value
1257 FastIS->recomputeInsertPt();
1259 // Try to select the instruction with FastISel.
1260 if (FastIS->selectInstruction(Inst)) {
1261 --NumFastIselRemaining;
1262 ++NumFastIselSuccess;
1263 // If fast isel succeeded, skip over all the folded instructions, and
1264 // then see if there is a load right before the selected instructions.
1265 // Try to fold the load if so.
1266 const Instruction *BeforeInst = Inst;
1267 while (BeforeInst != Begin) {
1268 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1269 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1272 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1273 BeforeInst->hasOneUse() &&
1274 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1275 // If we succeeded, don't re-select the load.
1276 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1277 --NumFastIselRemaining;
1278 ++NumFastIselSuccess;
1284 if (EnableFastISelVerbose2)
1285 collectFailStats(Inst);
1288 // Then handle certain instructions as single-LLVM-Instruction blocks.
1289 if (isa<CallInst>(Inst)) {
1291 if (EnableFastISelVerbose || EnableFastISelAbort) {
1292 dbgs() << "FastISel missed call: ";
1295 if (EnableFastISelAbort > 2)
1296 // FastISel selector couldn't handle something and bailed.
1297 // For the purpose of debugging, just abort.
1298 report_fatal_error("FastISel didn't select the entire block");
1300 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1301 unsigned &R = FuncInfo->ValueMap[Inst];
1303 R = FuncInfo->CreateRegs(Inst->getType());
1306 bool HadTailCall = false;
1307 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1308 SelectBasicBlock(Inst, BI, HadTailCall);
1310 // If the call was emitted as a tail call, we're done with the block.
1311 // We also need to delete any previously emitted instructions.
1313 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1318 // Recompute NumFastIselRemaining as Selection DAG instruction
1319 // selection may have handled the call, input args, etc.
1320 unsigned RemainingNow = std::distance(Begin, BI);
1321 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1322 NumFastIselRemaining = RemainingNow;
1326 bool ShouldAbort = EnableFastISelAbort;
1327 if (EnableFastISelVerbose || EnableFastISelAbort) {
1328 if (isa<TerminatorInst>(Inst)) {
1329 // Use a different message for terminator misses.
1330 dbgs() << "FastISel missed terminator: ";
1331 // Don't abort unless for terminator unless the level is really high
1332 ShouldAbort = (EnableFastISelAbort > 2);
1334 dbgs() << "FastISel miss: ";
1339 // FastISel selector couldn't handle something and bailed.
1340 // For the purpose of debugging, just abort.
1341 report_fatal_error("FastISel didn't select the entire block");
1343 NumFastIselFailures += NumFastIselRemaining;
1347 FastIS->recomputeInsertPt();
1349 // Lower any arguments needed in this block if this is the entry block.
1350 if (LLVMBB == &Fn.getEntryBlock()) {
1359 ++NumFastIselBlocks;
1362 // Run SelectionDAG instruction selection on the remainder of the block
1363 // not handled by FastISel. If FastISel is not run, this is the entire
1366 SelectBasicBlock(Begin, BI, HadTailCall);
1370 FuncInfo->PHINodesToUpdate.clear();
1374 SDB->clearDanglingDebugInfo();
1375 SDB->SPDescriptor.resetPerFunctionState();
1378 /// Given that the input MI is before a partial terminator sequence TSeq, return
1379 /// true if M + TSeq also a partial terminator sequence.
1381 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1382 /// lowering copy vregs into physical registers, which are then passed into
1383 /// terminator instructors so we can satisfy ABI constraints. A partial
1384 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1385 /// may be the whole terminator sequence).
1386 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1387 // If we do not have a copy or an implicit def, we return true if and only if
1388 // MI is a debug value.
1389 if (!MI->isCopy() && !MI->isImplicitDef())
1390 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1391 // physical registers if there is debug info associated with the terminator
1392 // of our mbb. We want to include said debug info in our terminator
1393 // sequence, so we return true in that case.
1394 return MI->isDebugValue();
1396 // We have left the terminator sequence if we are not doing one of the
1399 // 1. Copying a vreg into a physical register.
1400 // 2. Copying a vreg into a vreg.
1401 // 3. Defining a register via an implicit def.
1403 // OPI should always be a register definition...
1404 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1405 if (!OPI->isReg() || !OPI->isDef())
1408 // Defining any register via an implicit def is always ok.
1409 if (MI->isImplicitDef())
1412 // Grab the copy source...
1413 MachineInstr::const_mop_iterator OPI2 = OPI;
1415 assert(OPI2 != MI->operands_end()
1416 && "Should have a copy implying we should have 2 arguments.");
1418 // Make sure that the copy dest is not a vreg when the copy source is a
1419 // physical register.
1420 if (!OPI2->isReg() ||
1421 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1422 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1428 /// Find the split point at which to splice the end of BB into its success stack
1429 /// protector check machine basic block.
1431 /// On many platforms, due to ABI constraints, terminators, even before register
1432 /// allocation, use physical registers. This creates an issue for us since
1433 /// physical registers at this point can not travel across basic
1434 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1435 /// when they enter functions and moves them through a sequence of copies back
1436 /// into the physical registers right before the terminator creating a
1437 /// ``Terminator Sequence''. This function is searching for the beginning of the
1438 /// terminator sequence so that we can ensure that we splice off not just the
1439 /// terminator, but additionally the copies that move the vregs into the
1440 /// physical registers.
1441 static MachineBasicBlock::iterator
1442 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1443 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1445 if (SplitPoint == BB->begin())
1448 MachineBasicBlock::iterator Start = BB->begin();
1449 MachineBasicBlock::iterator Previous = SplitPoint;
1452 while (MIIsInTerminatorSequence(Previous)) {
1453 SplitPoint = Previous;
1454 if (Previous == Start)
1463 SelectionDAGISel::FinishBasicBlock() {
1465 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1466 << FuncInfo->PHINodesToUpdate.size() << "\n";
1467 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1468 dbgs() << "Node " << i << " : ("
1469 << FuncInfo->PHINodesToUpdate[i].first
1470 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1472 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1473 // PHI nodes in successors.
1474 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1475 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1476 assert(PHI->isPHI() &&
1477 "This is not a machine PHI node that we are updating!");
1478 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1480 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1483 // Handle stack protector.
1484 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1485 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1486 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1488 // Find the split point to split the parent mbb. At the same time copy all
1489 // physical registers used in the tail of parent mbb into virtual registers
1490 // before the split point and back into physical registers after the split
1491 // point. This prevents us needing to deal with Live-ins and many other
1492 // register allocation issues caused by us splitting the parent mbb. The
1493 // register allocator will clean up said virtual copies later on.
1494 MachineBasicBlock::iterator SplitPoint =
1495 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1497 // Splice the terminator of ParentMBB into SuccessMBB.
1498 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1502 // Add compare/jump on neq/jump to the parent BB.
1503 FuncInfo->MBB = ParentMBB;
1504 FuncInfo->InsertPt = ParentMBB->end();
1505 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1506 CurDAG->setRoot(SDB->getRoot());
1508 CodeGenAndEmitDAG();
1510 // CodeGen Failure MBB if we have not codegened it yet.
1511 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1512 if (!FailureMBB->size()) {
1513 FuncInfo->MBB = FailureMBB;
1514 FuncInfo->InsertPt = FailureMBB->end();
1515 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1516 CurDAG->setRoot(SDB->getRoot());
1518 CodeGenAndEmitDAG();
1521 // Clear the Per-BB State.
1522 SDB->SPDescriptor.resetPerBBState();
1525 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1526 // Lower header first, if it wasn't already lowered
1527 if (!SDB->BitTestCases[i].Emitted) {
1528 // Set the current basic block to the mbb we wish to insert the code into
1529 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1530 FuncInfo->InsertPt = FuncInfo->MBB->end();
1532 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1533 CurDAG->setRoot(SDB->getRoot());
1535 CodeGenAndEmitDAG();
1538 uint32_t UnhandledWeight = 0;
1539 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1540 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1542 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1543 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1544 // Set the current basic block to the mbb we wish to insert the code into
1545 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1546 FuncInfo->InsertPt = FuncInfo->MBB->end();
1549 SDB->visitBitTestCase(SDB->BitTestCases[i],
1550 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1552 SDB->BitTestCases[i].Reg,
1553 SDB->BitTestCases[i].Cases[j],
1556 SDB->visitBitTestCase(SDB->BitTestCases[i],
1557 SDB->BitTestCases[i].Default,
1559 SDB->BitTestCases[i].Reg,
1560 SDB->BitTestCases[i].Cases[j],
1564 CurDAG->setRoot(SDB->getRoot());
1566 CodeGenAndEmitDAG();
1570 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1572 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1573 MachineBasicBlock *PHIBB = PHI->getParent();
1574 assert(PHI->isPHI() &&
1575 "This is not a machine PHI node that we are updating!");
1576 // This is "default" BB. We have two jumps to it. From "header" BB and
1577 // from last "case" BB.
1578 if (PHIBB == SDB->BitTestCases[i].Default)
1579 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1580 .addMBB(SDB->BitTestCases[i].Parent)
1581 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1582 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1583 // One of "cases" BB.
1584 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1586 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1587 if (cBB->isSuccessor(PHIBB))
1588 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1592 SDB->BitTestCases.clear();
1594 // If the JumpTable record is filled in, then we need to emit a jump table.
1595 // Updating the PHI nodes is tricky in this case, since we need to determine
1596 // whether the PHI is a successor of the range check MBB or the jump table MBB
1597 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1598 // Lower header first, if it wasn't already lowered
1599 if (!SDB->JTCases[i].first.Emitted) {
1600 // Set the current basic block to the mbb we wish to insert the code into
1601 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1602 FuncInfo->InsertPt = FuncInfo->MBB->end();
1604 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1606 CurDAG->setRoot(SDB->getRoot());
1608 CodeGenAndEmitDAG();
1611 // Set the current basic block to the mbb we wish to insert the code into
1612 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1613 FuncInfo->InsertPt = FuncInfo->MBB->end();
1615 SDB->visitJumpTable(SDB->JTCases[i].second);
1616 CurDAG->setRoot(SDB->getRoot());
1618 CodeGenAndEmitDAG();
1621 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1623 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1624 MachineBasicBlock *PHIBB = PHI->getParent();
1625 assert(PHI->isPHI() &&
1626 "This is not a machine PHI node that we are updating!");
1627 // "default" BB. We can go there only from header BB.
1628 if (PHIBB == SDB->JTCases[i].second.Default)
1629 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1630 .addMBB(SDB->JTCases[i].first.HeaderBB);
1631 // JT BB. Just iterate over successors here
1632 if (FuncInfo->MBB->isSuccessor(PHIBB))
1633 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1636 SDB->JTCases.clear();
1638 // If we generated any switch lowering information, build and codegen any
1639 // additional DAGs necessary.
1640 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1641 // Set the current basic block to the mbb we wish to insert the code into
1642 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1643 FuncInfo->InsertPt = FuncInfo->MBB->end();
1645 // Determine the unique successors.
1646 SmallVector<MachineBasicBlock *, 2> Succs;
1647 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1648 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1649 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1651 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1652 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1653 CurDAG->setRoot(SDB->getRoot());
1655 CodeGenAndEmitDAG();
1657 // Remember the last block, now that any splitting is done, for use in
1658 // populating PHI nodes in successors.
1659 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1661 // Handle any PHI nodes in successors of this chunk, as if we were coming
1662 // from the original BB before switch expansion. Note that PHI nodes can
1663 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1664 // handle them the right number of times.
1665 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1666 FuncInfo->MBB = Succs[i];
1667 FuncInfo->InsertPt = FuncInfo->MBB->end();
1668 // FuncInfo->MBB may have been removed from the CFG if a branch was
1670 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1671 for (MachineBasicBlock::iterator
1672 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1673 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1674 MachineInstrBuilder PHI(*MF, MBBI);
1675 // This value for this PHI node is recorded in PHINodesToUpdate.
1676 for (unsigned pn = 0; ; ++pn) {
1677 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1678 "Didn't find PHI entry!");
1679 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1680 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1688 SDB->SwitchCases.clear();
1692 /// Create the scheduler. If a specific scheduler was specified
1693 /// via the SchedulerRegistry, use it, otherwise select the
1694 /// one preferred by the target.
1696 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1697 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1701 RegisterScheduler::setDefault(Ctor);
1704 return Ctor(this, OptLevel);
1707 //===----------------------------------------------------------------------===//
1708 // Helper functions used by the generated instruction selector.
1709 //===----------------------------------------------------------------------===//
1710 // Calls to these methods are generated by tblgen.
1712 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1713 /// the dag combiner simplified the 255, we still want to match. RHS is the
1714 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1715 /// specified in the .td file (e.g. 255).
1716 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1717 int64_t DesiredMaskS) const {
1718 const APInt &ActualMask = RHS->getAPIntValue();
1719 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1721 // If the actual mask exactly matches, success!
1722 if (ActualMask == DesiredMask)
1725 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1726 if (ActualMask.intersects(~DesiredMask))
1729 // Otherwise, the DAG Combiner may have proven that the value coming in is
1730 // either already zero or is not demanded. Check for known zero input bits.
1731 APInt NeededMask = DesiredMask & ~ActualMask;
1732 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1735 // TODO: check to see if missing bits are just not demanded.
1737 // Otherwise, this pattern doesn't match.
1741 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1742 /// the dag combiner simplified the 255, we still want to match. RHS is the
1743 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1744 /// specified in the .td file (e.g. 255).
1745 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1746 int64_t DesiredMaskS) const {
1747 const APInt &ActualMask = RHS->getAPIntValue();
1748 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1750 // If the actual mask exactly matches, success!
1751 if (ActualMask == DesiredMask)
1754 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1755 if (ActualMask.intersects(~DesiredMask))
1758 // Otherwise, the DAG Combiner may have proven that the value coming in is
1759 // either already zero or is not demanded. Check for known zero input bits.
1760 APInt NeededMask = DesiredMask & ~ActualMask;
1762 APInt KnownZero, KnownOne;
1763 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1765 // If all the missing bits in the or are already known to be set, match!
1766 if ((NeededMask & KnownOne) == NeededMask)
1769 // TODO: check to see if missing bits are just not demanded.
1771 // Otherwise, this pattern doesn't match.
1776 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1777 /// by tblgen. Others should not call it.
1778 void SelectionDAGISel::
1779 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1780 std::vector<SDValue> InOps;
1781 std::swap(InOps, Ops);
1783 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1784 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1785 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1786 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1788 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1789 if (InOps[e-1].getValueType() == MVT::Glue)
1790 --e; // Don't process a glue operand if it is here.
1793 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1794 if (!InlineAsm::isMemKind(Flags)) {
1795 // Just skip over this operand, copying the operands verbatim.
1796 Ops.insert(Ops.end(), InOps.begin()+i,
1797 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1798 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1800 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1801 "Memory operand with multiple values?");
1803 unsigned TiedToOperand;
1804 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1805 // We need the constraint ID from the operand this is tied to.
1806 unsigned CurOp = InlineAsm::Op_FirstOperand;
1807 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1808 for (; TiedToOperand; --TiedToOperand) {
1809 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1810 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1814 // Otherwise, this is a memory operand. Ask the target to select it.
1815 std::vector<SDValue> SelOps;
1816 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1817 InlineAsm::getMemoryConstraintID(Flags),
1819 report_fatal_error("Could not match memory address. Inline asm"
1822 // Add this to the output node.
1824 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1825 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1826 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1831 // Add the glue input back if present.
1832 if (e != InOps.size())
1833 Ops.push_back(InOps.back());
1836 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1839 static SDNode *findGlueUse(SDNode *N) {
1840 unsigned FlagResNo = N->getNumValues()-1;
1841 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1842 SDUse &Use = I.getUse();
1843 if (Use.getResNo() == FlagResNo)
1844 return Use.getUser();
1849 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1850 /// This function recursively traverses up the operand chain, ignoring
1852 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1853 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1854 bool IgnoreChains) {
1855 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1856 // greater than all of its (recursive) operands. If we scan to a point where
1857 // 'use' is smaller than the node we're scanning for, then we know we will
1860 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1861 // happen because we scan down to newly selected nodes in the case of glue
1863 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1866 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1867 // won't fail if we scan it again.
1868 if (!Visited.insert(Use).second)
1871 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1872 // Ignore chain uses, they are validated by HandleMergeInputChains.
1873 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1876 SDNode *N = Use->getOperand(i).getNode();
1878 if (Use == ImmedUse || Use == Root)
1879 continue; // We are not looking for immediate use.
1884 // Traverse up the operand chain.
1885 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1891 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1892 /// operand node N of U during instruction selection that starts at Root.
1893 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1894 SDNode *Root) const {
1895 if (OptLevel == CodeGenOpt::None) return false;
1896 return N.hasOneUse();
1899 /// IsLegalToFold - Returns true if the specific operand node N of
1900 /// U can be folded during instruction selection that starts at Root.
1901 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1902 CodeGenOpt::Level OptLevel,
1903 bool IgnoreChains) {
1904 if (OptLevel == CodeGenOpt::None) return false;
1906 // If Root use can somehow reach N through a path that that doesn't contain
1907 // U then folding N would create a cycle. e.g. In the following
1908 // diagram, Root can reach N through X. If N is folded into into Root, then
1909 // X is both a predecessor and a successor of U.
1920 // * indicates nodes to be folded together.
1922 // If Root produces glue, then it gets (even more) interesting. Since it
1923 // will be "glued" together with its glue use in the scheduler, we need to
1924 // check if it might reach N.
1943 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1944 // (call it Fold), then X is a predecessor of GU and a successor of
1945 // Fold. But since Fold and GU are glued together, this will create
1946 // a cycle in the scheduling graph.
1948 // If the node has glue, walk down the graph to the "lowest" node in the
1950 EVT VT = Root->getValueType(Root->getNumValues()-1);
1951 while (VT == MVT::Glue) {
1952 SDNode *GU = findGlueUse(Root);
1956 VT = Root->getValueType(Root->getNumValues()-1);
1958 // If our query node has a glue result with a use, we've walked up it. If
1959 // the user (which has already been selected) has a chain or indirectly uses
1960 // the chain, our WalkChainUsers predicate will not consider it. Because of
1961 // this, we cannot ignore chains in this predicate.
1962 IgnoreChains = false;
1966 SmallPtrSet<SDNode*, 16> Visited;
1967 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1970 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1971 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1972 SelectInlineAsmMemoryOperands(Ops);
1974 const EVT VTs[] = {MVT::Other, MVT::Glue};
1975 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1977 return New.getNode();
1981 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1983 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1984 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1986 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1987 SDValue New = CurDAG->getCopyFromReg(
1988 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1990 return New.getNode();
1994 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1996 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1997 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1998 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1999 Op->getOperand(2).getValueType());
2000 SDValue New = CurDAG->getCopyToReg(
2001 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
2003 return New.getNode();
2008 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
2009 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
2012 /// GetVBR - decode a vbr encoding whose top bit is set.
2013 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
2014 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2015 assert(Val >= 128 && "Not a VBR");
2016 Val &= 127; // Remove first vbr bit.
2021 NextBits = MatcherTable[Idx++];
2022 Val |= (NextBits&127) << Shift;
2024 } while (NextBits & 128);
2030 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2031 /// interior glue and chain results to use the new glue and chain results.
2032 void SelectionDAGISel::
2033 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2034 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2036 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2037 bool isMorphNodeTo) {
2038 SmallVector<SDNode*, 4> NowDeadNodes;
2040 // Now that all the normal results are replaced, we replace the chain and
2041 // glue results if present.
2042 if (!ChainNodesMatched.empty()) {
2043 assert(InputChain.getNode() &&
2044 "Matched input chains but didn't produce a chain");
2045 // Loop over all of the nodes we matched that produced a chain result.
2046 // Replace all the chain results with the final chain we ended up with.
2047 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2048 SDNode *ChainNode = ChainNodesMatched[i];
2050 // If this node was already deleted, don't look at it.
2051 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2054 // Don't replace the results of the root node if we're doing a
2056 if (ChainNode == NodeToMatch && isMorphNodeTo)
2059 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2060 if (ChainVal.getValueType() == MVT::Glue)
2061 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2062 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2063 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2065 // If the node became dead and we haven't already seen it, delete it.
2066 if (ChainNode->use_empty() &&
2067 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2068 NowDeadNodes.push_back(ChainNode);
2072 // If the result produces glue, update any glue results in the matched
2073 // pattern with the glue result.
2074 if (InputGlue.getNode()) {
2075 // Handle any interior nodes explicitly marked.
2076 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2077 SDNode *FRN = GlueResultNodesMatched[i];
2079 // If this node was already deleted, don't look at it.
2080 if (FRN->getOpcode() == ISD::DELETED_NODE)
2083 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2084 "Doesn't have a glue result");
2085 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2088 // If the node became dead and we haven't already seen it, delete it.
2089 if (FRN->use_empty() &&
2090 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2091 NowDeadNodes.push_back(FRN);
2095 if (!NowDeadNodes.empty())
2096 CurDAG->RemoveDeadNodes(NowDeadNodes);
2098 DEBUG(dbgs() << "ISEL: Match complete!\n");
2104 CR_LeadsToInteriorNode
2107 /// WalkChainUsers - Walk down the users of the specified chained node that is
2108 /// part of the pattern we're matching, looking at all of the users we find.
2109 /// This determines whether something is an interior node, whether we have a
2110 /// non-pattern node in between two pattern nodes (which prevent folding because
2111 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2112 /// between pattern nodes (in which case the TF becomes part of the pattern).
2114 /// The walk we do here is guaranteed to be small because we quickly get down to
2115 /// already selected nodes "below" us.
2117 WalkChainUsers(const SDNode *ChainedNode,
2118 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2119 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2120 ChainResult Result = CR_Simple;
2122 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2123 E = ChainedNode->use_end(); UI != E; ++UI) {
2124 // Make sure the use is of the chain, not some other value we produce.
2125 if (UI.getUse().getValueType() != MVT::Other) continue;
2129 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2132 // If we see an already-selected machine node, then we've gone beyond the
2133 // pattern that we're selecting down into the already selected chunk of the
2135 unsigned UserOpcode = User->getOpcode();
2136 if (User->isMachineOpcode() ||
2137 UserOpcode == ISD::CopyToReg ||
2138 UserOpcode == ISD::CopyFromReg ||
2139 UserOpcode == ISD::INLINEASM ||
2140 UserOpcode == ISD::EH_LABEL ||
2141 UserOpcode == ISD::LIFETIME_START ||
2142 UserOpcode == ISD::LIFETIME_END) {
2143 // If their node ID got reset to -1 then they've already been selected.
2144 // Treat them like a MachineOpcode.
2145 if (User->getNodeId() == -1)
2149 // If we have a TokenFactor, we handle it specially.
2150 if (User->getOpcode() != ISD::TokenFactor) {
2151 // If the node isn't a token factor and isn't part of our pattern, then it
2152 // must be a random chained node in between two nodes we're selecting.
2153 // This happens when we have something like:
2158 // Because we structurally match the load/store as a read/modify/write,
2159 // but the call is chained between them. We cannot fold in this case
2160 // because it would induce a cycle in the graph.
2161 if (!std::count(ChainedNodesInPattern.begin(),
2162 ChainedNodesInPattern.end(), User))
2163 return CR_InducesCycle;
2165 // Otherwise we found a node that is part of our pattern. For example in:
2169 // This would happen when we're scanning down from the load and see the
2170 // store as a user. Record that there is a use of ChainedNode that is
2171 // part of the pattern and keep scanning uses.
2172 Result = CR_LeadsToInteriorNode;
2173 InteriorChainedNodes.push_back(User);
2177 // If we found a TokenFactor, there are two cases to consider: first if the
2178 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2179 // uses of the TF are in our pattern) we just want to ignore it. Second,
2180 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2186 // | \ DAG's like cheese
2189 // [TokenFactor] [Op]
2196 // In this case, the TokenFactor becomes part of our match and we rewrite it
2197 // as a new TokenFactor.
2199 // To distinguish these two cases, do a recursive walk down the uses.
2200 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2202 // If the uses of the TokenFactor are just already-selected nodes, ignore
2203 // it, it is "below" our pattern.
2205 case CR_InducesCycle:
2206 // If the uses of the TokenFactor lead to nodes that are not part of our
2207 // pattern that are not selected, folding would turn this into a cycle,
2209 return CR_InducesCycle;
2210 case CR_LeadsToInteriorNode:
2211 break; // Otherwise, keep processing.
2214 // Okay, we know we're in the interesting interior case. The TokenFactor
2215 // is now going to be considered part of the pattern so that we rewrite its
2216 // uses (it may have uses that are not part of the pattern) with the
2217 // ultimate chain result of the generated code. We will also add its chain
2218 // inputs as inputs to the ultimate TokenFactor we create.
2219 Result = CR_LeadsToInteriorNode;
2220 ChainedNodesInPattern.push_back(User);
2221 InteriorChainedNodes.push_back(User);
2228 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2229 /// operation for when the pattern matched at least one node with a chains. The
2230 /// input vector contains a list of all of the chained nodes that we match. We
2231 /// must determine if this is a valid thing to cover (i.e. matching it won't
2232 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2233 /// be used as the input node chain for the generated nodes.
2235 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2236 SelectionDAG *CurDAG) {
2237 // Walk all of the chained nodes we've matched, recursively scanning down the
2238 // users of the chain result. This adds any TokenFactor nodes that are caught
2239 // in between chained nodes to the chained and interior nodes list.
2240 SmallVector<SDNode*, 3> InteriorChainedNodes;
2241 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2242 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2243 InteriorChainedNodes) == CR_InducesCycle)
2244 return SDValue(); // Would induce a cycle.
2247 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2248 // that we are interested in. Form our input TokenFactor node.
2249 SmallVector<SDValue, 3> InputChains;
2250 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2251 // Add the input chain of this node to the InputChains list (which will be
2252 // the operands of the generated TokenFactor) if it's not an interior node.
2253 SDNode *N = ChainNodesMatched[i];
2254 if (N->getOpcode() != ISD::TokenFactor) {
2255 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2258 // Otherwise, add the input chain.
2259 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2260 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2261 InputChains.push_back(InChain);
2265 // If we have a token factor, we want to add all inputs of the token factor
2266 // that are not part of the pattern we're matching.
2267 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2268 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2269 N->getOperand(op).getNode()))
2270 InputChains.push_back(N->getOperand(op));
2274 if (InputChains.size() == 1)
2275 return InputChains[0];
2276 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2277 MVT::Other, InputChains);
2280 /// MorphNode - Handle morphing a node in place for the selector.
2281 SDNode *SelectionDAGISel::
2282 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2283 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2284 // It is possible we're using MorphNodeTo to replace a node with no
2285 // normal results with one that has a normal result (or we could be
2286 // adding a chain) and the input could have glue and chains as well.
2287 // In this case we need to shift the operands down.
2288 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2289 // than the old isel though.
2290 int OldGlueResultNo = -1, OldChainResultNo = -1;
2292 unsigned NTMNumResults = Node->getNumValues();
2293 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2294 OldGlueResultNo = NTMNumResults-1;
2295 if (NTMNumResults != 1 &&
2296 Node->getValueType(NTMNumResults-2) == MVT::Other)
2297 OldChainResultNo = NTMNumResults-2;
2298 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2299 OldChainResultNo = NTMNumResults-1;
2301 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2302 // that this deletes operands of the old node that become dead.
2303 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2305 // MorphNodeTo can operate in two ways: if an existing node with the
2306 // specified operands exists, it can just return it. Otherwise, it
2307 // updates the node in place to have the requested operands.
2309 // If we updated the node in place, reset the node ID. To the isel,
2310 // this should be just like a newly allocated machine node.
2314 unsigned ResNumResults = Res->getNumValues();
2315 // Move the glue if needed.
2316 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2317 (unsigned)OldGlueResultNo != ResNumResults-1)
2318 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2319 SDValue(Res, ResNumResults-1));
2321 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2324 // Move the chain reference if needed.
2325 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2326 (unsigned)OldChainResultNo != ResNumResults-1)
2327 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2328 SDValue(Res, ResNumResults-1));
2330 // Otherwise, no replacement happened because the node already exists. Replace
2331 // Uses of the old node with the new one.
2333 CurDAG->ReplaceAllUsesWith(Node, Res);
2338 /// CheckSame - Implements OP_CheckSame.
2339 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2340 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2342 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2343 // Accept if it is exactly the same as a previously recorded node.
2344 unsigned RecNo = MatcherTable[MatcherIndex++];
2345 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2346 return N == RecordedNodes[RecNo].first;
2349 /// CheckChildSame - Implements OP_CheckChildXSame.
2350 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2351 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2353 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2355 if (ChildNo >= N.getNumOperands())
2356 return false; // Match fails if out of range child #.
2357 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2361 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2362 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2363 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2364 const SelectionDAGISel &SDISel) {
2365 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2368 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2369 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2370 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2371 const SelectionDAGISel &SDISel, SDNode *N) {
2372 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2375 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2376 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2378 uint16_t Opc = MatcherTable[MatcherIndex++];
2379 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2380 return N->getOpcode() == Opc;
2383 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2384 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2385 SDValue N, const TargetLowering *TLI) {
2386 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2387 if (N.getValueType() == VT) return true;
2389 // Handle the case when VT is iPTR.
2390 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2393 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2394 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2395 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2396 if (ChildNo >= N.getNumOperands())
2397 return false; // Match fails if out of range child #.
2398 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2401 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2402 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2404 return cast<CondCodeSDNode>(N)->get() ==
2405 (ISD::CondCode)MatcherTable[MatcherIndex++];
2408 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2409 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2410 SDValue N, const TargetLowering *TLI) {
2411 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2412 if (cast<VTSDNode>(N)->getVT() == VT)
2415 // Handle the case when VT is iPTR.
2416 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2419 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2420 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2422 int64_t Val = MatcherTable[MatcherIndex++];
2424 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2427 return C && C->getSExtValue() == Val;
2430 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2431 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2432 SDValue N, unsigned ChildNo) {
2433 if (ChildNo >= N.getNumOperands())
2434 return false; // Match fails if out of range child #.
2435 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2438 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2439 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2440 SDValue N, const SelectionDAGISel &SDISel) {
2441 int64_t Val = MatcherTable[MatcherIndex++];
2443 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2445 if (N->getOpcode() != ISD::AND) return false;
2447 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2448 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2451 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2452 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2453 SDValue N, const SelectionDAGISel &SDISel) {
2454 int64_t Val = MatcherTable[MatcherIndex++];
2456 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2458 if (N->getOpcode() != ISD::OR) return false;
2460 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2461 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2464 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2465 /// scope, evaluate the current node. If the current predicate is known to
2466 /// fail, set Result=true and return anything. If the current predicate is
2467 /// known to pass, set Result=false and return the MatcherIndex to continue
2468 /// with. If the current predicate is unknown, set Result=false and return the
2469 /// MatcherIndex to continue with.
2470 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2471 unsigned Index, SDValue N,
2473 const SelectionDAGISel &SDISel,
2474 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2475 switch (Table[Index++]) {
2478 return Index-1; // Could not evaluate this predicate.
2479 case SelectionDAGISel::OPC_CheckSame:
2480 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2482 case SelectionDAGISel::OPC_CheckChild0Same:
2483 case SelectionDAGISel::OPC_CheckChild1Same:
2484 case SelectionDAGISel::OPC_CheckChild2Same:
2485 case SelectionDAGISel::OPC_CheckChild3Same:
2486 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2487 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2489 case SelectionDAGISel::OPC_CheckPatternPredicate:
2490 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2492 case SelectionDAGISel::OPC_CheckPredicate:
2493 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2495 case SelectionDAGISel::OPC_CheckOpcode:
2496 Result = !::CheckOpcode(Table, Index, N.getNode());
2498 case SelectionDAGISel::OPC_CheckType:
2499 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2501 case SelectionDAGISel::OPC_CheckChild0Type:
2502 case SelectionDAGISel::OPC_CheckChild1Type:
2503 case SelectionDAGISel::OPC_CheckChild2Type:
2504 case SelectionDAGISel::OPC_CheckChild3Type:
2505 case SelectionDAGISel::OPC_CheckChild4Type:
2506 case SelectionDAGISel::OPC_CheckChild5Type:
2507 case SelectionDAGISel::OPC_CheckChild6Type:
2508 case SelectionDAGISel::OPC_CheckChild7Type:
2509 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2511 SelectionDAGISel::OPC_CheckChild0Type);
2513 case SelectionDAGISel::OPC_CheckCondCode:
2514 Result = !::CheckCondCode(Table, Index, N);
2516 case SelectionDAGISel::OPC_CheckValueType:
2517 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2519 case SelectionDAGISel::OPC_CheckInteger:
2520 Result = !::CheckInteger(Table, Index, N);
2522 case SelectionDAGISel::OPC_CheckChild0Integer:
2523 case SelectionDAGISel::OPC_CheckChild1Integer:
2524 case SelectionDAGISel::OPC_CheckChild2Integer:
2525 case SelectionDAGISel::OPC_CheckChild3Integer:
2526 case SelectionDAGISel::OPC_CheckChild4Integer:
2527 Result = !::CheckChildInteger(Table, Index, N,
2528 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2530 case SelectionDAGISel::OPC_CheckAndImm:
2531 Result = !::CheckAndImm(Table, Index, N, SDISel);
2533 case SelectionDAGISel::OPC_CheckOrImm:
2534 Result = !::CheckOrImm(Table, Index, N, SDISel);
2542 /// FailIndex - If this match fails, this is the index to continue with.
2545 /// NodeStack - The node stack when the scope was formed.
2546 SmallVector<SDValue, 4> NodeStack;
2548 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2549 unsigned NumRecordedNodes;
2551 /// NumMatchedMemRefs - The number of matched memref entries.
2552 unsigned NumMatchedMemRefs;
2554 /// InputChain/InputGlue - The current chain/glue
2555 SDValue InputChain, InputGlue;
2557 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2558 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2561 /// \\brief A DAG update listener to keep the matching state
2562 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2563 /// change the DAG while matching. X86 addressing mode matcher is an example
2565 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2567 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2568 SmallVectorImpl<MatchScope> &MatchScopes;
2570 MatchStateUpdater(SelectionDAG &DAG,
2571 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2572 SmallVectorImpl<MatchScope> &MS) :
2573 SelectionDAG::DAGUpdateListener(DAG),
2574 RecordedNodes(RN), MatchScopes(MS) { }
2576 void NodeDeleted(SDNode *N, SDNode *E) override {
2577 // Some early-returns here to avoid the search if we deleted the node or
2578 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2579 // do, so it's unnecessary to update matching state at that point).
2580 // Neither of these can occur currently because we only install this
2581 // update listener during matching a complex patterns.
2582 if (!E || E->isMachineOpcode())
2584 // Performing linear search here does not matter because we almost never
2585 // run this code. You'd have to have a CSE during complex pattern
2587 for (auto &I : RecordedNodes)
2588 if (I.first.getNode() == N)
2591 for (auto &I : MatchScopes)
2592 for (auto &J : I.NodeStack)
2593 if (J.getNode() == N)
2599 SDNode *SelectionDAGISel::
2600 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2601 unsigned TableSize) {
2602 // FIXME: Should these even be selected? Handle these cases in the caller?
2603 switch (NodeToMatch->getOpcode()) {
2606 case ISD::EntryToken: // These nodes remain the same.
2607 case ISD::BasicBlock:
2609 case ISD::RegisterMask:
2610 case ISD::HANDLENODE:
2611 case ISD::MDNODE_SDNODE:
2612 case ISD::TargetConstant:
2613 case ISD::TargetConstantFP:
2614 case ISD::TargetConstantPool:
2615 case ISD::TargetFrameIndex:
2616 case ISD::TargetExternalSymbol:
2617 case ISD::TargetBlockAddress:
2618 case ISD::TargetJumpTable:
2619 case ISD::TargetGlobalTLSAddress:
2620 case ISD::TargetGlobalAddress:
2621 case ISD::TokenFactor:
2622 case ISD::CopyFromReg:
2623 case ISD::CopyToReg:
2625 case ISD::LIFETIME_START:
2626 case ISD::LIFETIME_END:
2627 NodeToMatch->setNodeId(-1); // Mark selected.
2629 case ISD::AssertSext:
2630 case ISD::AssertZext:
2631 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2632 NodeToMatch->getOperand(0));
2634 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2635 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2636 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2637 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2640 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2642 // Set up the node stack with NodeToMatch as the only node on the stack.
2643 SmallVector<SDValue, 8> NodeStack;
2644 SDValue N = SDValue(NodeToMatch, 0);
2645 NodeStack.push_back(N);
2647 // MatchScopes - Scopes used when matching, if a match failure happens, this
2648 // indicates where to continue checking.
2649 SmallVector<MatchScope, 8> MatchScopes;
2651 // RecordedNodes - This is the set of nodes that have been recorded by the
2652 // state machine. The second value is the parent of the node, or null if the
2653 // root is recorded.
2654 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2656 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2658 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2660 // These are the current input chain and glue for use when generating nodes.
2661 // Various Emit operations change these. For example, emitting a copytoreg
2662 // uses and updates these.
2663 SDValue InputChain, InputGlue;
2665 // ChainNodesMatched - If a pattern matches nodes that have input/output
2666 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2667 // which ones they are. The result is captured into this list so that we can
2668 // update the chain results when the pattern is complete.
2669 SmallVector<SDNode*, 3> ChainNodesMatched;
2670 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2672 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2673 NodeToMatch->dump(CurDAG);
2676 // Determine where to start the interpreter. Normally we start at opcode #0,
2677 // but if the state machine starts with an OPC_SwitchOpcode, then we
2678 // accelerate the first lookup (which is guaranteed to be hot) with the
2679 // OpcodeOffset table.
2680 unsigned MatcherIndex = 0;
2682 if (!OpcodeOffset.empty()) {
2683 // Already computed the OpcodeOffset table, just index into it.
2684 if (N.getOpcode() < OpcodeOffset.size())
2685 MatcherIndex = OpcodeOffset[N.getOpcode()];
2686 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2688 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2689 // Otherwise, the table isn't computed, but the state machine does start
2690 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2691 // is the first time we're selecting an instruction.
2694 // Get the size of this case.
2695 unsigned CaseSize = MatcherTable[Idx++];
2697 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2698 if (CaseSize == 0) break;
2700 // Get the opcode, add the index to the table.
2701 uint16_t Opc = MatcherTable[Idx++];
2702 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2703 if (Opc >= OpcodeOffset.size())
2704 OpcodeOffset.resize((Opc+1)*2);
2705 OpcodeOffset[Opc] = Idx;
2709 // Okay, do the lookup for the first opcode.
2710 if (N.getOpcode() < OpcodeOffset.size())
2711 MatcherIndex = OpcodeOffset[N.getOpcode()];
2715 assert(MatcherIndex < TableSize && "Invalid index");
2717 unsigned CurrentOpcodeIndex = MatcherIndex;
2719 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2722 // Okay, the semantics of this operation are that we should push a scope
2723 // then evaluate the first child. However, pushing a scope only to have
2724 // the first check fail (which then pops it) is inefficient. If we can
2725 // determine immediately that the first check (or first several) will
2726 // immediately fail, don't even bother pushing a scope for them.
2730 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2731 if (NumToSkip & 128)
2732 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2733 // Found the end of the scope with no match.
2734 if (NumToSkip == 0) {
2739 FailIndex = MatcherIndex+NumToSkip;
2741 unsigned MatcherIndexOfPredicate = MatcherIndex;
2742 (void)MatcherIndexOfPredicate; // silence warning.
2744 // If we can't evaluate this predicate without pushing a scope (e.g. if
2745 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2746 // push the scope and evaluate the full predicate chain.
2748 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2749 Result, *this, RecordedNodes);
2753 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2754 << "index " << MatcherIndexOfPredicate
2755 << ", continuing at " << FailIndex << "\n");
2756 ++NumDAGIselRetries;
2758 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2759 // move to the next case.
2760 MatcherIndex = FailIndex;
2763 // If the whole scope failed to match, bail.
2764 if (FailIndex == 0) break;
2766 // Push a MatchScope which indicates where to go if the first child fails
2768 MatchScope NewEntry;
2769 NewEntry.FailIndex = FailIndex;
2770 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2771 NewEntry.NumRecordedNodes = RecordedNodes.size();
2772 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2773 NewEntry.InputChain = InputChain;
2774 NewEntry.InputGlue = InputGlue;
2775 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2776 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2777 MatchScopes.push_back(NewEntry);
2780 case OPC_RecordNode: {
2781 // Remember this node, it may end up being an operand in the pattern.
2782 SDNode *Parent = nullptr;
2783 if (NodeStack.size() > 1)
2784 Parent = NodeStack[NodeStack.size()-2].getNode();
2785 RecordedNodes.push_back(std::make_pair(N, Parent));
2789 case OPC_RecordChild0: case OPC_RecordChild1:
2790 case OPC_RecordChild2: case OPC_RecordChild3:
2791 case OPC_RecordChild4: case OPC_RecordChild5:
2792 case OPC_RecordChild6: case OPC_RecordChild7: {
2793 unsigned ChildNo = Opcode-OPC_RecordChild0;
2794 if (ChildNo >= N.getNumOperands())
2795 break; // Match fails if out of range child #.
2797 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2801 case OPC_RecordMemRef:
2802 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2805 case OPC_CaptureGlueInput:
2806 // If the current node has an input glue, capture it in InputGlue.
2807 if (N->getNumOperands() != 0 &&
2808 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2809 InputGlue = N->getOperand(N->getNumOperands()-1);
2812 case OPC_MoveChild: {
2813 unsigned ChildNo = MatcherTable[MatcherIndex++];
2814 if (ChildNo >= N.getNumOperands())
2815 break; // Match fails if out of range child #.
2816 N = N.getOperand(ChildNo);
2817 NodeStack.push_back(N);
2821 case OPC_MoveParent:
2822 // Pop the current node off the NodeStack.
2823 NodeStack.pop_back();
2824 assert(!NodeStack.empty() && "Node stack imbalance!");
2825 N = NodeStack.back();
2829 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2832 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2833 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2834 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2835 Opcode-OPC_CheckChild0Same))
2839 case OPC_CheckPatternPredicate:
2840 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2842 case OPC_CheckPredicate:
2843 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2847 case OPC_CheckComplexPat: {
2848 unsigned CPNum = MatcherTable[MatcherIndex++];
2849 unsigned RecNo = MatcherTable[MatcherIndex++];
2850 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2852 // If target can modify DAG during matching, keep the matching state
2854 std::unique_ptr<MatchStateUpdater> MSU;
2855 if (ComplexPatternFuncMutatesDAG())
2856 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2859 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2860 RecordedNodes[RecNo].first, CPNum,
2865 case OPC_CheckOpcode:
2866 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2870 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2874 case OPC_SwitchOpcode: {
2875 unsigned CurNodeOpcode = N.getOpcode();
2876 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2879 // Get the size of this case.
2880 CaseSize = MatcherTable[MatcherIndex++];
2882 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2883 if (CaseSize == 0) break;
2885 uint16_t Opc = MatcherTable[MatcherIndex++];
2886 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2888 // If the opcode matches, then we will execute this case.
2889 if (CurNodeOpcode == Opc)
2892 // Otherwise, skip over this case.
2893 MatcherIndex += CaseSize;
2896 // If no cases matched, bail out.
2897 if (CaseSize == 0) break;
2899 // Otherwise, execute the case we found.
2900 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2901 << " to " << MatcherIndex << "\n");
2905 case OPC_SwitchType: {
2906 MVT CurNodeVT = N.getSimpleValueType();
2907 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2910 // Get the size of this case.
2911 CaseSize = MatcherTable[MatcherIndex++];
2913 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2914 if (CaseSize == 0) break;
2916 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2917 if (CaseVT == MVT::iPTR)
2918 CaseVT = TLI->getPointerTy();
2920 // If the VT matches, then we will execute this case.
2921 if (CurNodeVT == CaseVT)
2924 // Otherwise, skip over this case.
2925 MatcherIndex += CaseSize;
2928 // If no cases matched, bail out.
2929 if (CaseSize == 0) break;
2931 // Otherwise, execute the case we found.
2932 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2933 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2936 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2937 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2938 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2939 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2940 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2941 Opcode-OPC_CheckChild0Type))
2944 case OPC_CheckCondCode:
2945 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2947 case OPC_CheckValueType:
2948 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2951 case OPC_CheckInteger:
2952 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2954 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2955 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2956 case OPC_CheckChild4Integer:
2957 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2958 Opcode-OPC_CheckChild0Integer)) break;
2960 case OPC_CheckAndImm:
2961 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2963 case OPC_CheckOrImm:
2964 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2967 case OPC_CheckFoldableChainNode: {
2968 assert(NodeStack.size() != 1 && "No parent node");
2969 // Verify that all intermediate nodes between the root and this one have
2971 bool HasMultipleUses = false;
2972 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2973 if (!NodeStack[i].hasOneUse()) {
2974 HasMultipleUses = true;
2977 if (HasMultipleUses) break;
2979 // Check to see that the target thinks this is profitable to fold and that
2980 // we can fold it without inducing cycles in the graph.
2981 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2983 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2984 NodeToMatch, OptLevel,
2985 true/*We validate our own chains*/))
2990 case OPC_EmitInteger: {
2991 MVT::SimpleValueType VT =
2992 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2993 int64_t Val = MatcherTable[MatcherIndex++];
2995 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2996 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2997 CurDAG->getTargetConstant(Val, VT), nullptr));
3000 case OPC_EmitRegister: {
3001 MVT::SimpleValueType VT =
3002 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3003 unsigned RegNo = MatcherTable[MatcherIndex++];
3004 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3005 CurDAG->getRegister(RegNo, VT), nullptr));
3008 case OPC_EmitRegister2: {
3009 // For targets w/ more than 256 register names, the register enum
3010 // values are stored in two bytes in the matcher table (just like
3012 MVT::SimpleValueType VT =
3013 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3014 unsigned RegNo = MatcherTable[MatcherIndex++];
3015 RegNo |= MatcherTable[MatcherIndex++] << 8;
3016 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3017 CurDAG->getRegister(RegNo, VT), nullptr));
3021 case OPC_EmitConvertToTarget: {
3022 // Convert from IMM/FPIMM to target version.
3023 unsigned RecNo = MatcherTable[MatcherIndex++];
3024 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3025 SDValue Imm = RecordedNodes[RecNo].first;
3027 if (Imm->getOpcode() == ISD::Constant) {
3028 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3029 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
3030 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3031 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3032 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
3035 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3039 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3040 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3041 // These are space-optimized forms of OPC_EmitMergeInputChains.
3042 assert(!InputChain.getNode() &&
3043 "EmitMergeInputChains should be the first chain producing node");
3044 assert(ChainNodesMatched.empty() &&
3045 "Should only have one EmitMergeInputChains per match");
3047 // Read all of the chained nodes.
3048 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3049 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3050 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3052 // FIXME: What if other value results of the node have uses not matched
3054 if (ChainNodesMatched.back() != NodeToMatch &&
3055 !RecordedNodes[RecNo].first.hasOneUse()) {
3056 ChainNodesMatched.clear();
3060 // Merge the input chains if they are not intra-pattern references.
3061 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3063 if (!InputChain.getNode())
3064 break; // Failed to merge.
3068 case OPC_EmitMergeInputChains: {
3069 assert(!InputChain.getNode() &&
3070 "EmitMergeInputChains should be the first chain producing node");
3071 // This node gets a list of nodes we matched in the input that have
3072 // chains. We want to token factor all of the input chains to these nodes
3073 // together. However, if any of the input chains is actually one of the
3074 // nodes matched in this pattern, then we have an intra-match reference.
3075 // Ignore these because the newly token factored chain should not refer to
3077 unsigned NumChains = MatcherTable[MatcherIndex++];
3078 assert(NumChains != 0 && "Can't TF zero chains");
3080 assert(ChainNodesMatched.empty() &&
3081 "Should only have one EmitMergeInputChains per match");
3083 // Read all of the chained nodes.
3084 for (unsigned i = 0; i != NumChains; ++i) {
3085 unsigned RecNo = MatcherTable[MatcherIndex++];
3086 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3087 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3089 // FIXME: What if other value results of the node have uses not matched
3091 if (ChainNodesMatched.back() != NodeToMatch &&
3092 !RecordedNodes[RecNo].first.hasOneUse()) {
3093 ChainNodesMatched.clear();
3098 // If the inner loop broke out, the match fails.
3099 if (ChainNodesMatched.empty())
3102 // Merge the input chains if they are not intra-pattern references.
3103 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3105 if (!InputChain.getNode())
3106 break; // Failed to merge.
3111 case OPC_EmitCopyToReg: {
3112 unsigned RecNo = MatcherTable[MatcherIndex++];
3113 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3114 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3116 if (!InputChain.getNode())
3117 InputChain = CurDAG->getEntryNode();
3119 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3120 DestPhysReg, RecordedNodes[RecNo].first,
3123 InputGlue = InputChain.getValue(1);
3127 case OPC_EmitNodeXForm: {
3128 unsigned XFormNo = MatcherTable[MatcherIndex++];
3129 unsigned RecNo = MatcherTable[MatcherIndex++];
3130 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3131 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3132 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3137 case OPC_MorphNodeTo: {
3138 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3139 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3140 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3141 // Get the result VT list.
3142 unsigned NumVTs = MatcherTable[MatcherIndex++];
3143 SmallVector<EVT, 4> VTs;
3144 for (unsigned i = 0; i != NumVTs; ++i) {
3145 MVT::SimpleValueType VT =
3146 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3147 if (VT == MVT::iPTR)
3148 VT = TLI->getPointerTy().SimpleTy;
3152 if (EmitNodeInfo & OPFL_Chain)
3153 VTs.push_back(MVT::Other);
3154 if (EmitNodeInfo & OPFL_GlueOutput)
3155 VTs.push_back(MVT::Glue);
3157 // This is hot code, so optimize the two most common cases of 1 and 2
3160 if (VTs.size() == 1)
3161 VTList = CurDAG->getVTList(VTs[0]);
3162 else if (VTs.size() == 2)
3163 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3165 VTList = CurDAG->getVTList(VTs);
3167 // Get the operand list.
3168 unsigned NumOps = MatcherTable[MatcherIndex++];
3169 SmallVector<SDValue, 8> Ops;
3170 for (unsigned i = 0; i != NumOps; ++i) {
3171 unsigned RecNo = MatcherTable[MatcherIndex++];
3173 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3175 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3176 Ops.push_back(RecordedNodes[RecNo].first);
3179 // If there are variadic operands to add, handle them now.
3180 if (EmitNodeInfo & OPFL_VariadicInfo) {
3181 // Determine the start index to copy from.
3182 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3183 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3184 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3185 "Invalid variadic node");
3186 // Copy all of the variadic operands, not including a potential glue
3188 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3190 SDValue V = NodeToMatch->getOperand(i);
3191 if (V.getValueType() == MVT::Glue) break;
3196 // If this has chain/glue inputs, add them.
3197 if (EmitNodeInfo & OPFL_Chain)
3198 Ops.push_back(InputChain);
3199 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3200 Ops.push_back(InputGlue);
3203 SDNode *Res = nullptr;
3204 if (Opcode != OPC_MorphNodeTo) {
3205 // If this is a normal EmitNode command, just create the new node and
3206 // add the results to the RecordedNodes list.
3207 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3210 // Add all the non-glue/non-chain results to the RecordedNodes list.
3211 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3212 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3213 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3217 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3218 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3220 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3221 // We will visit the equivalent node later.
3222 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3226 // If the node had chain/glue results, update our notion of the current
3228 if (EmitNodeInfo & OPFL_GlueOutput) {
3229 InputGlue = SDValue(Res, VTs.size()-1);
3230 if (EmitNodeInfo & OPFL_Chain)
3231 InputChain = SDValue(Res, VTs.size()-2);
3232 } else if (EmitNodeInfo & OPFL_Chain)
3233 InputChain = SDValue(Res, VTs.size()-1);
3235 // If the OPFL_MemRefs glue is set on this node, slap all of the
3236 // accumulated memrefs onto it.
3238 // FIXME: This is vastly incorrect for patterns with multiple outputs
3239 // instructions that access memory and for ComplexPatterns that match
3241 if (EmitNodeInfo & OPFL_MemRefs) {
3242 // Only attach load or store memory operands if the generated
3243 // instruction may load or store.
3244 const MCInstrDesc &MCID = TII->get(TargetOpc);
3245 bool mayLoad = MCID.mayLoad();
3246 bool mayStore = MCID.mayStore();
3248 unsigned NumMemRefs = 0;
3249 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3250 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3251 if ((*I)->isLoad()) {
3254 } else if ((*I)->isStore()) {
3262 MachineSDNode::mmo_iterator MemRefs =
3263 MF->allocateMemRefsArray(NumMemRefs);
3265 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3266 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3267 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3268 if ((*I)->isLoad()) {
3271 } else if ((*I)->isStore()) {
3279 cast<MachineSDNode>(Res)
3280 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3284 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3285 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3287 // If this was a MorphNodeTo then we're completely done!
3288 if (Opcode == OPC_MorphNodeTo) {
3289 // Update chain and glue uses.
3290 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3291 InputGlue, GlueResultNodesMatched, true);
3298 case OPC_MarkGlueResults: {
3299 unsigned NumNodes = MatcherTable[MatcherIndex++];
3301 // Read and remember all the glue-result nodes.
3302 for (unsigned i = 0; i != NumNodes; ++i) {
3303 unsigned RecNo = MatcherTable[MatcherIndex++];
3305 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3307 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3308 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3313 case OPC_CompleteMatch: {
3314 // The match has been completed, and any new nodes (if any) have been
3315 // created. Patch up references to the matched dag to use the newly
3317 unsigned NumResults = MatcherTable[MatcherIndex++];
3319 for (unsigned i = 0; i != NumResults; ++i) {
3320 unsigned ResSlot = MatcherTable[MatcherIndex++];
3322 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3324 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3325 SDValue Res = RecordedNodes[ResSlot].first;
3327 assert(i < NodeToMatch->getNumValues() &&
3328 NodeToMatch->getValueType(i) != MVT::Other &&
3329 NodeToMatch->getValueType(i) != MVT::Glue &&
3330 "Invalid number of results to complete!");
3331 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3332 NodeToMatch->getValueType(i) == MVT::iPTR ||
3333 Res.getValueType() == MVT::iPTR ||
3334 NodeToMatch->getValueType(i).getSizeInBits() ==
3335 Res.getValueType().getSizeInBits()) &&
3336 "invalid replacement");
3337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3340 // If the root node defines glue, add it to the glue nodes to update list.
3341 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3342 GlueResultNodesMatched.push_back(NodeToMatch);
3344 // Update chain and glue uses.
3345 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3346 InputGlue, GlueResultNodesMatched, false);
3348 assert(NodeToMatch->use_empty() &&
3349 "Didn't replace all uses of the node?");
3351 // FIXME: We just return here, which interacts correctly with SelectRoot
3352 // above. We should fix this to not return an SDNode* anymore.
3357 // If the code reached this point, then the match failed. See if there is
3358 // another child to try in the current 'Scope', otherwise pop it until we
3359 // find a case to check.
3360 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3361 ++NumDAGIselRetries;
3363 if (MatchScopes.empty()) {
3364 CannotYetSelect(NodeToMatch);
3368 // Restore the interpreter state back to the point where the scope was
3370 MatchScope &LastScope = MatchScopes.back();
3371 RecordedNodes.resize(LastScope.NumRecordedNodes);
3373 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3374 N = NodeStack.back();
3376 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3377 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3378 MatcherIndex = LastScope.FailIndex;
3380 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3382 InputChain = LastScope.InputChain;
3383 InputGlue = LastScope.InputGlue;
3384 if (!LastScope.HasChainNodesMatched)
3385 ChainNodesMatched.clear();
3386 if (!LastScope.HasGlueResultNodesMatched)
3387 GlueResultNodesMatched.clear();
3389 // Check to see what the offset is at the new MatcherIndex. If it is zero
3390 // we have reached the end of this scope, otherwise we have another child
3391 // in the current scope to try.
3392 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3393 if (NumToSkip & 128)
3394 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3396 // If we have another child in this scope to match, update FailIndex and
3398 if (NumToSkip != 0) {
3399 LastScope.FailIndex = MatcherIndex+NumToSkip;
3403 // End of this scope, pop it and try the next child in the containing
3405 MatchScopes.pop_back();
3412 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3414 raw_string_ostream Msg(msg);
3415 Msg << "Cannot select: ";
3417 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3418 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3419 N->getOpcode() != ISD::INTRINSIC_VOID) {
3420 N->printrFull(Msg, CurDAG);
3421 Msg << "\nIn function: " << MF->getName();
3423 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3425 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3426 if (iid < Intrinsic::num_intrinsics)
3427 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3428 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3429 Msg << "target intrinsic %" << TII->getName(iid);
3431 Msg << "unknown intrinsic #" << iid;
3433 report_fatal_error(Msg.str());
3436 char SelectionDAGISel::ID = 0;